NCV57001FDWR2G [ONSEMI]
Isolated high current and high efficiency IGBT gate driver with internal galvanic isolation;
| 型号： | NCV57001FDWR2G |
| 厂家： | 
ONSEMI |
| 描述： | Isolated high current and high efficiency IGBT gate driver with internal galvanic isolation 双极性晶体管 |
| 文件： | 总19页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Isolated High Current IGBT
Gate Driver
1
SOIC−16 WB
CASE 751G−03
NCV57001F
NCV57001F is a variant of NCV57001 with reduced
Soft−Turn−Off time suited to drive large IGBTs or power modules.
NCV57001F is a high−current single channel IGBT driver with
internal galvanic isolation, designed for high system efficiency and
reliability in high power applications. Its features include
complementary inputs, open drain FAULT and Ready outputs, active
Miller clamp, accurate UVLOs, DESAT protection, and soft turn−off
at DESAT. NCV57001F accommodates both 5 V and 3.3 V signals on
the input side and wide bias voltage range on the driver side including
negative voltage capability. NCV57001F provides >5 kVrms
MARKING DIAGRAM
NCV57001F
DWR2G
AWLYYWWG
NCV57001FDWR2G = Specific Device Code
(UL1577 rating) galvanic isolation and >1200 V
(working
IORM
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
voltage) capabilities. NCV57001F is available in the wide−body
SOIC−16 package with guaranteed 8 mm creepage distance between
input and output to fulfill reinforced safety insulation requirements.
Features
• High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages
• Low Output Impedance for Enhanced IGBT Driving
• Short Propagation Delays with Accurate Matching
• Active Miller Clamp to Prevent Spurious Gate Turn−on
• DESAT Protection with Programmable Delay
• Typ 550 ns Soft Turn Off during IGBT Short Circuit
• IGBT Gate Clamping during Short Circuit
• IGBT Gate Active Pull Down
PIN CONNECTIONS
VEE2A
DESAT
GND2
N/C
GND1
VDD1
RST
FLT
VDD2
OUT
RDY
IN−
• Tight UVLO Thresholds for Bias Flexibility
• Wide Bias Voltage Range including Negative VEE2
• 3.3 V to 5 V Input Supply Voltage
CLAMP
VEE2
IN+
GND1A
• 5000 V Galvanic Isolation (to meet UL1577 requirements)
• 1200 V Working Voltage (per VDE0884−10 requirements)
• High transient immunity
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
• High electromagnetic immunity
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Typical Applications
• Automotive Power Supplies
• HEV/EV Powertrain
• BSG Inverter
• PTC Heater
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
August, 2021 − Rev. 2
NCV57001F/D
NCV57001F
VDD1
VDD2
VDD1
UVLO2
UVLO1
VCLAMP−THR
+
−
CLAMP
IN−
IN+
VEE2
STO
VDD1
RDY
OUT
Logic
Logic
1
VDD2
IDESAT−CHG
VDD1
+
DESAT
GND2
RST
RS
−
VDD1
VDESAT−THR
2
GND1
1
VEE2
GND1A
VEE2A
Figure 1. Simplified Block Diagram
+V2
V1
VDD1
IN+
VDD2
DESAT
IN−
OUT
RDY
CLAMP
VEE2
FLT
RST
−V2
GND1
GND2
GND1
GND2
Figure 2. Simplified Application Schematics
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2
NCV57001F
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
No.
1
I/O
Description
V
EE2A
Power
Output side negative power supply. A good quality bypassing capacitor is
required from these pins to GND2 and should be placed close to the pins for
best results. Connect it to GND2 for unipolar supply application.
V
EE2
8
DESAT
2
I/O
Input for detecting the desaturation of IGBT due to a short circuit condition.
An internal constant current source I
charging an external capacitor
−
DESAT CHG
connected to this pin allows a programmable blanking delay every ON cycle
before DESAT fault is processed, thus preventing false triggering. When the
DESAT voltage goes up and reaches V
, the output is driven low.
−
DESAT THR
Further, the FLT output is activated, please refer to Figure 5.
A 5 ms mute time apply to IN+ and IN− once DESAT occurs.
Output side gate drive reference connecting to IGBT emitter or FET source.
Not connected.
GND2
N/C
3
4
5
Power
−−
V
DD2
Power
Output side positive power supply. The operating range for this pin is from
UVLO2 to its maximum allowed value. A good quality bypassing capacitor is
required from this pin to GND2 and should be placed close to the pins for best
results.
OUT
6
7
O
Driver output that provides the appropriate drive voltage and source/sink current
to the IGBT/FET gate. OUT is actively pulled low during start−up and under
Fault conditions.
CLAMP
I/O
Provides clamping for the IGBT/FET gate during the off period to protect it from
parasitic turn−on. Its internal N FET is turned on when the voltage of this pin falls
below V
+ V
. It is to be tied directly to IGBT/FET gate with
−
EE2
CLAMP THR
minimum trace length for best results.
GND1
IN+
9
Power
I
Input side ground reference.
16
10
Non inverted gate driver input. It is internally clamped to V
and has
DD1
a pull−down resistor of 50 kW to ensure that output is low in the absence of an
input signal. A minimum positive going pulse−width is required at IN+ before
OUT responds.
IN−
11
12
I
Inverted gate driver input. It is internally clamped to V
resistor of 50 kW to ensure that output is low in the absence of an input signal.
A minimum negative going pulse−width is required at IN− before OUT responds.
and has a pull−up
DD1
RDY
O
Power good indication output, active high when V
is good. There is
DD2
an internal 50 kW pull−up resistor connected to this pin. Multiple of them from
different drivers can be “OR”ed together.
If a low RDY event is triggered by UVLO2, the maximum low duration for RDY is
200 ns.
OUT remains low when RDY is low. Short time delay may apply. See Figure 4
for details.
FLT
13
O
Fault output (active low) that allows communication to the main controller that
the driver has encountered a desaturation condition and has deactivated the
output.
RST
14
15
I
Reset input with an internal 50 kW pull−up resistor, active low to reset fault latch.
V
DD1
Power
Input side power supply (3.3 V to 5 V).
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NCV57001F
Table 2. SAFETY AND INSULATION RATINGS
Symbol
Parameter
Min
I − IV
I − IV
I − IV
I − IV
I − III
600
Unit
Installation Classifications per DIN VDE 0110/1.89
Table 1 Rated Mains Voltage
< 150 V
< 300 V
< 450 V
< 600 V
RMS
RMS
RMS
RMS
< 1000 V
RMS
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
Climatic Classification
40/100/21
2
Polution Degree (DIN VDE 0110/1.89)
V
Input−to−Output Test Voltage, Method b, V
x 1.875 = V , 100% Production Test
2250
V
V
V
PR
IORM
PR
pk
pk
pk
with tm = 1 s, Partial Discharge < 5 pC
Input−to−Output Test Voltage, Method a, V
x 1.6 = V , Type
−
IORM
PR
and Sample Test with tm = 10 s, Partial Discharge < 5 pC
V
IORM
Maximum Repetitive Peak Voltage
1200
870
8400
8.0
V
IOWM
Maximum Working Insulation Voltage
V
RMS
V
IOTM
Highest Allowable Over Voltage
V
pk
E
CR
External Creepage
mm
mm
um
°C
E
External Clearance
8.0
CL
DTI
Insulation Thickness
17.3
150
36
T
Case
Safety Limit Values – Maximum Values in Failure; Case Temperature
Safety Limit Values – Maximum Values in Failure; Input Power
Safety Limit Values – Maximum Values in Failure; Output Power
P
mW
mW
W
S,INPUT
P
1364
S,OUTPUT
9
R
Insulation Resistance at TS, V = 500 V
10
IO
IO
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NCV57001F
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) Over operating free−air temperature range unless otherwise noted
Symbol
Parameter
Minimum
−0.3
−0.3
−10
Maximum
Unit
V
V
V
−GND1
Supply voltage, input side
6
DD1
DD2
−GND2
−GND2
Positive Power Supply, output side
Negative Power Supply, output side
Differential Power Supply, output side
25
0.3
25
V
V
V
EE2
V
−V
MAX2
0
V
DD2
EE2
(V
)
V
Gate−driver output voltage
V
EE2
− 0.3
V + 0.3
DD2
V
A
OUT
I
Gate−driver output sourcing current (maximum pulse
width = 10 ms, maximum duty cycle = 0.2%, V
7.8
−
PK SRC
= 20 V)
MAX2
I
Gate−driver output sinking current (maximum pulse
width = 10 ms, maximum duty cycle = 0.2%, V
7.1
2.5
10
A
A
−
PK SNK
= 20 V)
MAX2
I
Clamp sinking current (maximum pulse width = 10 ms,
maximum duty cycle = 0.2%, V = 3 V)
−
PK CLAMP
CLAMP
t
Maximum Short Circuit Clamping Time
(I = 500 mA)
ms
CLP
OUT_CLAMP
V
−GND1
Voltage at IN+, IN−, RST, FLT, RDY
Output current of FLT, RDY
Desat Voltage
−0.3
V
+ 0.3
V
mA
V
LIM
DD1
I
−GND1
10
LIM
V
−GND2
−GND2
−0.3
− 0.3
V
DD2
V
DD2
+ 0.3
DESAT
CLAMP
V
Clamp Voltage
V
+ 0.3
V
EE2
PD
Power Dissipation
SOIC−16 wide package
mW
TJ(max)
TSTG
Maximum Junction Temperature
−40
−65
150
°C
°C
kV
kV
−
Storage Temperature Range
150
2
ESDHBM
ESDCDM
MSL
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Moisture Sensitivity Level
2
1
T
SLD
Lead Temperature Soldering Reflow, Pb−Free Versions
(Note 3)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 25°C.
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Value
114
Unit
2
RJA
Thermal Resistance,
Junction−to−Air
100 mm , 1 oz Copper, 1 Surface Layer
°C/W
2
650 mm , 1 oz Copper, 2 Surface Layers and
62
2 Internal Power Plane Layers
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2
2
5. Values based on copper area of 100 mm (or 0.16 in ) of 1 oz copper thickness and FR4 PCB substrate.
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5
NCV57001F
Table 5. OPERATING RANGES (Note 6)
Symbol
Parameter
Min
UVLO1
UVLO2
−10
Max
5.5
24
0
Unit
V
V
V
−GND1
−GND2
−GND2
Supply voltage, input side
DD1
Positive Power Supply, output side
Negative Power Supply, output side
V
DD2
V
V
EE2
V
−V
MAX2
Differential Power Supply, output side
0
24
V
DD2
EE2
(V
)
V
Low level input voltage at IN+, IN−, RST
High level input voltage at IN+, IN−, RST
Common Mode Transient Immunity (1500 V)
Ambient Temperature
0
0.3 × V
V
V
IL
DD1
V
DD1
V
IH
0.7 × V
DD1
|dV /dt|
100
kV/ms
°C
ISO
TA
−40
125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
ISOLATION CHARACTERISTICS
Symbol
Parameter
Conditions
T = 25°C, Relative Humidity < 50%, t = 1.0
Min
Typ
Max
Unit
V
Input−Output
Isolation Voltage
5000
−
−
V
RMS
ISO, input−output
A
minute, I
10 A, 50 Hz (See Note 7, 8, 9)
I−O
11
R
Isolation
Resistance
V
I−O
= 500 V (See Note 7)
−
10
−
W
ISO
7. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together
8. 5,000 V for 1−minute duration is equivalent to 6,000 V for 1−second duration.
RMS
RMS
9. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN VDE V 0884−11 Safety and Insulation
Ratings Table
Table 6. ELECTRICAL CHARACTERISTICS (V
= 5 V, V
= 15 V, V
= −8 V.)
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
VOLTAGE SUPPLY
Parameter
Test Conditions
Min
Typ
Max
Unit
V
UVLO1 Output Enabled
UVLO1 Output Disabled
UVLO1 Hysteresis
3.0
V
V
UVLO1−OUT−ON
V
2.4
0.125
13.2
12.2
UVLO1−OUT−OFF
V
V
UVLO1−HYST
V
UVLO2 Output Enabled
UVLO2 Output Disabled
UVLO2 Hysteresis
13.5
12.5
1
13.8
12.8
V
UVLO2−OUT−ON
UVLO2−OUT−OFF
V
V
V
V
UVLO2−HYST
I
Input Supply Quiescent Current
Output Low
IN+ = Low, IN− = Low
1
2
6
4
mA
DD1−0
RDY = High, FLT = High
IN+ = High, IN− = Low
I
Input Supply Quiescent Current
Output High
4.8
3.3
mA
mA
DD1−100
RDY = High, FLT = High
IN+ = Low, IN− = Low
I
Output Positive Supply
Quiescent Current,
Output Low
DD2−0
RDY = High, FLT = High, no load
IN+ = High, IN− = Low
I
I
Output Positive Supply
Quiescent Current,
Output High
4
5
mA
DD2−100
RDY = High, FLT = High, no load
IN+ = High, IN− = Low, no load
I
Output Negative Supply
Quiescent Current, Output Low
0.4
0.2
2
2
mA
mA
EE2−0
Output Negative Supply
Quiescent Current, Output High
IN+ = High, IN− = Low, no load
EE2−100
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NCV57001F
Table 6. ELECTRICAL CHARACTERISTICS (V
= 5 V, V
= 15 V, V
= −8 V.) (continued)
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
LOGIC INPUT AND OUTPUT
Parameter
Test Conditions
Min
Typ
Max
Unit
V
IN+, IN−, RST Low Input
0.3 ×
V
DD1
V
V
V
IL
Voltage
V
IH
IN+, IN−, RST High Input
Voltage
0.7 ×
V
DD1
V
Input Hysteresis Voltage
0.15
IN−HYST
×
V
DD1
I
, I
IN−, RST Input current
(50 kW pull−up resistor)
V
V
V
/V = 0 V
−100
mA
mA
mA
V
IN−L RST−L
IN− RST
I
IN+ Input Current
(50 kW pull−down resistor)
= 5 V
IN+
100
100
IN+H
I
, I
RDY, FLT Pull−up Current
(50 kW pull−up resistor)
/V = Low
RDY FLT
RDY−L FLT−L
V
, V
RDY, FLT Low Level Output
Voltage
I
/I = 5 mA
0.3
10
RDY−L
FLT−L
RDY FLT
t
t
Input Pulse Width of IN+, IN− for
No Response at Output
ns
ns
ns
ON−MIN1
ON−MIN2
Input Pulse Width of IN+, IN− for
Guaranteed Response at Output
30
t
Pulse Width of RST for
Resetting FLT
800
RST−MIN
DRIVER OUTPUT
V
V
Output Low State
I
I
I
I
= 200 mA
0.1
0.5
0.3
0.8
7.1
0.2
0.8
0.5
1
V
V
OUTL1
OUTL3
OUTH1
OUTH3
SINK
SINK
SRC
SRC
(V
– V
)
OUT
EE2
= 1.0 A, T = 25°C
A
V
V
Output High State
(V – V
= 200 mA
)
OUT
DD2
= 1.0 A, T = 25°C
A
I
Peak Driver Current, Sink
(Note 10)
V
= 7.9 V
A
A
PK−SNK1
OUT
I
Peak Driver Current, Source
(Note 10)
V
= −5 V
7.8
PK−SRC1
OUT
MILLER CLAMP
V
Clamp Voltage
I
I
= 2.5 A, T = 25°C
1.3
1.7
2.5
V
CLAMP
CLAMP
A
= 2.5 A, T = −40°C to
CLAMP
125°C
A
V
Clamp Activation Threshold
1.5
2
2.5
1
V
V
CLAMP−THR
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage
(V – V
V
IN+ = Low, IN− = High,
= 500 mA
0.9
CLAMP−OUT
I
OUT
)
DD2
OUT
(pulse test, t
= 10 ms)
CLPmax
V
Clamping Voltage, Clamp
(V − V
IN+ = High, IN− = Low,
I = 500 mA
CLAMP−CLAMP
1.4
1.5
V
CLAMP−CLAMP
)
CLAMP
DD2
(pulse test, t
= 10 ms)
CLPmax
DESAT PROTECTION
V
DESAT Threshold Voltage
Blanking Charge Current
Blanking Discharge Current
8.5
9
9.5
V
DESAT−THR
DESAT−CHG
I
V
DESAT
= 7 V
0.45
0.5
50
0.55
mA
mA
I
DESAT−DIS
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NCV57001F
Table 6. ELECTRICAL CHARACTERISTICS (V
= 5 V, V
= 15 V, V
= −8 V.) (continued)
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
DYNAMIC CHARACTERISTIC
Parameter
Test Conditions
Min
Typ
Max
Unit
t
IN+, IN− to Output High
Propagation Delay
C
= 10 nF
LOAD
to 10% of output change for PW
40
60
90
ns
PD−ON
V
IH
> 150 ns. OUT and CLAMP pins are
connected together
t
IN+, IN− to Output Low
C
= 10 nF
LOAD
to 90% of output change for PW
40
66
90
ns
ns
PD−OFF
Propagation Delay
V
IL
> 150 ns. OUT and CLAMP pins are
connected together
t
Propagation Delay Distortion
(= t − t
T = 25°C, PW >150 ns
A
−15
−25
−30
−6
15
25
30
DISTORT
)
PD−OFF
PD−ON
T = −40°C to 125°C, PW > 150 ns
A
t
Prop Delay Distortion between
Parts
PW > 150 ns
0
ns
ns
ns
ns
ns
ns
DISTORT_TOT
t
t
Rise Time (see Figure 3)
C
= 1 nF, 10% to 90% of
LOAD
14
RISE
Output Change
Fall Time (see Figure 3)
C
= 1 nF, 90% to 10% of
19
FALL
LOAD
Output Change
t
DESAT Leading Edge Blanking
Time (See Figure 5)
450
370
550
LEB
t
DESAT Threshold Filtering Time
(see Figure 5)
FILTER
t
Soft Turn Off Time (see Figure 5)
C
= 10 nF, R = 10 W.
G
STO
LOAD
V
EE2
= 0 V
C
= 10 nF, R = 10 W
750
450
5
LOAD
G
t
Delay after t
to FLT
1000
ns
ms
ns
ns
FLT
FILTER
t
Input Mute Time after t
FILTER
MUTE
t
RST Rise to FLT Rise Delay
23
55
100
100
RST
t
t
RDY High to Output High Delays
(see Figure 4)
RDY1O
RDY2O
t
t
V
to RDY Low
6
8
15
ms
RDY1F
RDY2F
UVLO2−OUT−OFF
Delays (see Figure 4)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10.Values based on design and/or characterization.
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NCV57001F
V
IH
IL
IN+
V
t
t
t
MIN
FALL
RISE
90%
t
PD−ON
t
MIN
t
PD−OFF
10%
Figure 3. Simplified Block Diagram
RDY
RDY
t
t
RDY1F
RDY2F
IN+
IN+
V
UVLO2−OUT−ON
V
UVLO2−OUT−OFF
V
V
UVLO1−OUT−ON
V
DD1
UVLO1−OUT−OFF
V
DD2
V
t
t
UVLO2−OUT−ON
RDY2O
RDY1O
OUT
V
UVLO2−OUT−OFF
OUT
Figure 4. Simplified Block Diagram
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NCV57001F
IN+
t
MUTE
t
PD−ON
t
FILTER
V
EE2
+ 2V
V
OUT
t
STO
V
DESAT−THR
t
LEB
DESAT
t
FLT
FLT
t
RST
RST
t
RST−MIN
Figure 5. UVLO Waveform
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NCV57001F
FEATURE DESCRIPTIONS
Under Voltage Lockout (UVLO)
UVLO ensures correct switching of IGBT connected to
the driver output.
• The IGBT is turned−off, if the supply V
drops
CC2
below V
to low.
and the RDY pin output goes
UVLO2−OUT−OFF
• The IGBT is turned−off, if the supply V
drops
CC1
• The driver output does not start to react to the input
below V
to low.
and the RDY pin output goes
UVLO1−OUT−OFF
signal on V until the V rises above the
IN
UVLO1−OUT−ON
CC1
V
again. If the supply V
increases
DD1
• The driver output does not start to react to the input
over V
, the RDY pin output goes to be
UVLO1−OUT−ON
signal on V until the V rises above the
open−drain and outputs continue to switch IGBT
IN
UVLO1−OUT−ON
CC1
V
again. If the supply V
increase
CC1
• VEE2 is not monitored.
over V
, the RDY pin output goes to be
UVLO1−OUT−ON
open−drain and outputs continue to switch IGBT
RDY
tRDY2
RDY
IN+
tRDY1F
tRDY2R
IN+
VUVLO2-OUT-ON
VUVLO2-OUT-OFF
VUVLO1-OUT-ON
VUVLO1-OUT-OFF
VDD1
VDD2
VUVLO2-OUT-ON
VUVLO2-OUT-OFF
OUTH
/OUTL
OUTH
/OUTL
Figure 6. UVLO Diagram
Active Miller Clamp Protection (CLAMP)
For operation with unipolar supply, typically, V
=
DD2
NCV57001F supports both bipolar and unipolar power
supply with active Miller clamp.
15 V with respect to GND , and V
= GND . In this case,
2
EE2
2
the IGBT can turn on due to additional charge from IGBT
Miller capacitance caused by a high voltage slew rate
transition on the IGBT collector. To prevent IGBT to turn on,
the CLAMP pin is connected directly to IGBT gate and
Miller current is sinked through a low impedance CLAMP
transistor. When the IGBT is turned−off and the gate voltage
For operation with bipolar supplies, the IGBT is turned off
with a negative voltage through OUTL with respect to its
emitter. This prevents the IGBT from unintentionally
turning on because of current induced from its collector to
its gate due to Miller effect. In this condition it is not
necessary to connect CLAMP output of the gate driver to the
IGBT gate, but connecting CLAMP output to the IGBT gate
is also not an issue. Typical values for bipolar operation are
transitions below V , the CLAMP current output is
CLAMP
activated.
V
DD2
= 15 V and V = −5 V with respect to GND .
EE2 2
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11
NCV57001F
Figure 7. Current Path without Miler Clamp Protection
Figure 8. Current Path with Miler Clamp Protection
Non−inverting and Inverting Input Pin (IN+, IN−)
NCV57001F has two possible input modes to control
IGBT. Both inputs have defined minimum input pulse width
to filter occasional glitches.
• Non−inverting input IN+ controls the driver output
while inverting input IN− is set to LOW
Desaturation Protection (DESAT)
Desaturation protection ensures the protection of IGBT at
short circuit. When the V
voltage goes up and reaches
CESAT
the set limit, the output is driven low and /FLT output is
activated. Blanking time can be set by internal current
source and an external capacitor. To avoid false DESAT
triggering and minimize blanking time, fast switching
diodes with low internal capacitance are recommended. All
DESAT protective diodes internal capacitances builds
voltage divider with the blanking capacitor.
• Inverting input IN− controls the driver output while
non−inverting input IN+ is set to HIGH
Warning: When the application use an independent or
separate power supply for the control unit ant the input
side of the driver, all inputs should be protected by a
serial resistor (In case of a power failure of the driver, the
driver may be damaged due to overloading of the input
protection circuits)
Warning: Both external protective diodes are
recommended for the protection against voltage spikes
caused by IGBT transients passing through parasitic
capacitances.
DESAT Circuit Parameters Specification
VDESAT−THR
IDESAT−CHG
t
BLANK + CBLANK
@
V
DESAT−THR u RS−DESAT @ IDESAT−CHG ) VF HV diode ) VCESAT_IGBT
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12
NCV57001F
VDD2
I
DESAT-CH G
HS-IGBT
VDD1
V
DESAT
DESAT
+
-
R
S-DESAT
HV diode
Control
Logic
C
BL ANK
V
DESAT-THR
Vo
FLT
I
DESAT-DIS
RG
QDIS
LS-IGBT
GND2
GND1
GND2
GND1
Figure 9. DESAT Protection Schematic
A
IN+
tPD-ON
tMUTE
tFILTER
VOUTH/L
VEE2 + 2V
tOUT-C
VDESAT -THR
tLEB
DESAT
FLT
tFLT
tRST
RST
tRST-MIN
Figure 10. DESAT Switch Off Behavior
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13
NCV57001F
Fault Output Pin (FLT)
RESET Input
FLT open−drain output provides feedback to the
controller about driver DESAT protection conditions. The
open−drain FLT outputs of multiple NCV57001F devices
can be wired together forming a single, common fault bus
for interfacing directly to the microcontroller. FLT output
has 50kΩ internal pull−up resistor to VDD1.
• FLT input is used to set back FLT output after DESAT
conditions disappear
Warning: When the application use an independent or
separate power supply for the control unit ant the input
side of the driver, all inputs should be protected by a
serial resistor (In case of a power failure of the driver, the
driver may be damaged due to overloading of the input
protection circuits)
Ready Output Pin (RDY)
RDY open−drain output provides feedback to the
controller about driver UVLO and TSD protections
conditions.
• If either side of device have insufficient supply (VDD1
or VDD2), the RDY pin output goes low; otherwise,
RDY pin output is open drain.
• If the temperature crosses the TSD threshold, the RDY
pin output goes low; otherwise, RDY pin output is open
drain.
Power Supply (VDD1, VDD2, VEE2)
NCV57001F is designed to support two different power
supply configurations, bipolar or unipolar power supply. For
reliable high output current the suitable external power
capacitors required. Parallel combination of 100 nF + 4.7 mF
ceramic capacitors is optimal for a wide range of
applications using IGBT. For reliable driving IGBT
modules (containing several parallel IGBT’s) is a higher
capacity required (typically 100 nF + 10 mF). Capacitors
should be as close as possible to the driver’s power pins.
The open−drain RDY outputs of multiple NCV57001F
devices can be “OR”ed together.
• In bipolar power supply the driver is typically supplied
with a positive voltage of 15 V at VDD2 and negative
voltage −5 V at VEE2 (Figure 11). Negative power
supply prevents a dynamic turn on throughout the
internal IGBT input capacitance.
• In Unipolar power supply the driver is typically
supplied with a positive voltage of 15 V at VDD2.
Dynamic turn on throughout the internal IGBT input
capacitance could be prevented by Active Miler Clamp
function. CLAMP output should be directly connected
to IGBT gate (Figure 12).
Reset Input Pin (RST)
Reset input pin has internal pull−up resistor to VDD1. In
normal condition the RST pin is connected to HIGH, to reset
FAULT conditions or disable output pulses connect RST pin
to LOW. In applications that does not allow to control the
reset, RST pin should be connected to IN+, the driver will be
reset by each input pulse.
VEE2A
GND1
VDD1
RST
DESAT
GND2
OUTH
FLT
VDD1
1μF
100n
VDD2
OUTL
RDY
IN-
+
-
VDD2
+
-
CLAMP
VEE2
IN+
100n
10μF
GND1A
VEE2
-
+
100n
10μF
Figure 11. Bipolar Power Supply
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14
NCV57001F
VEE2A
DESAT
GND2
OUTH
GND1
VDD1
RST
FLT
VDD1
1μF
100n
VDD2
OUTL
RDY
IN-
+
-
VDD2
+
-
CLAMP
VEE2
IN+
100n
10μF
GND1A
Figure 12. Unipolar Power Supply
Common Mode Transient Immunity (CMTI)
VEE2A
DESAT
GND2
OUTH
GND1
VDD1
RST
+
-
+
-
10μF
10μF
FLT
OUT must remain stable
VDD2
OUTL
RDY
IN-
+
S1
-
CLAMP
VEE2
IN+
GND1A
-
+
HV PULSE
Figure 13. Common−Mode Transient Immunity Test Circuit
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15
NCV57001F
Figure 14. Recommended Basic Bipolar Power Supply PCB Design
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16
NCV57001F
High-speed signals
Ground plane
10 mil s
0.25 mm
10 mil s
0.25 mm
Keep this space free
from traces, pads and
40 mil s
1 mm
40 mil s
1 mm
vias
Power plane
10 mil s
0.25 mm
10 mil s
0.25 mm
Low-speed signals
314 mils
(8 mm)
Figure 15. Recommended Layer Stack
Package
ORDERING INFORMATION
†
Device
Shipping
NCV57001FDWR2G*
1,000 / Tape & Reel
SOIC−16 Wide Body
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G
ISSUE E
DATE 08 OCT 2021
1
SCALE 1:1
GENERIC
MARKING DIAGRAM*
16
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
XXXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42567B
SOIC−16 WB
PAGE 1 OF 1
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