NCV12711ADNR2G [ONSEMI]
Automotive Qualified 4-45 Vin DC/DC Peak Current Controller;
| 型号： | NCV12711ADNR2G |
| 厂家： | 
ONSEMI |
| 描述： | Automotive Qualified 4-45 Vin DC/DC Peak Current Controller |
| 文件： | 总25页 (文件大小：1786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Current Mode PWM
Controller
MSOP10, 3x3
CASE 846AE
NCV12711
The NCV12711 is a fixed−frequency peak−current−mode PWM
controller containing all of the features necessary for implementing
single−ended power converter topologies. The device operates from
4 V to 45 V without auxiliary winding and within its thermal
capabilities. The controller contains a programmable oscillator
capable of operating from 100 kHz to 1 MHz and integrates slope
compensation to prevent subharmonic oscillations. The controller
includes a programmable soft−start, input voltage UVLO protection,
and an over−power protection (OPP) circuit which limits the total
power capability of the circuit as the input voltage increases. The
UVLO pin also features a shutdown comparator which allows for an
external signal to disable switching and brings the controller into a low
quiescent state. An onboard op−amp allows the implementation of
primary−side regulated converters or non−isolated dc−dc converters.
The NCV12711 contains a suite of protection features including
cycle−by−cycle peak−current limiting with smooth frequency increase
and a timer−based overload protection. All protection features place
the device into a low quiescent fault mode with a 1−s auto−recovery
period to allow for system recovery if the fault condition is removed.
MARKING DIAGRAM
10
V11x
AYWG
G
1
V11x
= Specific Device Code
= A
x
A
Y
W
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
UVLO
FB
1
2
3
10
9
Vin
Common General Features
• Wide V Input Range (4 – 45 V)
cc
VCC
DRV
GND
CS
• Internal 7.5−V Regulator
• Current−Mode Control with Adjustable Slope Compensation
• 0% Duty Ratio Operation in No−Load Condition
• Internal Over Power Protection
SS
8
RT
7
4
5
• Single Resistor Programmable Oscillator – 100 kHz to 1 MHz
• Adjustable Soft−Start on Peak Current and Frequency
• Programmable Input Voltage UVLO with Hysteresis
• Shutdown Threshold for External Disable
• Overload Protection with 30 ms Overload Timer
• Internal Operational Amplifier
• Fault Auto−recovery Mode with 1−s Auto−recovery Period
COMP
6
ORDERING INFORMATION
†
Device
NCV12711ADNR2G MSOP10, 3x3 2,500 / Tape
(Pb−Free) & Reel
Package
Shipping
•
1 A Source / Sink Gate Driver
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Typical Applications
• Single−ended Flyback and Forward Converters for Electric Vehicles
• Automotive 4 − 45 V Input DC/DC Controller for Auxiliary Power
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
May, 2022 − Rev. 0
NCV12711/D
NCV12711
.
+
.
1
2
3
4
5
UVLO
FB
Vin 10
+
9
8
7
6
VCC
DRV
SS
RT GND
CS
COMP
Figure 1. Low−Dissipation Wide−Range Application Non−Isolated Converter
.
+
.
.
+
1
2
3
4
5
UVLO
FB
Vin 10
+
9
8
7
6
VCC
SS
DRV
GND
CS
RT
COMP
Figure 2. Primary−Side−Regulated Wide−Range−Application Isolated Converter
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2
NCV12711
UVLO
VIN
+
−
Internal
regulator
UVLO
−
VUVLO(th)
−
delay
VCC(OVP)
+
+
+
tVCCOVP(DLY)
+
+
+
VCC
fault
clock
Enable
CVcc
VSTBY(th)
−
clamp
+
S
STBY
SHDN
S
R
VCC
In
Out
Q
R
VEE
Q
DRV
ramp
−
VRST(th)
+
tLEB(SCP)
Vdd
+
+
+
Rramp
−
ICS(OPP)
VOPP(start)
VSCP(LIM)
−
clock
CS
Rt
tLEB(CS)
VCS(LIM)
+
ramp
Dmax
OSC
−
t LEB(SCP)
Peak current reduction
0% for UVLO = 4 V
10% for UVLO = 4 V
15% for UVLO = 4 V
20% for UVLO = 4 V
Fault
Vdd
Jitter
(option)
ICS(OPP)
Enable
switching
SS
SS
VSS
1/kSS
control
Vout
SSend
Fault
Vdd
RFB
Voffskip
+
SHDN
SS_END
OVLD
NSCP
COMP
−
1/k PWM
Fault
Logic
FB
+
V
COMPskip
+
VCC(OVP)
VCC(UVLO)
+
+
VREF
−
Figure 3. Block Diagram
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3
NCV12711
PIN DESCRIPTION
DFNW10
Pin Name
Pin Description
1
UVLO
The UVLO pin is the input to the standby and UVLO comparators. A resistor divider between the power supply
input voltage and ground is connected to the UVLO pin to set the input voltage level at which the controller will
be enabled. UVLO hysteresis is set by a 5−mA pull−down current source. An externally−supplied pull−down
signal can also be used to disable the controller. The UVLO pin is also used to determine the over−power
protection amount.
2
3
4
FB
SS
RT
The FB pin senses the voltage to be regulated via a resistive divider. A passive network connected between this
pin and COMP allows to set poles and zeroes as suggested by the compensation strategy.
A capacitor on this pin sets the soft−start sequence during which the peak current setpoint is gradually
increased as well as the switching frequency.
The RT pin sets the oscillator frequency in the controller. This pin requires a resistor to ground closely located to
the controller. Typical R resistor values are in the range of 10 kW – 150 kW.
T
5
6
COMP
CS
This is the op−amp output pin, loaded by the R resistance.
FB
The CS pin is the current sense input for the PWM and current limit comparators. An external low−pass filter is
recommended for improved noise immunity. The external filter resistor is also used to determine the amount of
compensation ramp added to the current sense information.
7
8
GND
DRV
This pin is the controller ground.
The DRV pin is a high current output used to drive the external MOSFET gate. DRV has source and sink
capability of 1 A.
9
VCC
VIN
The VCC pin provides bias to the controller via a linear regulator. An external decoupling capacitor to ground in
the range of 1 – 10 mF is recommended. An auxiliary winding can help turn off the regulator and improve power
dissipation in wide input range applications.
10
This is the controller supply input. If kept below V
it can be safely connected to VCC.
CC(OVP)
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
V
V
Supply Voltage (Continuous)
−0.3 to 45
in(MAX)
I
Supply Current
mA
CC(MAX)
V
in
V
in
= 12 V
= 45 V
35
10
V
VCC pin
−0.3 to 30
V
V
A
V
CC(MAX)
V
DRV Voltage (Note 1)
DRV Current (Peak)
Max Voltage on Signal Pins
−0.3 V to V
DRV(high)
DRV(MAX)
DRV(MAX)
I
1.25
V
SIG(MAX)
V
Vcc
V
Vcc
> 5.5 V
< 5.5 V
−0.3 to 5.5
−0.3 to V
Vcc
I
Max Current on Signal Pins
10
mA
°C/W
°C/W
°C/W
°C
SIG(MAX)
R
Thermal Resistance Junction−to−Air
Junction−to−Top Thermal Characterization Parameter
Junction−to−Board Thermal Characterization Parameter
Maximum Junction Temperature
139
q
J−A
Y
q
5.5
J−T
Y
q
68.4
150
J−B
T
JMAX
T
Storage Temperature Range
−55 to 150
−40 to 125
°C
STG
T
J
Operating Temperature Range
°C
ESD Capability (Notes 2, 3)
Human Body Model per JEDEC Standard JESD22−A114E.
Charge Device Model per JEDEC Standard JESD22−C101E.
V
2000
1000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, V
, when V
DRV(high)
exceeds the driver clamp voltage. Otherwise, the
CC
maximum driver voltage is V
.
CC
2. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Charge Device Model 1000 V per JEDEC Standard JESD22−C101E
3. This device contains latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds 100 mA.
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4
NCV12711
RECOMMENDED OPERATING CONDITIONS
Symbol
Rating
Value
4.5 – 40
Unit
V
V
in
Supply Voltage
T
J
Operating Temperature Range
−40 to 125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (V = 12 V, V = 12 V, V
= open, C
= 1 nF, R = 53.6 kW V = 0 V, V = Open,
IN
CC
COMP
DRV T , CS SS
V
= 1.2 V, V = 0 V, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted)
UVLO
FB
J
J
Symbol
SUPPLY CIRCUIT
Supply Voltage
Characteristics
Test Condition
Min
Typ
Max
Unit
V
V
Regulation Level
I
= −5 mA
7.0
3.5
3.3
3.0
7.5
3.7
3.5
3.3
8.0
3.95
3.75
3.6
V
V
V
V
CC(reg)
cc
CC
in
in
CC
V
Start−up Level (Part Switches)
Minimum Operating Voltage
Reset Voltage (All Faults Clear)
V
V
V
increasing
decreasing
in(STR)
V
in(MIN)
V
decreasing
CC(reset)
V
Hysteresis between V
and V
in(MIN)
−
15
−
200
20
2.5
0.2
−
−
−
mV
mA
mA
V
IN(hys)
in(STR)
I
Start−up Current
V
V
= V
– 0.2 V
start
CC
CC(reg)
I
Start−up Current with V = 0 V
pin shorted to ground
−
VIN(LIM)
cc
cc
V
V
CC
Threshold for Non−Short Circuit Detection
−
−
CC(SC)
Vin(off)
I
Start−up Circuit Off−State Leakage Current
Supply Over−Voltage Protection
Hysteresis on Supply OVP
V
in
= 45 V
−
95
29
−
mA
V
V
25
−
27
100
7
CC(OVP)
V
mV
ms
CC(OVP_HYS)
VCCOVP(DLY)
t
VCC OVP Detection Filter Delay
−
−
Supply Current
SHDN (VCC Pin)
STBY (VCC Pin)
I
V
V
V
V
= 0 V
= 0.4 V
= 0 V
= 0.4 V
= Open, V
= 0 V
−
−
−
−
−
−
60
340
104
380
−
120
650
170
700
4
mA
mA
mA
mA
mA
mA
CC(SHDN)
CC(STBY)
UVLO
UVLO
UVLO
UVLO
I
I
I
SHDN (VIN and VCC Pins Shorted)
STBY (VIN and VCC Pins Shorted)
Enable
CC(SHDNVI)
CC(STBYVI)
I
C
V
= 2 V
COMP
CC(EN)
DRV
I
Fault
−
500
CC(FLT)
CS
CURRENT SENSE
V
Current Limit Comparator Threshold
237
250
25
263
75
mV
ns
CS(LIM)
CS(DLY)
t
Propagation Delay From Current Sense Limit to DRV
Low
Step V from 0 – 0.35 V
−
CS
V
Short Circuit Protection (SCP) Current Limit Threshold
−
−
325
25
−
75
mV
ns
SCP(LIM)
t
Propagation Delay From Short Circuit Limit to DRV Low Step V from 0 – 0.44 V
SCP(DLY)
CS
t
Minimum On−time Duration
−
135
4
170
−
ns
on,min
N
Short Circuit Counter
V
CS
= 1 V
−
SCP
t
CS Leading Edge Blanking (LEB)
SCP Leading Edge Blanking
CS LEB Pull−down Resistance
Overload Timer Duration
60
35
−
110
60
155
90
ns
ns
W
LEB(CS)
t
LEB(SCP)
R
27
55
PD(LEB)
t
V
> 0.25 V
22.5
−
28.5
0
34.5
−
ms
%
CS(OVLD)
CS
V
CS Skip Threshold in % of the Max CS Level
0% duty ratio –
< 325 mV
CS(skip)
V
COMP
V
Compensation Ramp Peak Level
Internal Ramp Resistance to CS Pin
1.55
15
1.8
21
2.05
27
V
ramp
R
kW
ramp
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NCV12711
ELECTRICAL CHARACTERISTICS (V = 12 V, V = 12 V, V
= open, C
= 1 nF, R = 53.6 kW V = 0 V, V = Open,
IN
CC
COMP
DRV T , CS SS
V
= 1.2 V, V = 0 V, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted) (continued)
UVLO
FB
J
J
Symbol
COMP SECTION
Characteristics
Test Condition
Min
Typ
Max
Unit
K
PWM to COMP Gain Through Resistor Divider
Propagation Delay to DRV Low (Note 6)
V
= 1.25 V / 2.9 V
= 2 V,
7.6
8.0
25
8.4
75
PWM
PWM(Dly)
COMP
t
V
COMP
−
ns
Step V 0 – 0.35 V
CS
V
Internal Feedback Offset
0.3
−
0.64
325
5
0.91
−
V
mV
mV
kW
V
offskip
V
0% Duty Ratio Level – 0−A Setpoint and No DRV
Voltage Hysteresis between Skip and Skip_out Level
Internal Pull−Up Resistance
V
V
is decreasing
is increasing
COMP(skip)
COMP
V
−
−
COMP(skip_hys)
COMP
R
4
5
6
FB
COMP(open)
V
COMP Open Pin Voltage
V
V
V
V
= 3.6 V
3.15
0.84
86
−
3.45
1
−
cc
I
COMP Output Current
= 0
1.2
94
0
mA
%
COMP
COMP
COMP
COMP
D
Maximum Duty Ratio Limit (Note 6)
Minimum Duty Ratio (Note 6)
= Open
= 0
90
−
MAX
D
%
MIN
OPERATIONAL AMPLIFIER SECTION
V
Voltage Feedback Input
T = 25_C
2.45
2.42
2.5
2.5
2.55
2.58
V
ref
J
−40_C < T < 125_C
J
I
IB
Input Bias Current
V
FB
= 3 V
−
−
−
−
−
0.01
90
1
−
−
−
−
−
mA
dB
A
OL
Open−Loop Voltage Gain
V
COMP
= 2 to 4 V
BW
Unity Gain Bandwidth (T = 25°C)
MHz
dB
j
PSRR
Power Supply Rejection Ratio
60
10
I
Output Current (Output Resistance is R ) Sink
(V
COMP
= 0.35 V, V = 2.7 V)
mA
OPS
FB
FB
Output Voltage Swing
High State
Low State
V
COMP is open, V = 2.3 V
−
−
4.8
0.03
−
0.15
V
V
OTH
OTL
FB
V
COMP is open, V = 2.7 V
FB
SOFT START
V
Soft−Start Open Pin Voltage
Soft−Start End Threshold
Soft−Start Current
V
= 3.6 V
2.80
1.85
12
−
3.35
2.00
15
8
−
2.15
18
−
V
V
SS(open)
cc
V
SS(end)
I
SS
0 < V < V
SS(end)
mA
SS
K
SS
Soft−Start to CS Divider
Soft−Start Discharge Resistance
R
−
−
100
−
W
SS(DIS)
SW(SS)
f
Minimum Frequency for V = 0 V
Clamp frequency
20
30
kHz
SS
OSCILLATOR
f
f
f
f
Oscillator Frequency 1
Oscillator Frequency 2
Oscillator Frequency 3
Oscillator Frequency 4
R
T
R
T
R
T
R
T
= 53.6 kW
= 130 kW
= 18.7 kW
= 8.66 kW
185
90
200
100
215
110
550
−
kHz
kHz
kHz
kHz
OSC1
OSC2
OSC3
OSC4
450
−
500
1000
UNDER−VOLTAGE LOCKOUT
V
Standby Threshold
V
V
V
increasing
decreasing
decreasing
0.3
0.25
−
0.35
0.3
50
7
0.4
0.35
−
V
V
STBY(th)
UVLO
UVLO
UVLO
V
Reset Threshold
RST(th)
V
Standby Hysteresis
mV
ms
V
STBY(HYS)
STBY(DLY)
t
Standby Detection RC Filter
UVLO Threshold
−
−
V
V
V
increasing
0.49
4.5
−
0.5
5
0.51
5.5
−
UVLO(th)
UVLO
I
UVLO Hysteresis Current
UVLO Detection Delay Filter
mA
ms
UVLO(HYS)
t
= V
− 50 mV
1.1
UVLO(DLY)
UVLO
UVLO(th)
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NCV12711
ELECTRICAL CHARACTERISTICS (V = 12 V, V = 12 V, V
= open, C
= 1 nF, R = 53.6 kW V = 0 V, V = Open,
IN
CC
COMP
DRV T , CS SS
V
= 1.2 V, V = 0 V, for typical values T = 25°C, for min/max values, T is – 40°C to 125°C, unless otherwise noted) (continued)
UVLO
FB
J
J
Symbol
UNDER−VOLTAGE LOCKOUT
Enable Filter Delay
OVER−POWER PROTECTION
Characteristics
Test Condition
Min
Typ
Max
Unit
t
V
UVLO
increasing
−
5
−
ms
UVLO(EN)
V
UVLO Voltage Above Which OPP Applied
Maximum Peak Current Reduction
−
−
−
−
−
1
V
%
V
OPP(START)
OPP
V
V
= 4 V
15
4
−
−
−
−
red
UVLO
OPP
Internal Peak Reduction Clamp on UVLO
COMP Threshold Voltage Above Which OPP is Applied
COMP Threshold Voltage for 100% OPP
= V
(1– OPP
red
)
clp
CS
CS(LIM)
V
1.4
2.6
V
OPP(0%)
V
V
OPP(100%)
GATE DRIVE
t
DRV Rise Time
DRV Fall Time
V
= 1.2 V to 10.8 V, C
6
6
10
10
16
16
ns
ns
DRV(rise)
DRV
DRV
= 1 nF
t
V
DRV
= 10.8 V to 1.2 V, C
DRV(fall)
DRV
= 1 nF
I
DRV Source Current
DRV Sink Current
V
V
V
V
= 6 V, Note 8
= 6 V, Note 8
−
−
8
6
0.9
1.0
10
−
−
−
A
A
V
V
DRV(SRC)
DRV
DRV
I
DRV(SNK)
V
DRV Clamp Voltage
Minimum DRV Voltage
= 20 V, R = 10 kW
DRV
12
−
DRV(clamp)
CC
CC
V
= V
+ 100 mV,
DRV(MIN)
CC(reg)
R
= 10 kW
DRV
FAULT PROTECTION
Auto−recovery Timer
THERMAL SHUTDOWN
t
0.8
1
1.2
s
AR
T
Thermal Shutdown
150
165
25
180
°C
°C
SHDN
T
Thermal Shutdown Hysteresis
−
−
SHDN(hys)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Disabling of overload timer refers to not acknowledging overload as a fault. The device will continue to switch indefinitely without going to
fault mode.
5. Disabling Slope compensation means that no compensation ramp is applied.
6. Electrical characteristics apply to both COMP Architectures
7. OPP Current Gain disabled means that no OPP current is injected out of the CS pin
8. Guaranteed by design
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NCV12711
TYPICAL CHARACTERISTICS
7.48
7.47
7.46
7.45
7.44
7.43
3.732
3.727
3.722
3.717
3.712
3.707
3.702
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. VCC(REG) vs. Temperature
Figure 5. Vin(STR) vs. Temperature
3.318
3.316
3.314
3.312
3.310
3.308
3.306
3.304
3.302
3.492
3.487
3.482
3.477
3.472
3.467
3.462
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. Vin(MIN) vs. Temperature
Figure 7. VCC(reset) vs. Temperature
25.9
25.4
24.9
24.4
23.9
23.4
57.1
56.6
56.1
55.6
55.1
54.6
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Istart vs. Temperature
Figure 9. Ivin(off) vs. Temperature
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NCV12711
TYPICAL CHARACTERISTICS (continued)
27.42
27.40
27.38
27.36
27.34
27.32
27.30
27.28
27.26
65
64
63
62
61
60
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. VCC(OVP) vs. Temperature
Figure 11. ICC(SHDN) vs. Temperature
112
111
110
109
108
107
106
105
104
375
365
355
345
335
325
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. ICC(STBY) vs. Temperature
Figure 13. ICC(SHDN_VI) vs. Temperature
2.05
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
420
410
400
390
380
370
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. ICC(STBY_VI) vs. Temperature
Figure 15. ICC(EN) vs. Temperature
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9
NCV12711
TYPICAL CHARACTERISTICS (continued)
33
31
29
27
25
23
21
250.5
249.5
248.5
247.5
246.5
245.5
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Vcs(lim) vs. Temperature
Figure 17. tCS(DLY) vs. Temperature
325.6
325.4
325.2
325.0
324.8
324.6
324.4
324.2
324.0
323.8
323.6
114
112
110
108
106
104
102
100
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. VSCP(LIM) vs. Temperature
Figure 19. tLEB(CS) vs. Temperature
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
21.3
21.1
20.9
20.7
20.5
20.3
20.1
19.9
19.7
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. Vramp vs. Temperature
Figure 21. Rramp vs. Temperature
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10
NCV12711
TYPICAL CHARACTERISTICS (continued)
4.94
4.93
4.92
4.91
4.90
4.89
4.88
0.8
0.7
0.6
0.5
0.4
0.3
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Voffskip vs. Temperature
Figure 23. RFB vs. Temperature
2.514
2.512
2.510
2.508
2.506
2.504
2.502
2.500
2.498
89.13
89.08
89.03
88.98
88.93
88.88
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 24. DMAX vs. Temperature
Figure 25. Vref vs. Temperature
102.7
102.6
102.5
102.4
102.3
102.2
102.1
201.5
201.0
200.5
200.0
199.5
199.0
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 26. fosc1 vs. Temperature
Figure 27. fosc2 vs. Temperature
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11
NCV12711
TYPICAL CHARACTERISTICS (continued)
504
502
500
498
496
494
492
0.3548
0.3543
0.3538
0.3533
0.3528
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 28. fosc3 vs. Temperature
Figure 29. VSTBY(th) vs. Temperature
0.5006
0.5001
0.4996
0.4991
0.4986
0.4981
0.4976
0.2980
0.2975
0.2970
0.2965
0.2960
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 30. VRST(th) vs. Temperature
Figure 31. VUVLO(th) vs. Temperature
15.9
15.7
15.5
15.3
15.1
14.9
14.7
10.4
10.2
10.0
9.8
9.6
9.4
9.2
−50 −25
−50 −25
0
25
50
75
100 125 150
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 32. OPPred vs. Temperature
Figure 33. VDRV(clamp) vs. Temperature
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12
NCV12711
APPLICATION INFORMATION
NCV12711 implements
a
standard current−mode
and increases along the soft−start sequence. Soft−start is
activated when a new startup sequence occurs or during
an auto−recovery hiccup.
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count and cost effectiveness are
key design parameters, particularly in dc−dc converters
modules and open−frame power supplies. NCV12711
brings all the necessary components normally needed in
today modern power supply designs.
• Current−mode operation with internal slope
compensation: implementing peak current mode control
at a fixed operating frequency, the NCV12711 includes an
externally−adjustable slope compensation scheme. By
sizing a single resistance connected in series with the CS
pin, the designer has the ability to tailor the compensation
level exactly to his needs.
• On−board op−amp: an op−amp allows the
implementation of non−isolated dc−dc converters but
also isolated versions in which the rectified auxiliary
voltage is used for regulation.
• V OVP: an OVP protects the circuit against V
cc
cc
runaways. The fault must be present at least 7 ms to be
validated. This OVP is auto−recovery.
• Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (the auxiliary winding
level does not properly collapse in presence of an output
short). In this controller, every time the internal 0.25−V
maximum peak current limit is activated (or less when
OPP is active), an error flag is asserted and a time period
starts, thanks to the programmable timer. When the timer
has elapsed, the controller enters an auto−recovery mode
with a 1−s recurrence.
• Winding or diode short circuit protection: in case the
secondary−side winding (or even the rectifying diode) is
shorted, the primary−side current can grow very quickly
with possibly−lethal conditions in the converter. An extra
comparator with a smaller LEB monitors if the peak
current exceeds 25% of the maximum value
• 0% duty ratio operation: the loop can program a 0−A peak
current setpoint when it imposes 640 mV on the error
amplifier COMP pin. It means, the width of the DRV
pulse is a minimum t (LEB + propagation delay). If V
on
out
keeps increasing in this situation, the regulation is lost and
the IC goes to skip mode with no DRV pulse. It ensures
that the IC will safely skip cycles at minimum t during
light load, preventing output runaway while keeping
output ripple at a minimum.
on
• Internal regulator: the part includes an internal regulator
powering the device from 4 to 45 V without the need to
resort to an auxiliary winding. When power dissipation is
at stake, it is possible to lift the VCC pin up via an
auxiliary winding and permanently disable the regulator.
(250 mV/R
) four consecutive times. At the end of
sense
this sequence, the converter enters auto−recovery mode.
• Input voltage monitoring: the UVLO pin observes the
input voltage through a resistive divider. This pin serves
two purposes: a) it ensures the converter operates within
the range it has been designed for and b) it routes this
information to a power−limiting path for over−power
protection (OPP).
• Internal OPP: the part internally buffers the UVLO
voltage and reduces the maximum peak current setpoint
at high input line. Please note that the OPP current starts
from 0% when the UVLO voltage is 1.0 V, a low−line
condition. It helps pass maximum power at the lowest
input voltage despite some compensation at high line.
OPP is also disabled during the start−up sequence or in
light−load operation.
• Internal soft−start: a soft−start precludes the main power
switch from being stressed upon start up and it reduces
output voltage overshoots. In this controller, the soft−start
can be adjusted by a simple capacitor to ground. Beside
peak current smooth increase brought by this mechanism,
the switching frequency starts from a low 30−kHz value
Supplying the Controller
The component integrates a start−up current source
supplied from the VIN pin and capable of sourcing up to
20 mA typically to the VCC pin. When V reaches the
regulation level of 7.5 V, the startup is a linear regulator
which can continue to supply and regulate V at 7.5 V. The
recommended VCC capacitance to ensure stability of the
regulator is 1 – 10 mF. This source is a dual−current type
meaning that if for any reason the V is shorted to ground,
cc
cc
cc
the current is safely limited to 2.5 mA, preventing any lethal
runaway at a high input voltage. When the short circuit is
released and V exceeds a certain voltage level (200 mV
cc
typical), the source is back to its 20−mA setpoint. The
20−mA are typically specified for a 12−V level on the VIN
pin but the part will deliver current as soon as a bias appears
on the part. Figure 34 shows a simulated start−up sequence
with VIN plateauing at 4 V for some time before taking off
towards 15 V. The driving pulses follow the voltage and are
clamped at the 7.5−V voltage later on.
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13
NCV12711
v
VIN
(t)
v
DRV
(t)
v
cc
(t)
Figure 34. The LDO is Activated During the Start−up Sequence and Powers the Controller
As the LDO supplies the controller, it sees the average
current absorbed by the controller. This current is
If we assume a R
soldered on a wide copper area, then the maximum VIN
of 130°C/W when the part is
qJ−A
approximately made of I
current leading to a total current equal to:
plus the MOSFET driving
voltage at a 50°C ambient temperature will be:
CC(EN)
Tj * TA
Vin,max
t
ILDO [ ICC(EN) ) IDRV [ ICC(EN) ) fswQG
(eq. 4)
R
qJ*AILDO
(eq. 1)
Assume a junction temperature limit of 110°C and a
maximum ambient of 60°C, then the maximum bias voltage
for this circuit while the LDO is permanently activated
would be:
Assume you have selected a MOSFET featuring a 35−nC
total gate charge Q and operate it at 250 kHz. The average
G
current flowing in the LDO will be:
ILDO [ 4 m ) 250 k @ 35 n [ 12.8 mA
(eq. 2)
110 * 60
Vin,max
t
[ 30 V
This current multiplied by the maximum voltage at the
VIN pin will define the controller average power
dissipation:
(eq. 5)
130 12.8 m
Beyond this value, risks exist to damage the die by
excessive power dissipation. To benefit from the full voltage
range up to 45 V, it is recommended to a) reduce the
PLDO + ILDOVVIN
(eq. 3)
dissipated power by lowering f and adopting a low−Q
sw
G
power MOSFET and/or b) add an auxiliary winding to the
transformer and use the LDO as a simple one−shot start−up
source (Figure 35).
4 − 45 V
Loop is closed − regulation is met
V
cc
(t)
V
in
= 4 V
VIN
0 − 20 mA
Regulator
D1
+
7.5 V
VCC
+
CV
cc
Figure 35. The LDO Can Be Associated with an Auxiliary Winding and Be Turned Off in Normal Operation
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14
NCV12711
Protecting the VCC Pin
The short circuit between the pins bypasses the LDO and
the whole circuit is fed by the input rail. Make sure the input
rail voltage always remain below the OVP voltage otherwise
the controller will stop working. In the example, the 25−V
limit corresponds to the minimum of the OVP specification.
The VCC pin is protected by an over−voltage detection
circuitry which immediately reacts as soon as the bias on this
pin exceeds 27 V typically (25 V minimum). When the fault
happens and lasts more than 7 ms, all pulses are immediately
stopped and the circuit remains silent for 1 s. It resumes
operation via a soft−start sequence and goes back to normal
mode if the fault has gone. This function is there to protect
the controller in case you would accidentally supply it with
a large voltage on the auxiliary winding for instance if the
control loop fails. In some low−voltage applications, you
can directly supply the controller from the input rail by
shorting the VIN and VCC pins together (Figure 36).
Monitoring the Input Voltage
It is important to check that the converter operates within
an authorized input voltage range. For that purpose, the
UVLO pin permanently monitors a scaled−down image of
the input rail and turns the IC on or off accordingly.
A simplified view of the internal circuitry is shown in
Figure 37.
V
in
4 − 25 V
V
UVLO(th)
VIN
−
R
+
UVLO1
Regulator
0 − 20 mA
+
Enable
R
UVLO(HYS)
+
7.5 V
UVLO
VCC
+
RUVLO2
0.1 mF
4.7 mF
IUVLO(HYS)
t = 7 ms
27 V
+
Fault
−
If V
UVLO
would go
beyond 4.5 V
Figure 36. For Low−voltage Applications, it is Possible
to Connect the VIN and VCC Pins Together. The OVP
on the VCC Pin Remains Active and will Stop Pulses if
the Input Rail Exceeds 27 V.
Figure 37. A Comparator Turns The IC On or Off
Depending the VIN Pin Bias Level
The turn−on and –off voltages can be obtained using the
following formulas:
R
UVLO1 ) RUVLO2
RUVLO2
Von + [VUV(th) ) (RUVLO1 ø RUVLO2 ) RHYS) IUV(HYS)
]
(eq. 6)
(eq. 7)
R
UVLO1 ) RUVLO2
Voff + (VUVLO(th) * VUVLO(HYS)
)
RUVLO2
From these expressions, resistors setting the turn−on
and −off levels are determined with the below equations in
which R
is arbitrarily fixed:
UVLO2
(VUVLO(th) * VUVLO(HYS)) Von ) IUVLO(HYS)RUVLO2 (VUVLO(th) * VUVLO(hys)) * Voff (VUVLO(th) ) IUVLO(HYS)RUVLO2
)
RUVLO(HYS)
+
(eq. 8)
(eq. 9)
IUVLO(HYS)Voff
R
UVLO2 (Voff * VUVLO(th) ) VUVLO(HYS)
)
RUVLO1
+
V
UVLO(th) * VUVLO(HYS)
As an example, if R
turn−on voltage with a 6−V turn−off level, then
= 10 kW and you select an 8−V
diode at the UVLO pin to keep the pin voltage within its safe
operating area.
UVLO2
R
= 20 kW and R = 114 kW. The Excel sheet posted
HYS
UVLO1
Limiting the Power Excursion at High Input Voltage
It is a well−known phenomenon that the maximum power
delivered by a flyback converter varies with the input
voltage. Assuming a wide input range design, your
converter can potentially exhibit more current for the output
diode at high line than at low line with detrimental effects for
on the NCV12711 landing page automates the calculation of
these resistors. As a final note, once the resistive divider is
determined, it is important to verify that the maximum
voltage on the UVLO pin does not approach or exceed its
5.5−V maximum rating at the maximum input voltage.
Should it be the case, you will have to install a 4.7−V Zener
www.onsemi.com
15
NCV12711
reliability. This is because the converter is designed to
NCV12711 embarks an over−power protection (OPP)
scheme which reduces the maximum peak current setpoint
when the UVLO voltage varies from 1 V (low line) to 4 V
where the OPP is no longer active. The peak setpoint will
reduce by 15% when the UVLO hits 4 V (Figure 38). An
option exists to turn OPP permanently off, please contact
sales for that purpose.
deliver its nominal power at the lowest input voltage.
Transition to DCM and propagation delays are the reason
why the power capability changes with the input voltage.
V
sense(max)
OPP
red
Soft−Start Sequence
100%
85%
To limit the stress on primary− and secondary−sides, the
NCV12711 incorporates a soft−start circuitry which
smoothly increases the peak current setpoint
cycle−by−cycle but also sweeps the switching frequency.
The converter starts with an almost 0−A setpoint at a 30−kHz
frequency and increases this value up to the nominal
selection. A capacitor is charged by a 15−mA current source
up to 2 V where the sequence has ended. The capacitor is
thus selected based on the wanted soft−start duration:
UVLO
clamp
V
UVLO
0.5
V
1
2
3
4
4.5
5
V
OPP(start)
OPP(stop)
I
SStSS
15 m 10 m
Figure 38. The Maximum Peak Current Reduces
with the Input Voltage and Reaches 85% of its
Nominal Value at the Highest Input Voltage
CSS
+
+
+ 75 nF
(eq. 10)
2
VSS(end)
i
D
(t)
f
(t)
SW
End of
sweep
End of
sweep
v
SS
(t)
Figure 39. The Peak Current is Smoothly Ramped Up as Well as the Switching Frequency Which Starts from a
Low 30 kHz
Figure 39 shows a typical start−up sequence highlighting
current and frequency variations during this sequence.
Please note the different time scale for the frequency plot.
The frequency sweep ensures the lowest possible stress at
power up and is especially interesting when secondary−side
synchronous rectification is used: in absence of output
voltage, the MOSFET body diode plays the rectifier role
until the control circuit takes the lead when sufficiently
powered. In absence of a smooth frequency ramp−up,
violent voltage spikes can appear across the synchronous
MOSFET and may destroy it. A slow frequency increase
ensures a limited stress until the synchronous circuit is fully
operational.
Feedback and Current Sense
The controller hosts an operational amplifier (op−amp)
useful
for
either
non−isolated
dc−dc
or
primary−side−operated isolated flyback converters. The
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16
NCV12711
output of this op−amp controls the peak current setpoint via
In which t
represents the maximum propagation delay
prop
a resistive divider associated with a series diode as shown in
Figure 40. The voltage−to−peak−current−setpoint division
from the detection of the over−current event to the effective
MOSFET gate pulldown. The IC contributes up to 75 ns to
this figure but if you add a gate resistance, this number can
grow significantly.
ratio is 8 with a maximum value V
clamped at
CS(LIM)
250 mV. The maximum inductor current without active OPP
is therefore defined as:
VCS(LIM)
Vin
Lp
IL,max
+
)
tprop_
(eq. 11)
0.325 V
Rsense
+
5 V
+
PWM reset
−
5 kW
Skip cycle
+
COMP
V
out
0.64 V
100 kW
2.5 V
Current sense
R
2
CS
+
250 mV
+
C
2
R
1
55 W
14.23 kW
R
sense
C
1
−
R
lower
FB
t
LEB
Figure 40. The Series Diode Introduces an Offset Making Sure Skip Cycle Occurs at a 0% Duty Ratio
In a current−mode controller, the minimum on−time
duration is set by the propagation delay and the
leading−edge blanking duration. The sum of both variables
regulation. The output pulses can reduce down to the
smallest possible ones and equal LEB plus propagation
delay, including the MOSFET turn−off time. If the loop asks
for less than this value, the peak current is frozen to this
minimum value:
gives the minimum t . When the load current is getting
on
lighter, the op−amp pulls the COMP pin down in an attempt
to reduce the peak current setpoint. The voltage on the
COMP decreases until the minimum on−time is reached.
Vin
Ip,min
+
(tLEB ) tprop).
(eq. 13)
Lp
With the NCV12711, this minimum t is around 135 ns and
on
Assuming a 5−mH primary inductance L with a 40−V
p
despite a COMP pin going further down, it cannot be
reduced. Thus, there is always a little bit of energy that is
transmitted cycle by cycle from the primary to the secondary
side. An output voltage runaway in a flyback converter is
therefore possible in a no−load condition. To avoid this
situation, a diode drop (≈ 640 mV) is inserted with the
feedback voltage setting the peak current. For the maximum
peak value, the COMP pin will be biased at the following
level:
input voltage and a 150−ns pulse duration, the peak current
cannot be below 1.2 A. If the load keeps decreasing, an
output voltage runaway can happen as peak current can no
longer be reduced: regulation is lost. To avoid an
over−voltage situation, the controller hosts a skip cycle
comparator which shuts pulses off when the feedback is out
of its normal dynamic range. When V
keeps going
COMP
down in an attempt to regulate (with no action of course), it
reaches 325 mV and all pulses are stopped. As V is now
out
VCOMP + VCS(LIM) kPWM ) Vf + 0.25 8 ) 0.64 + 2.64 V
falling in lack of pulses, the COMP pin slightly goes up
again and authorizes pulses until COMP goes low. This is
skip cycle operation. Unlike other controller where skip is
programmed at 10 − 15% peak current, here it only activates
when the regulation is lost. Thus, if you do not want to see
skip cycle in your application, either install a dummy output
load (a bleeder) or reduce the output resistance of the
feedback divider so that it draws enough current to maintain
(eq. 12)
On the opposite, the minimum current will be reached
when V
falls below 0.64 V. The dynamic on the COMP
COMP
pin can therefore be depicted by the graph shown in
Figure 41 with simulation data. At power up, the loop asks
for the maximum peak current and regulates when the target
is met. Considering a light−load condition, the loop will
reduce the setpoint to a minimum so as to keep V in
out
V
COMP
above 640 mV.
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17
NCV12711
V
COMP
(V)
5
5 V
Open−loop operation
v
(t)
COMP
2.64 V
Loop is
closed
v
DRV
(t)
3
1
min t
no DRV
0.64 V
0.325 V
on
Open−loop operation
325 mV
Skip cycle
0
Figure 41. The COMP Pin Swings between 2.64 V and 0.64 V for a 0−A Peak Setpoint. Skip Cycle Operation Happens when the
Loop Fails to Regulate at the Lowest Possible Peak Current Setpoint.
Slope Compensation
In which V is the secondary−side rectifier drop, N is the
f
Current−mode power supplies are prone to sub−harmonic
oscillations. This is because the inner current−loop gain
crossover frequency is too high and there is no phase margin
at this point. The condition happens when the converter
operates in continuous conduction mode (CCM) with a duty
1:N transformer turns ratio, L the primary−side inductance
p
and R
the current sensing resistance. The compensation
sense
slope is given in the data−sheet and depends on the selected
switching period:
Vramp
Se
+
ratio approaching 50%.
A simple cure for these
(eq. 15)
DmaxTsw
sub−harmonic oscillations is to inject a compensation ramp
Now, compute the division ratio value between S , the
e
S which will reduce the current−loop gain. It can be done in
e
existing ramp level and what you want to inject. If we select
a compensation level equal to 50% of the inductor
downslope current, then the division ratio equals:
several ways but the simplest one is to sum the ramp with the
current sense information. NCV12711 integrates an
artificial ramp derived from the oscillator. Once buffered, it
biases the CS pin via a 20−kW resistor (Figure 42) only
during the on−time. Inserting a resistance in series with the
sensed voltage offers a simple means to adjust the
compensation effort. If you do not want compensation,
simply reduce this resistance or suppress it provided your
PCB layout is clean.
0.5 Sf
0.5 @ DmaxRsenceTsw (Vout ) Vf)
divratio +
+
Se
LpNVramp
(eq. 16)
Then, the resistance to add in series with the CS pin is
simply:
Rcomp + divratio Rramp
(eq. 17)
1.9 V
Assume the following data: L = 5 mH, R
= 0.03 W,
p
sense
D
V
= 90%, F = 100 kHz, R
= 1.9 V. Applying the above formulas to a 5−V
= 20 kW, N = 1.25 and
max
sw
ramp
t on
ramp
PWM
reset
converter leads to a compensation resistance value of 1.4 kW:
V
L
:+ 5 V
N
D
:+ 1.25
R
F
:+ 20 kW
R
k
:+ 0.03 W
ramp
sense
out
turns
max
Rramp
:+ 5 mH
:+ 90%
:+ 100 kHz
sw
:+ 50%
Rcomp
p
comp
1
+
CS
Feedback
V
S
:+ 1.9 V
T
:+
sw
V :+ 0.5 V
ramp
f
F
sw
Rsense
V
V
) V
@ L
−
ramp
out
V
ms
f
V
ms
:+
+ 0.19
S :+
@ R
+ 0.026
sense
e
f
T
N
sw
p
turns
k
@ S
f
comp
S
Figure 42. You Can Easily Adjust the Slope
Compensation Level you Need by Inserting a
Resistance in Series with the CS Pin
divratio :+
+ 0.069
e
3
R
:+ R
@ divratio + 1.389 10
W
comp
ramp
To determine the value of R
determine the primary−side inductor current downslope S .
Once scaled to volts per second via the sense resistance, we
have:
, you first need to
comp
k
@ R
@ T @ (V
) V )
f
comp
sense
sw
out
f
@ R
+ 1.389 kW
ramp
L
@ N
@ V
p
ramp
turns
Figure 43. The Compensation Resistance is Easily
Determined with a few Calculation Steps
V
out ) Vf
Sf +
Rsense
(eq. 14)
NLp
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18
NCV12711
Short Circuit Protection
recovers and resumes operation. If the fault is still present,
a new 1−s off−mode takes place and the converter keeps
ticking as long as the fault remains. Figure 44 describes a
start−up sequence leading to a regulated output and
suddenly followed by an output short circuit. The error flag
is asserted immediately and the timer starts counting. During
this time, the peak current is pushed to the maximum value.
When the timer has elapsed, all pulses stop and the 1−s
off−time period starts. Then the power supply attempts to
resume operations (not shown). The overload timer is set to
30 ms but longer periods of time are available upon request
to the factory. Please contact your sales person for more
information.
If the loop asks for the maximum power, the peak−current
setpoint is clamped to 250 mV (no OPP). When this
happens, the controller arms an error flag signaling a fault
condition. This naturally occurs during the start−up
sequence until the converter regulates and resets the flag.
A fault timer of 30 ms starts every time the error flag is
asserted. When the timer reaches completion, all pulses are
stopped and the part remains silent for 1 s. If the auxiliary
winding disappears during the 1−s off−mode, the LDO takes
over and supplies the part. At the end of the 1−s period, a
fresh start−up sequence takes place with soft−start and
frequency sweep. If the fault has disappeared, the converter
Timer completed
v
DRV
(t)
1−s recovery
v
FB
(t)
regulation
Fault
asserted
asserted
Error flag
reset
v
out
(t)
Short circuit
Figure 44. The Circuit Auto−recovers from a Short Circuit or an Overload Situation
In case the peak current measured at the CS pin largely
exceeds the 250−mV voltage setpoint, second
over−current comparator trips. This second comparator
benefits from a smaller LEB duration (60 ns versus 110 ns)
and reacts in case the sensed voltage exceeds the 250−mV
limit by 25%: V
. When such an event occurs, e.g.
SCP(LIM)
a
when the secondary diode fails shorted, the controller counts
4 consecutive events and stops all pulses immediately. The
part then waits 1 s before attempting to restart. The internal
circuitry appears in Figure 45.
www.onsemi.com
19
NCV12711
t
LEB(SCP)
ton
t
LEB(CS)
R
ramp
R
comp
CS
+
Count by
four
t
LEB(SCP)
R
sense
−
+
V
SCP(LIM)
V
dd
−
5 kW
PWM
reset
COMP
100 kW
+
+
V
offskip
14.23
250 mV
kW
Figure 45. If the Current Sense Pin Exceeds the Maximum Cycle−by−cycle Limit by 25%, a Counter Records the Event and
Stops All Pulses after 4 Consecutive Events
Operational Amplifier
In which:
The on−board op−amp exhibits a gain−bandwidth product
(GBW) of 1.4 MHz with a low−frequency pole located at
53 Hz. It features an open−drain configuration loaded by the
internal 5−kW pull−up resistor. With this circuit, it is
possible to implement a type 2 compensator hosting a pole
at the origin, one zero and one pole. Such configuration is
shown in Figure 46 with its typical ac response in the right
side. The type 2 lends itself well to stabilizing current−mode
dc−dc converters. The characteristics of such compensator
are described by the following transfer functions:
wz
R2
C1
R2
R1
G0
+
[
(eq. 19)
(eq. 20)
R1
C
1 ) c2
1
wz
+
R2C1
1
1
[
wp
+
C1C2
R2C1
(eq. 21)
R
2 C1)C2
Approximated formulas are valid when we have C << C .
2
1
1 )
s
G(s) + *G0
s
(eq. 18)
1 )
wp
V
out
5 V
(dB)
60
R
FB
+
40
R
1
+
f
c
V
ref
Mid−band gain G
0
20
0
V
(f)
−
COMP
COMP
R
2
V
(f)
out
C
2
(°C)
V
(f)
COMP
140
C
1
V
out
(f)
FB
phase
boost
120
100
R
lower
90°
Figure 46. The On−board op−amp Lets you Realize a Type 2 Compensator which is Adequate for Stabilizing
Current−mode dc−dc Converters
www.onsemi.com
20
NCV12711
The op−amp own characteristic can be neglected if the
A quick experiment on the prototype will let you know if
you need to keep or slightly adjust this value. The following
array suggest values for some typical switching frequencies:
selected crossover frequency is moderate, around the kHz
for instance. However, if you plan to extend crossover at
10 kHz or so, then it is important to verify the compensator
response once the op−amp characteristic is accounted for
especially if a high gain is required at crossover. A separate
application note covers a compensation exercise in details.
NCV12711 lends itself well to opto−isolated applications
also. Just ground the feedback pin and connect the
opto−coupler collector to the COMP pin with a capacitor for
Table 1.
Frequency (kHz)
R (kW)
t
100
150
200
250
300
350
400
127
74.2
52.4
40.5
33
the pole generation together with R
.
FB
5 V
27.8
24
V
ref
R
FB
+
+
For stability reasons, it is usually not recommended to
−
COMP
decouple the R pin with a capacitor.
t
C
U1B
pole
6
1x10
FB
5
8x10
Figure 47. If you Tie the FB Pin to Ground, then
an Opto−isolator Can Pull the COMP Pin Down
for Regulation Purposes
5
6x10
F
sw
(R )
t
5
4x10
2x10
Oscillator
The oscillator lets you select a switching frequency from
5
100 kHz up to 1 MHz. By pulling the R pin to ground via a
t
resistance, it is possible to select the switching frequency.
The curve from Figure 48 links the switching frequency with
the resistance value. An approximate formula lets you also
determine the resistance as follows:
0
4
5
5
5
0
5x10
1x10
1.5x10
2x10
R
t
Figure 48. You Can Extract the R Resistance
Value from the Graph or Compute it with the
Approximate Expression
8.9 @ 109
t
Rt [
(eq. 22)
F
sw * 30 k
Assuming a wanted 100−kHz operation, you would select
a resistance of
8.9 @ 109
Rt +
[ 127 kW
(eq. 23)
100 k * 30 k
www.onsemi.com
21
NCV12711
Application Circuits
The NCV12711 can be used in a variety of applications.
Figure 49 represents a 100−kHz flyback converter
regulating the auxiliary winding at 12 V. This is a
wide−range application since the board operates from a 4−V
input voltage up to 45 V. the precision
R14
100
R16
10
10
212211
R12
100
aux
16
16
10
212211C17
VA
VB
D2
FSV10100V
R1
L3
470p
J2a
1 W
D1
1N49317
18k
MSS1038−152NL
T1
12 V/1 A
0 V
+
17
17
22
22 22
22
22
22
22
22
22 10
191199
19
19
19
19
19
19
191199
1.5u
.
10
TO−277
3
R21
33
0.5 W
R20
2.2
C5
330u
C13
330u
C14
R19
1k
C1
D5
330u
10n
.
6
16
22
28
28
gnd
U1
−
J2b
SW1
4
4
2
1
16ZLG330MEFC8X11.5
1SMB5929BT3G
SMB − 3 W
R9
38k
R5
68k
C8
0.1uF
MCNDS−02V
4
5
.
b
a
4
7
7
Lp = 8 uH
1:2 − power
1:2 − aux
C12
R4
1.5k
TP5
12
NCV12711
J1a
0.47uF
D4
BAV21
R18
47
C18
3.3n
17
22
22
11
8 4.3 V/4.0 V
C19
470p
VIN
UVLO
FB
10
9
12 1
11 2
20 3
25 V
+
17
8
8
4
3
44
C9
100uF
C10
2.2u
C11
2.2u
Part number = C1206C332KBRACTU
1
VCC
630 V
11
11
3
33
14
14
4.5−45 V
R10
TP2
15
10
aux
15
Q1
J1b
SS
DRV
GND
CS
8
FDMS86103L
Power56
20
20
15
18
18
18
−
11
15
TP1
R17
10k
RT
4
7
TP3
5
3
3
9
9
9
1N4148
D3
6
R8
10k
TP4
COMP
13 5
6
13
5
5
5
5
6
6
6
6
8
8
8
3
3
6
MSOP10
C16
330pF
13
R3
850
22p
R11
133k
R13
R2
40m
C3
4.7u
50 V
C7
0.1uF
50 V
R7
133k
C2
40m
Vishay
25
11
11
WSL2512R0400FEA
R6
10k
C4
10n
C6
22nF
25
R15
0
gnd
SW1 − position b: Vcc on aux, 4.5−45 V Vin
SW1 − position a: Vcc on Vin, 4.5−28 V Vin
SW1 − all open: Vcc on LDO, 4.5−45 V Vin
SW1 − all closed: forbidden
C15
4.7nF
11
11
shortest possible length − hi peak currents (10 A)
Figure 49. 4.5 − 45 V Input Voltage Isolated Flyback Converter Delivering 12 V/1 A
Figure 50 represents a 5−V/2−A application circuit
operated from a 4.5−to−10−V input source, a typical
industrial board−mounted module. A synchronous rectifier
ensures a good overall efficiency. There is no auxiliary
winding on this board.
R1
Lp
1:1.25
= 5uH
L3
VB
J2a
22k1
W
−
power
MSS1038−152NL
10ZLG470MEFC8X11.5
+
17
17
3
3
3
3
3
3
3
3
3
3
25
25
25
25 25
25
25
25
25
25
25
1,2
8,7
1.5u
20
.
C5
470u
C13
470u
C1
10n
D1
10
10
21 C17
2.2n
R16
10
R20
2.2
.
1N4937
3,4
R14
J2b
6,5
3
28
28
0 V
−
R29
10
2
1
10
21
VA
16
16
25
0.25
W
T1
R5
68k
R12
20
SO−8FL
30 1.5 m
U1
25
34
25
R18
100
Q2
R9
560
R15
10k
R4
1.5k
3
TP4
12
V
NCV12711
FDMS86181
J1a
6
D2
1N4148
C9
470uF
R26
10k
17
3
3
8 4.3 V/4.0
8
V
8
10 10
VIN
UVLO
FB
10
12 1
11 2
20 3
C19
+
R22
10k
17
6
6
66
TP2
6
25
C10
2.2u
C8
2.2u
0.1uF
22
22
26
26
C11
2.2u
U3B
1
R31
2.2
VCC
9
11
11
6
10
10
10
1919
30
34
4.5−10 V
R11
10k
C18
0.1uF
R19
1k
Q1
U2B
R10
10
C14
J1b
R23
0
SS
FDMS86103L
SO−8FL
DRV
GND
CS
8
D4
18
2.2uF 30
20
15
5
15
15
15
18
18
−
30
1N4148
R100
0R
30 30
23
23
23
23
27
27
27
TP1
100
V
11
m
R28
10k
RT
4
7
U5
9
9
9
TP3
D3 1N4148
R24
91k
4
4
R27
0
7
34
34
NCP4306
LLD
COMP
TRIG
13 5
6
4
5
13
5
5
8
8
8
6
6
6
6
5
5
4
4
32
MSOP10
C16
1nF
20
13
29
29
CS 6
29
3
R3
TON
R25
10k
R13
40m
U4
NCP431
R2
40m
R7
133k
C3
4.7u
16
C7
0.1uF
50
C2
850
D5
1N751
5.1
31
C12
22p
T2 OFF
33
R17
10k
GND7
4.7uF
V
V
R30
33k
V
R21
0
VCC
DRV8
7
1
R6
10k
C6
22nF
C4
10n
U3A
PS2801
Vishay
WSL2512R0400FEA
7
303300
SOIC8
shortest possible length
− hi peak currents (8 A)
All components around U5 must be
closely located to the IC, in particular
C14 and C19.
C20
3.3n
Part number
=
C1206C332KBRACTU
630
V
Figure 50. 4.5 − 10 V 5−V/2−A Opto−isolated dc−dc Flyback Module
www.onsemi.com
22
NCV12711
Considering NCV12711 for a non−isolated dc−dc
converter such as a SEPIC or a boost is an option as shown
in the below figure:
4−10 V
L1
35uH
R9
24.9k
U1
NCV12711
R8
9.1k
D1
1N4148
D2
MBRS320
3.9 V/3 V
FB
VIN
UVLO
10
9
1
2
9
1
12 V/1 A
6
3
FB
VCC
R1
22
2
4
C6
2.2uF
R4
59k
Q1
NTHS5404T1
R7
50k
SS
DRV
GND
CS
11 3
10 4
13 5
8
5
C5
0.39u
RT
7
R3
330
14
8
C2
680u
FB
COMP
6
7
C4
15n
C3
22n
MSOP10
=250 kHz
C8
R10
10n 4.64k
R6
43k
R2
0.055
F
C1
100p
R5
15.5k
sw
0 V
0 V
Figure 51. Here an Example of a 250−kHz−operated 12−W Boost Converterc delivers 12 V
Finally, it is also possible to use the NCV12711 as a
high−side controller, for instance to build
primary−side−regulated flyback converter operated without
an auxiliary winding:
a
Figure 52. A 100−kHz−operated 12−W Flyback Converter Delivering 12 V without Auxiliary Winding
With a 12−V output, the reflected voltage imposes a
maximum input voltage limited to 38 V. It can be increased
if V takes on a lower value.
out
www.onsemi.com
23
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
MSOP10, 3x3
CASE 846AE
ISSUE A
SCALE 1:1
DATE 20 JUN 2017
A
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
D
F
B
10
6
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 MM IN
EXCESS OF MAXIMUM MATERIAL CONDITION.
q
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15
MM PER SIDE. DIMENSION E DOES NOT INCLUDE INTER-
LEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 MM PER SIDE.
DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DATUMS A AND B TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE
SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE
BODY.
E
E1
L
L2
C
L1
DETAIL A
PIN ONE
INDICATOR
1
5
e
10X b
M
S
S
0.08
C
B
A
TOP VIEW
MILLIMETERS
DETAIL A
DIM MIN
NOM
−−−
0.05
0.85
−−−
−−−
3.00
4.90
3.00
MAX
1.10
0.15
0.95
0.27
0.23
3.10
5.05
3.10
A
A
A1
A2
b
c
D
E
E1
e
−−−
0.00
0.75
0.17
0.13
2.90
4.75
2.90
A1
0.10 C
c
SEATING
PLANE
C
END VIEW
SIDE VIEW
0.50 BSC
0.70
L
0.40
0.80
L1
L2
q
0.95 REF
0.25 BSC
−−−
RECOMMENDED
0°
8°
SOLDERING FOOTPRINT*
10X
GENERIC
MARKING DIAGRAM*
0.85
10X
0.29
10
5.35
XXXX
AYWG
G
1
0.50
XXXX
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PITCH
A
Y
W
G
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present and may be in
either location. Some products may not
follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34098E
MSOP10, 3X3
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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