NCT80DBR2G [ONSEMI]
Hardware Monitor with I2C Serial Interface;
| 型号： | NCT80DBR2G |
| 厂家： | 
ONSEMI |
| 描述： | Hardware Monitor with I2C Serial Interface |
| 文件： | 总28页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCT80
Hardware Monitor with I2C
Serial Interface
The NCT80 is a two−wire serially programmable hardware monitor.
It can monitor its on chip temperature via its local sensor, 7 analog
inputs and measure the speed of two fans. Each of the measured values
are compared with programmable limits and if any channel is outside
the programmed limit an interrupt is generated via the INT output pin.
It also has a chassis intrusion detection input pin which is latched on
an intrusion event.
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Communication with the NCT80 is accomplished via the I C
interface which is compatible with industry standard protocols.
Through this interface the NCT80s internal registers may be accessed.
These registers allow the user to read the current temperature, fan
speed and voltages, change the configuration settings and adjust each
channels limits.
TSSOP−24
DB SUFFIX
CASE 948H
The NCT80 is available in a 24−lead TSSOP package and operates
over a wide supply range of 2.8 to 5.75 V. This makes the NCT80 ideal
for a wide variety of applications ranging from computers to servers
and test equipment.
XXXXX
XXXXG
ALYW
Features
• On−chipTemperature Sensor
• 2 Fan Speed Monitoring Inputs
• 7 Analog Inputs for Voltage Monitoring
• Chassis Intrusion Detection
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
• Overtemperature Output
• Limit Comparison of Monitored Channels
• 3 Address Selection Pins
PIN CONNECTIONS
1
• Power Saving Shutdown Mode
A2
A1
INT_IN
SDA
2
• I C Compliant Interface
SCL
A0/NTEST_OUT
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
AIN0
TACH1
TACH2
BTI
AIN1
Compliant
AIN2
AIN3
CI
AIN4
GND
AIN5
V
DD
AIN6
INT
GPO
AGND
RST_OUT/
RST_IN/
THERM
NTEST_IN
(Top View)
ORDERING INFORMATION
†
Device
NCT80DBR2G
Package
Shipping
TSSOP−24
(Pb−Free)
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
July, 2012 − Rev. 0
NCT80/D
NCT80
A2 A1 A0
SDA
SCL
2
3
24
22
23
ON−CHIP
TEMPERATURE
SENSOR
11
GPO
I2C INTERFACE
12 NTEST_IN/
RST_IN
21
20
AIN0
AIN1
Limit and
Config
Registers
19
18
17
AIN2
AIN3
AIN4
AIN5
Data
Registers
A−TO−D
ANALOG
MUX
10
INT
CONVERTER
RST_OUT/
THERM
13
Interrupt
Control
16
AIN6 15
CI
TACH1
Status Register
4
Fan
Speed
Counter
5
NCT80
TACH2
1
8
14
7
6
9
V
DD
AGND
CI BTI INT_IN
GND
Figure 1. Functional Block Diagram of NCT80
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
2
3
4
5
6
INT_IN
SDA
Active low digital input. This signal is propagated to the INT output pin of the NCT80.
2
I C Serial Bi−directional Data Input/Output. Open−drain pin; needs a pull−up resistor.
SCL
Serial Clock Input. Open−drain pin; needs a pull−up resistor.
Digital Input. Fan tachometer input to measure speed of Fan.
Digital Input. Fan tachometer input to measure speed of Fan.
TACH1
TACH2
BTI
Digital Input. Board Temperature Interrupt driven by O.S. outputs of additional temperature sensors
such as the NCT75.
7
CI
Digital I/O. An active high input from an external latch which captures a Chassis Intrusion event.
This line can go high without any clamping action, regardless of the powered state of the NCT80
(Chassis Intrusion)
8
9
GND
Power Supply Ground.
V
DD
Positive Supply Voltage. Bypass to ground with a 0.1 mF bypass capacitor.
Digital Output. Open drain Interrupt Request pin.
10
11
INT
GPO
Digital Output. An active low open drain output intended to drive an external
P−channel power MOSFET in order to offer software power control.
12
13
NTEST_IN/RST_IN
RST_OUT/THERM
Dual function pin. Active low input that enables NAND Tree Test functionality. Once enabled the part
is reset to its power on default.
Dual function pin. RST_OUT: Active low reset output pin. THERM:
Overtemperature shutdown output pin.
14
15
16
17
18
19
20
21
22
AGND
AIN6
Analog Ground.
Analog Input. 0 V to 2.56 V.
Analog Input. 0 V to 2.56 V.
Analog Input. 0 V to 2.56 V.
Analog Input. 0 V to 2.56 V.
Analog Input. 0 V to 2.56 V.
Analog Input. 0 V to 2.56 V.
Analog Input. 0 V to 2.56 V.
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
2
A0/NTEST_OUT
Dual function pin. Functions as an I C address selection bit. This is the LSB of the address. Pin also
functions as an output when performing a NAND test.
2
23
24
A1
A2
Functions as an I C address selection bit.
2
Functions as an I C address selection bit.
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NCT80
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
Supply Voltage (V
)
V
DD
−0.3 to +6.5
DD
Voltage on any input or output pin
Input Current at any pin
−0.3 to V + 0.3
V
DD
I
5
150.7
mA
°C
°C
V
IN
Maximum Junction Temperature
Storage Temperature Range
T
J(max)
T
STG
−65 to 160
2500
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
ESD
ESD
HBM
CDM
1000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Table 3. OPERATING RANGES
Rating
Symbol
Min
2.8
Max
5.75
125
Unit
V
Operating Supply Voltage
Operating Ambient Temperature Range
V
DD
T
A
−40
°C
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Table 4. ELECTRICAL CHARACTERISTICS
(T = T
to T , V = 2.8 V to 5.75 V. All specifications for −40°C to +125°C, unless otherwise noted.)
MAX DD
A
MIN
Parameter
Test Conditions
Min
Typ
Max
Unit
POWER SUPPLY CHARACTERISTICS
Supply Voltage
2.8
5.75
V
Supply Current
Interface inactive
0.580
mA
mA
Shutdown Current
Shutdown mode enabled
200
TEMPERATURE TO DIGITAL CONVERTER CHARACTERISTICS
Local Sensor Accuracy
T = 0°C to +100°C
2
3
°C
°C
°C
A
V
= 2.8 V to 5.75 V
DD
T = −40°C to +125°C
A
Resolution
0.0625
ANALOG−to−DIGITAL CONVERTER CHARACTERISTICS
ADC Resolution (bits)
10
Bits
mV
%
Resolution (10 bits with full−scale at 2.56 V)
Total Unadjusted Error (TUE)
2.5
1
1
Differential Nonlinearity (DNL)
LSB
ms
Round Robin Cycle Time
662
728
810
MULTIPLEXER/ADC INPUT CHARACTERISTICS
On resistance
11.5
13
kW
mA
mA
Input current (on channel leakage current)
Off channel leakage current
0.005
0.005
FAN RPM−to−DIGITAL CONVERTER
Fan RPM Error
T = −40°C to +125°C
A
10
%
Full scale count
255
(max)
rpm
TACH1 & TACH2 Nominal Input RPM
Divisor = 1, Fan count = 153
8800
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NCT80
Table 4. ELECTRICAL CHARACTERISTICS
(T = T
to T , V = 2.8 V to 5.75 V. All specifications for −40°C to +125°C, unless otherwise noted.)
MAX DD
A
MIN
Parameter
Test Conditions
Min
Typ
Max
Unit
FAN RPM−to−DIGITAL CONVERTER
TACH1 & TACH2 Nominal Input RPM
Divisor = 2, Fan count = 153
Divisor = 3, Fan count = 153
Divisor = 4, Fan count = 153
4400
2200
1100
22.5
rpm
rpm
rpm
kHz
Internal Clock Frequency
20.2
2.4
24.8
0.4
DIGITAL OUTPUTS (A0/ NTEST_OUT, INT)
Output high voltage, logical “1”
Output low voltage, logical “0”
I
= +5.0 mA, V = 2.8 V – 5.75 V
V
V
OUT
DD
I
= −5.0 mA, V = 2.8 V – 5.75 V
DD
OUT
OPEN DRAIN OUTPUTS (GPO, RST_OUT/OS, CI, SDA)
Output low voltage, logical “0”
High level output current
RST_OUT/OS, CI pulse width
DIGITAL INPUTS (Except for BTI)
Input high voltage, logical “1”
Input low voltage, logical “0“
ALL DIGITAL INPUTS (Except for BTI)
Input current (Logical “1“)
Input current (Logical “0“)
Input capacitance
I
= +5.0 mA, V = 3.6 V
0.4
1
V
OUT
DD
V
OUT
= V
0.1
mA
ms
DD
10
22.5
0.7 x V
V
V
DD
0.3 x V
DD
V
IN
= V
−1
−0.005
0.005
20
mA
mA
pF
DD
V
IN
= 0 V
1
BTI DIGITAL INPUT
Input current (Logical “1“)
Input current (Logical “0“)
Input capacitance
V
= V
−10
mA
mA
pF
IN
DD
V
= 0 V
2000
IN
20
Table 5. I2C TIMING
Parameter (Note 4)
Clock Frequency
Clock Period
Symbol
Min
10
Typ
Max
Unit
kHz
ms
f
400
100
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
2.5
Data Setup Time (Note 5)
Data Out Stable
Start Hold Time (Note 6)
Stop Setup Time
SCL High Time
ns
100
0
0.9
ms
ns
100
100
ns
0.6
1.3
0.6
ms
SCL Low Time
ms
Start Setup Time
SCL, SDA Rise Time
SCL, SDA Fall Time
Bus Free Time
ms
300
300
ns
t
10
ns
t
1.3
0
ms
11
12
Glitch Immunity
t
50
35
ns
Timeout
t
25
ms
Timeout
4. Guaranteed by design, but not production tested.
5. Time for 10% or 90% of SDA to 10% of SCL.
6. Time from 10% of SDA to 90% of SCL.
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NCT80
TYPICAL CHARACTERISTICS
600
500
400
300
200
600
500
400
300
200
100
0
100
0
2.8
3.3
3.8
4.3
(V)
4.8
5.3
5.8
2.8
3.3
3.8
4.3
(V)
4.8
5.3
5.8
V
V
DD
DD
Figure 2. Supply Current vs. VDD
Figure 3. Supply Current vs. VDD
(Voltage Conversion)
600
500
400
300
200
600
500
400
300
200
100
0
100
0
2.8
3.3
3.8
4.3
(V)
4.8
5.3
5.8
2.8
3.3
3.8
4.3
(V)
4.8
5.3
5.8
V
V
DD
DD
Figure 4. Supply Current vs. VDD
(Temperature Conversion)
Figure 5. Shutdown Current vs. VDD
1.0
0.8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.6
0.4
0.2
0
15
16
17
18
19
20
21
22
23
24
25
26
28
29
−0.2
−0.4
−0.6
−0.8
−1.0
2.8
3.0
3.3
3.6 4.125 4.5
(V)
5.0
5.75
V
DD
Figure 6. TUE vs. Code
Figure 7. Local Temp Error vs. VDD
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NCT80
t
10
t
9
t
4
t
7
SCL
SDA
t
6
t
t
8
4
t
5
t
3
t
2
t
11
STOP
START
STOP
START
Figure 8. Serial Interface Timing
Theory of Operation
and the temperature sensor resolution. The resolution can be
configured either 9 bit or 12 bit. Bit 3 enables 12−bit
temperature conversions. In 12−bit mode, bits 4 to 7
represent the four LSBs of the temperature measurement. In
9−bit mode, bit 4 represents the LSB of the temperature
measurement.
The NCT80 contains an on chip local temperature sensor,
an 8 channel multiplexer, a 10 bit sigma−delta analog to
digital converter and different internal registers in a single
package. It has the capability to monitor 7 analog inputs
AIN0−AIN6. The effective use of these analog inputs can be
accomplished by connecting them to monitor different power
supplies level present in any communication system. It also
has two fan speed measurement inputs that can be configured
either as fan failure signal or the tachometer signal. The fan
inputs are digital signals with transition levels according to
the fan tach pulse inputs in the electrical characteristics
table. The signal conditioning circuitry is present on the chip
to accommodate slow rise and fall times. The nominal fan
speeds are programmable from 1100 to 8800 RPM (based on
count of 153). Full scale fan counts are 255 (8bit counter)
which represents a very slow or stopped fan.
Conversion Rate Register: This register can be accessed to
control the conversion rate of the ADC.
Channel Add/Remove Register: This register can be
accessed by the user to manually add or remove
measurement channels from the ADC.
RAM Registers: The results for monitoring fan counts,
temperature, voltages etc are all contained in it. It consists
of 31 bytes with the first 10 bytes are the results and the next
20 bytes are the interrupt alarm limit registers. Limit values
for analog measurements are stored in the appropriate limit
registers. In the case of voltage measurements, high and low
limits can be stored so that an interrupt request will be
generated if the measured value goes above or below
acceptable values. In the case of temperature, a Hot
Temperature (high limit), and a Hot Temperature Hysteresis
(low limit) can be programmed. The hysteresis value is
usually a few degrees lower than the high limit. These limits
allow the system to be shut down when the hot limit is
exceeded and restarted automatically when the temperature
has dropped below the hysteresis limit.
The communication interface with the device is
2
accomplished by an I C interface that is compatible to both
Standard Mode and Fast Mode operations. The standard and
fast modes correspond to 100 kHz and 400 kHz. NCT80 also
has a three address selection pins A0−A2 that facilitate the
use of eight devices on a single bus.
Internal Registers
In this section the overview of important internal registers
is presented. NCT80 contains 41 internal registers the details
of whom can be seen in the register map section.
The last byte is the upper locations for manufacturer ID.
Configuration Register: This register can be accessed for
control and configuration.
Application Details
Interrupt Status Registers: There are two registers that
provide the status of each interrupt alarm. Continuous
reading of the status register can make the bits in the register
toggle intermittently and momentarily clears the INT pin also.
Power−ON_RESET
When NCT80 is turned ON by applying power to V pin
DD
it undergoes to a reset mode where most of the internal
registers are reset. The Interrupt and RAM registers do not
reset on power ON and their values are determined
immediately after the reset process. The configuration
register bit 7 has the same function as the power ON reset.
This bit can be set to 1 to initiate the reset process which
clears automatically afterwards.
Interrupt Mask Registers: These registers can be accessed
for masking of individual interrupt sources, as well as
separate masking for both hardware interrupt outputs.
Fan Divisor Output pin Configuration: This register can
be accessed to configure fan reading modes and also the OS
and RST_OUT pin configuration. Bits 0 to 5 of this register
contain the divisor bits for the TACH1 and TACH2 inputs.
Bits 6 and 7 control the function of the RST_OUT/OS output.
Initiating Inputs Monitoring
The monitoring cycle of the NCT80 begins when a one is
written to the Start bit (bit 0) and a zero to the INT_Clear bit
(bit 3) of the Configuration Register. When the NCT80
monitoring sequence is started, it cycles sequentially
OS Configuration/Temperature Resolution Register:
This register can be accessed to configure the OS output pin
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NCT80
through the measurement of the 7 analog inputs. Each input
is multiplexed separately into the NCT80’s 10 bit ADC and
The selection of resistors value can be simplified by first
selecting the value of R . The value of R should be high
2
2
stored in the appropriate value register. The on−chip
temperature sensor is monitored through a 12 bit sigma delta
enough to protect both inputs under overdrive conditions
and must be low enough to avoid leakage current errors. A
ADC giving the temperature a resolution of 0.0625°C. At
typical value for R with in 10 kW−100 kW range will serve
this purpose. The value of R1 then can be selected to provide
1.9 V at the AINx pins as follows:
2
the same time the fan speed inputs are independently
monitored. Once each conversion is completed the data is
compared with programmed limits stored in the limit
registers of RAM. It can then be read back over the serial bus.
The sequence of items that are monitored except for the
temperature reading corresponds to locations in the RAM
registers as follows:
1. Temperature
2. AIN0
Supply * 1.9
R1 +
R2
1.9
It is necessary to limit input currents to avoid the Absolute
maximum rating value. Extra external resistors must be used
to achieve this at any pin.
Temperature Measurement
Temperature data can be read from the Temperature
Reading Register at 27h. Temperature limits can be read
from and written to the Hot Temperature, Hot Temperature
Hysteresis, OS Temperature, and OS Temperature
Hysteresis Limit Registers. These registers have addresses
from 38h to 3Bh respectively. The temperature data limit is
represented by 8 bit, 9 bit and 12 bit two’s complement word
with an LSB equal to 1°C.
3. AIN1
4. AIN2
5. AIN3
6. AIN4
7. AIN5
8. AIN6
9. TACH 1
10. TACH 2
Reading Results
Table 6. 8 BIT TEMPERATURE DATA REPRESENTATION
The conversion results are stored in the value registers at
addresses from 20h to 29h. These conversion results can be
read at any time and correspond to the result of the last
conversion. A typical sequence of events after NCT80
power−on is as follows:
Temperature
+125°C
+25°C
+1°C
Binary Output
0111 1101
0001 1001
0000 0001
0000 0000
1111 1111
HEX Output
7Dh
19h
01h
1. Set alarm limits
2. Set interrupt masks
3. Start the NCT80 monitoring process
+0°C
00h
−1°C
FFh
−25°C
−55°C
1110 0111
1100 1001
E7h
Analog Inputs
C9h
NCT80 has a 10−bit ADC which has an LSB value of
2.5 mV. The input has a full scale input range of 0 to 2.56 V.
The analog inputs are often connected to power supplies
whose values can be 2.5, 3.3, 5 or 12 V. This poses a
requirement to attenuate the voltage inputs within the
acceptable input range of the ADC.
Voltage divider can be used to attenuate the analog input
voltages with in the desired range. For any applications a
voltage divider with an output signal of 1.9 V to the analog
inputs will be an appropriate selection. This selection will give
a tolerance for upward excursion in the power supply of 25%.
Table 7. 9 BIT TEMPERATURE DATA REPRESENTATION
Temperature
+125°C
+25°C
Binary Output
0 1111 1010
0 0011 0010
0 0000 0011
0 0000 0000
1 1111 1111
1 1100 1110
1 1001 0010
HEX Output
0 FAh
0 32h
+1.5°C
+0°C
0 03h
0 00h
−0.5°C
−25°C
1 FFh
1 CEh
1 92h
Supply
−55°C
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
R
1
10−bit ADC &
Multiplexer
0−2.56 Vin
R
2
AIN6
Temperature
Figure 9. Resistor Divider to Attenuate the Power
Supply Voltage within Required Range
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NCT80
Comparator Mode
In Comparator mode, exceeding T causes the OS output
to go low (default) and remain low until the temperature falls
Table 8. 12 BIT TEMPERATURE DATA REPRESENTATION
OS
Temperature
+125°C
+25°C
Binary Output
0111 1101 0000
0001 1001 0000
0000 0001 0000
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 0000
1110 0111 0000
1100 1001 0000
HEX Output
7 D0h
1 90h
below T _HYST. When the temperature falls below
OS
T _HYST, OS goes high.
OS
+1°C
0 10h
Chassis Intrusion
A chassis intrusion input (pin 7) is provided to detect
unauthorised tampering with the equipment.
+0.0625°C
+0°C
0 01h
0 00h
−0.0625°C
−1.0°C
F FFh
F F0h
RESET
A RESET input (pin 12) and RESET output (pin 13) is
also provided. Pulling the input pin low will reset all the
NCT80 internal registers to their default values. This pin
must be pulled high in order for the user to be able to
configure the device.
−25°C
E 70h
−55°C
C 90h
When using a single−byte read, the eight MSBs of the
temperature reading can be found in the Value RAM
Register at 27h. The remainder of the temperature reading
can be found in the OS_CONFIG_TEMP_RESOLUTION
Register at address 06h, bits 4 to 7. In 9−bit format, bit 7 is
the only valid bit. In addition, all nine or 12 bits can be read
using a double−byte read at register address 27h.
The RESET output is at least 10 ms.
ADC Converter
The analog inputs (AIN0−AIN6) are multiplexed into the
on−chip successive approximation, analog−digital converter.
This has a resolution of 10 bits. The basic input range is zero
to 2.56 V.
When the ADC is running, it samples and converts an
input every 728 ms, except for the internal temperature. This
is converted using a sigma delta ADC.
Temperature Interrupts
There are four Value RAM Register limits for the
temperature reading that affect the INT and OS outputs of the
NCT80. These are the HOT_TEMP_HIGH_LIMIT (HTHL),
Fan Monitoring Cycle Time
HOT_TEMP_HYSTERESIS_LIMIT
(HTHT_HYST),
When a monitoring cycle is started, monitoring of the fan
speed inputs begins at the same time as monitoring of the
analog inputs. However, the two monitoring cycles are not
synchronized in any way. The monitoring cycle time for the
fan inputs is dependent on fan speed and is much slower than
for the analog inputs. The monitoring cycle time depends on
the fan speed and number of tach output pulses per
revolution. Two complete periods of the fan tach output
(three rising edges) are required for each fan measurement.
Therefore, if the start of a fan measurement just misses a
rising edge, the measurement can take almost three tach
periods. In order to read a valid result from the fan value
registers, the total monitoring time allowed after starting the
monitoring cycle should, therefore, be three tach periods of
TACH1 plus three tach periods of TACH2 at the lowest
normal fan speed.
OS_TEMP_HIGH_LIMIT (TOS) and OS_TEMP_
HYSTERESIS_LIMIT (T _HYST) having address from
OS
38h−3Bh.
There are three interrupt modes of operation: Default
Interrupt, One−Time Interrupt, and Comparator. The OS
output of the NCT80 can be programmed for One−Time
Interrupt mode and Comparator mode. INT can be
programmed for Default Interrupt mode and One−Time
Interrupt mode. These modes are explained in the following
subsections.
Default Interrupt Mode
In Default Interrupt mode, exceeding HTHL causes an
interrupt that remains active indefinitely until reset by
reading Interrupt Status Register 1 at address 01h or cleared
by the INT_Clear bit in the Configuration Register at
address 00h, bit 3. When an interrupt event has occurred by
exceeding HTHL, and is then reset, another interrupt occurs
again when the next temperature conversion has completed.
The interrupts continue to occur in this manner until the
temperature falls below HTHL_HYST, at which time the
interrupt output automatically clears.
Fan Inputs
Pins 4 and 5 are fan speed inputs. Signal conditioning in
the NCT80 accommodates the slow rise and fall times
typical of fan tachometer outputs. The maximum input
signal range is 0 to VCC. In the event that these inputs are
supplied from fan outputs that exceed 0 V to 6.5 V, either
resistive attenuation of the fan signal or diode clamping
must be included to keep inputs within an acceptable range.
Figure 10 to Figure 13 show circuits for most common fan
tach outputs. If the fan tach output has a resistive pull−up to
VCC it can be directly connected to the fan input, as shown
in Figure 10.
One−Time Interrupt Mode
In One−Time Interrupt mode, exceeding HTHL causes an
interrupt that remains active indefinitely until reset by
reading Interrupt Status Register 1 or cleared by the
INT_Clear bit in the Configuration Register. When an
interrupt event has occurred by exceeding HTHL, and is
then reset, an interrupt does not occur again until the
temperature falls below HTHL_HYST.
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8
NCT80
Figure 10. Fan with Tach. Pull−Up to +VCC
If the fan output has a resistive pull−up to 12 V (or other voltage greater than 6.5 V), the fan output can be clamped with a
zener diode, as shown in Figure 11. The zener voltage should be chosen so it is greater than VIH but less than 6.5 V, allowing
for the voltage tolerance of the zener. A value of between 3 V and 5 V is suitable.
Figure 11. Fan with Tach. Pull−Up to Voltage >6.5 V
If the fan has a strong pull−up (less than 1 kW) to 12 V, or a totem−pole output, then a series resistor can be added to limit
the zener current, as shown in Figure 12. Alternatively, a resistive attenuator may be used, as shown in Figure 13. R1 and R2
should be chosen such that:
R2
2 V t Vpull−up
ǒR
Ǔ t 5 V
pull−up ) R1 ) R2
The fan inputs have an input resistance of nominally 160 kW to ground, so this should be taken into account when calculating
resistor values. With a pull−up voltage of 12 V and pull−up resistor less than 1 kW, suitable values for R1 and R2 would be
100 kW
Figure 12. Fan with Strong Tach. Pull−Up to >VCC or Totem−Pole Output, Clamped with Zener and Resistor
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9
NCT80
Figure 13. Fan with Strong Tach. Pull−Up to >VCC or Totem−Pole Output, Attenuated with R1/R2
Fan Speed Measurement
the fan revolution is measured by gating an on−chip
22.5 kHz oscillator into the input of an 8−bit counter for two
periods of the fan tach output, as shown in Figure 14; the
accumulated count is actually proportional to the fan tach
period and inversely proportional to the fan speed.
The fan counter does not count the fan tach output pulses
directly, because the fan speed may be less than 1000 rpm
and it would take several seconds to accumulate a
reasonably large and accurate count. Instead, the period of
22.5 kHz
CLOCK
CONFIGURATION
REG. 1 BIT 0
2
1
3
4
FAN0
INPUT
1
2
3
4
FAN1
INPUT
START OF
MONITORING
CYCLE
FAN0
MEASUREMENT
PERIOD
FAN1
MEASUREMENT
PERIOD
Figure 14. Fan Speed Measurement
The measurement begins on the rising edge of a fan tach
pulse, and ends on the next−but−one rising edge. The fans
are monitored sequentially, so if only one fan is monitored
the monitoring time is the time taken after the Start Bit for
it to produce two complete tach cycles or for the counter to
reach full scale, whichever occurs sooner. If more than one
fan is monitored, the monitoring time depends on the speed
of the fans and the timing relationship of their tach pulses.
This is illustrated in Figure 14. Once the fan speeds have
been measured, they will be stored in the Fan Speed Value
Registers and the most recent value can be read at any time.
The measurements will be updated as long as the monitoring
cycle continues. To accommodate fans of different speed
and/or different numbers of output pulses per revolution, a
prescaler (divisor) of 1, 2, 4, or 8 may be added before the
counter. The default value is 2, which gives a count of 153
for a fan running at 4400 rpm producing two output pulses
per revolution. The count (stored in the TACH registers) is
calculated by the equation:
(22.5 103 60)
(rpm Divisor)
Count +
3
22.5x10 = oscillator frequency
Divisor = number of poles in the fan
Fan Limit Values
Fans in general will not over speed if run from the correct
voltage, so the failure condition of interest is under speed
due to electrical or mechanical failure. For this reason only,
low−speed limits are programmed into the limit registers for
the fans. It should be noted that, since fan period rather than
speed is being measured, a fan failure interrupt will occur
when the measurement exceeds the limit value.
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NCT80
Table 9. REGISTER MAP
Register Name
Type
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Reset Value
0x08
Address Offset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
CONFIGURATIONREGISTER
STATUSREGISTER1
STATUSREGISTER2
MASKREGISTER1
MASKREGISTER2
FAN_DIVISOR_OUTPUT_PIN_CONFIG
OS_CONFIG_TEMP_RESOLUTION
CONVERSION_RATE
CHANNEL_SELECT_REGISTER
CONVERSION_RATE
IN0_READING
0x00
0x00
0x00
0x00
0x14
0x01
0x00
0x00
0x00
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00
IN1_READING
IN2_READING
IN3_READING
IN4_READING
IN5_READING
IN6_READING
TEMP_READING
TACH1_READING
TACH2_READING
0x00
IN0_HIGH_LIMIT
0x00
IN0_LOW_LIMIT
0x00
IN1_HIGH_LIMIT
0x00
IN1_LOW_LIMIT
0x00
IN2_HIGH_LIMIT
0x00
IN2_LOW_LIMIT
0x00
IN3_HIGH_LIMIT
0x00
IN3_LOW_LIMIT
0x00
IN4_HIGH_LIMIT
0x00
IN4_LOW_LIMIT
0x00
IN5_HIGH_LIMIT
0x00
IN5_LOW_LIMIT
0x00
IN6_HIGH_LIMIT
0x00
IN6_LOW_LIMIT
0x00
HOT_TEMP_HIGH_LIMIT
HOT_TEMP_HYSTERESIS_LIMIT
OS_TEMP_HIGH_LIMIT
OS_TEMP_HYSTERESIS_LIMIT
TACH1_COUNT_LIMIT
TACH2_COUNT_LIMIT
MANUFACTURERID
0x00
0x00
0x00
0x00
0x00
0x00
0x1A
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NCT80
CONFIGURATIONREGISTER
Register Information
Description
Offset
Allows the user to configure many features of the NCT80 device.
0x00
Bitfield Details
Description
Field
Name
Access Default
7
INITIALIZATION
Setting this bit to 1 resets the main user writeable registers to their power on
default values.
RW
0
6
5
GPO
Setting this bit to 1 drives the GPO pin low.
RW
RW
0
0
Chassis_clear
Setting this bit to 1 clears the GPI (chassis intrusion pin).
After 10 ms this bit self clears.
4
3
2
RESET
Setting this bit to 1 outputs at least a 10 ms RESET (active low) pulse on
RST_OUT. If bits 7 and 6 of register 0x05 are set to 1 and 0 respectively
then this RESET bit is cleared once the pulse is inactive.
RW
RW
RW
0
1
0
INT_clear
Setting this bit to 1 disables the INT output. This does not affect the Interrupt
Status Registers/ The device will stop monitoring temperature and voltage.
Monitoring will resume upon the clearing of this bit.
INT_polarity_select Setting this bit to 1 selects an active high output while setting it to 0 selects
active low output.
1
0
INT_en
Start
Setting this bit to 1 enables the INT output.
RW
RW
0
0
Setting this bit to 1 enables the monitoring of temperature, voltage and fan
readings. Setting this bit to 0 disables these monitoring operations and
effectively puts the device in shutdown mode.
STATUSREGISTER1
Register Information
Description
Offset
Register to indicate if a high or low limit has been exceeded.
0x01
Bitfield Details
Field
Name
INT_IN
IN6
Description
Access Default
7
6
5
4
3
2
1
0
The NCT80 sets this bit to 1 if a low has been detected on the INT_IN pin.
The NCT80 sets this bit to 1 if the high or low limit has been exceeded.
The NCT80 sets this bit to 1 if the high or low limit has been exceeded.
The NCT80 sets this bit to 1 if the high or low limit has been exceeded.
The NCT80 sets this bit to 1 if the high or low limit has been exceeded.
The NCT80 sets this bit to 1 if the high or low limit has been exceeded.
The NCT80 sets this bit to 1 if the high or low limit has been exceeded.
The NCT80 sets this bit to 1 if the high or low limit has been exceeded.
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
IN5
IN4
IN3
IN2
IN1
IN0
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NCT80
STATUSREGISTER2
Register Information
Description
Offset
Register to indicate if a high or low limit has been exceeded.
0x02
Bitfield Details
Description
Field
7:6
5
Name
Reserved
OS_bit
Access Default
RO
RO
0x0
0
The NCT80 sets this bit to 1 if the temperature exceeds either the high or
low OS limit. The interrupt mode can be selected in register 0x04 bit 7.
4
3
2
1
GPI
TACH2
TACH1
BTI
The NCT80 sets this bit to 1 if the GPI (chassis intrusion) pin has gone high.
The NCT80 sets this bit to 1 if the fan speed limit has been exceeded.
The NCT80 sets this bit to 1 if the fan speed limit has been exceeded.
RO
RO
RO
RO
0
0
0
0
If this bit is set to 1 then it indicates that an interrupt has occurred on the
Board Temperature Input (BTI) pin.
0
Temperature
The NCT80 sets this bit to 1 if the temperature exceeds either the high or
low limit. The interrupt mode can be selected in register 0x04 bit 6.
RO
0
MASKREGISTER1
Register Information
Description
Offset
Register to mask out of limit conditions shown in the corresponding status register.
0x03
Bitfield Details
Field
Name
Description
Access Default
7
6
5
4
3
2
1
0
INT_IN
IN6
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
IN5
IN4
IN3
IN2
IN1
IN0
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NCT80
MASKREGISTER2
Register Information
Description
Offset
Register to mask out of limit conditions shown in the corresponding status register.
0x04
Bitfield Details
Description
Field
Name
Access Default
RW 0
7
Mode_select_OS_
temp_interrupt
Writing zero to this bit selects the default interrupt mode which gives the user an
interrupt if the temperature goes above the OS limit. The interrupt will be cleared
once the status register is read, but it will again be generated when the next
conversion has completed. It will continue to do so until the temperature goes
below the hysteresis limit.
Writing a 1 to this bit selects the one time interrupt mode which only gives the
user one interrupt when it goes above the OS limit. The interrupt will be cleared
once the status register is read. Another interrupt will not be generated until the
temperature goes below the hysteresis limit. It will also be cleared if the status
register is read. No more interrupts will be generated until the temperature goes
above the OS limit again. The corresponding bit will be cleared in the status
register every time it is read but may not set again when the next conversion is
done.
6
Mode_select_hot_
temp_interrupt
Writing zero to this bit selects the default interrupt mode which gives the user an
interrupt if the temperature goes above the hot limit. The interrupt will be cleared
once the status register is read, but it will again be generated when the next
conversion has completed. It will continue to do so until the temperature goes
below the hysteresis limit.
RW
0
Writing a 1 to this bit selects the one time interrupt mode which only gives the
user one interrupt when it goes above the hot limit. The interrupt will be cleared
once the status register is read. Another interrupt will not be generated until the
temperature goes below the hysteresis limit. It will also be cleared if the status
register is read. No more interrupts will be generated until the temperature goes
above the hot limit again. The corresponding bit will be cleared in the status
register every time it is read but may not set again when the next conversion is
done.
5
4
3
2
1
0
OS_bit
GPI
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
Writing a 1 to this bit disables the corresponding status bit for the INT output.
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
TACH2
TACH1
BTI
Temperature
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NCT80
FAN_DIVISOR_OUTPUT_PIN_CONFIG
Register Information
Description
Offset
This register allows the user to configure the TACH reading modes and also the OS and RST_OUT
pin configuration.
0x05
Bitfield Details
Field
Name
Description
Access
Default
7
RST_en
Setting this bit to 1 enables the RST_OUT functionality on the RST_OUT / OS
output pin. If bits 6 and 7 are set to 0 then this pin is disabled.
RW
0
6
OS_pin_en
Setting this bit to 1 enables the OS functionality on the RST_OUT / OS output
pin. For the OS pin to function, bit 7 of this register must be set to 0. If bits 6
and 7 are set to 0 then this pin is disabled.
RW
RW
0
5:4
TACH2_divisor
If level sensitive input is selected setting bit <4> = 1 selects and active−low
input (An interrupt will be generated if the TACH2 input is Low), if bit <4> = 0
selects an active−high input (an interrupt will be generated if the TACH2
input is High).
0x1
0x0:
0x1:
0x2:
0x3:
Divide by 1
Divide by 2
Divide by 4
Divide by 8
3:2
TACH1_divisor
If level sensitive input is selected setting bit <2> = 1 selects and active−low
input (An interrupt will be generated if the TACH1 input is Low), if bit <2> = 0
selects an active−high input (an interrupt will be generated if the TACH1 input
is High).
RW
0x1
0x0:
0x1:
0x2:
0x3:
Divide by 1
Divide by 2
Divide by 4
Divide by 8
1
0
TACH2_mode
TACH1_mode
Setting this bit to 1 selects the level sensitive input mode.
Setting this bit to 0 selects TACH Count Mode for the input pin.
RW
RW
0
0
Setting this bit to 1 selects the level sensitive input mode.
Setting this bit to 0 selects TACH Count Mode for the input pin.
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NCT80
OS_CONFIG_TEMP_RESOLUTION
Register Information
Description
Offset
This register allows the user to configure the OS output pin and also the temperature sensor resolution.
0x06
Bitfield Details
Field
Name
Description
Access
Default
7:4
Temp_resolution
Depending of the state of bit 3 in this register these bits are the LSBs of the
temperature measurement. If 8 bit resolution is selected then bit 7 only is
the LSB of the temperature reading. If 11 bit resolution is selected then bits
7−4 are the LSBs of the temperature data (bit 7 being the most significant
of the 4 bits).
RW
0x0
3
2
1
0
Temp_resolution_
control
Selects either an 8 bit or 11 bit temperature conversion.
RW
RW
RW
RO
0
0
0
1
0:
1:
Selects an 8 bit plus sign temperature conversion.
Selects an 11 bit plus sign temperature conversion.
OS_mode_select
OS_polarity
Selects the mode of operation for the OS pin.
0:
1:
Selects the polarity of the open drain OS pin.
0:
1:
Selects OS to be active low.
Selects OS to be active high.
OS_status
This read only bit mirrors the state of the RST_OUT/OS pin when the OS pin
is enabled.
CONVERSION_RATE
Register Information
Description
Offset
Register to control the conversion rate of the ADC input channels.
0x07
Bitfield Details
Description
Field
7:1
0
Name
Access
RO
Default
0x00
0
Reserved
Conv_rate
RW
0:
1:
Sets the conversion rate to be ever 728 ms (typical).
Sets the NCT80 to operate in continuous conversion mode.
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NCT80
CHANNEL_SELECT_REGISTER
Register Information
Description
Offset
Allows the user to manually add/remove measurement channels from the ADC round robin loop.
0x08
Bitfield Details
Field
Name
Description
Access Default
7
Temp
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0:
1:
This channel is included in the conversion loop.
This channel is disabled and conversions are skipped. Value register
will return 0 and it will not cause an interrupt to be generated.
6
5
4
3
2
1
0
IN6
IN5
IN4
IN3
IN2
IN1
IN0
0:
1:
This channel is included in the conversion loop.
This channel is disabled and conversions are skipped. Value register
will return 0 and it will not cause an interrupt to be generated.
0:
1:
This channel is included in the conversion loop.
This channel is disabled and conversions are skipped. Value register
will return 0 and it will not cause an interrupt to be generated.
0:
1:
This channel is included in the conversion loop.
This channel is disabled and conversions are skipped. Value register
will return 0 and it will not cause an interrupt to be generated.
0:
1:
This channel is included in the conversion loop.
This channel is disabled and conversions are skipped. Value register
will return 0 and it will not cause an interrupt to be generated.
0:
1:
This channel is included in the conversion loop.
This channel is disabled and conversions are skipped. Value register
will return 0 and it will not cause an interrupt to be generated.
0:
1:
This channel is included in the conversion loop.
This channel is disabled and conversions are skipped. Value register
will return 0 and it will not cause an interrupt to be generated.
0:
1:
This channel is included in the conversion loop.
This channel is disabled and conversions are skipped. Value register
will return 0 and it will not cause an interrupt to be generated.
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NCT80
CONVERSION_RATE_PROGRAMMING
Register Information
Description
Offset
Register to add further programmability to the conversion rate of the ADC input channels.
Note Any non−zero value in this register over−rides setting as controlled from register 07h
0x09
Bitfield Details
Field
7:3
Name
Description
Access
Default
0x00
Reserved
Conv_rate
RO
RW
2:0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Use Conversion rate as setup from register 0x07 bit 0
Conversion rate = 1.2 ms
0x0
Conversion rate = 4.8 ms
Conversion rate = 9.6 ms
Conversion rate = 38 ms
Conversion rate = 77 ms
Conversion rate = 154 ms
Conversion rate = 614 ms
IN0_READING
Register Information
Description
Offset
This register stores the data returned on this input channel
0x20
Bitfield Details
Description
Field
Name
Access
RO
Default
15:6
IN0_Data
0x0000
IN1_READING
Register Information
Description
Offset
This register stores the data returned on this input channel
0x21
Bitfield Details
Field
Name
Description
Access
Default
15:6
IN1_Data
RO
0x0000
IN2_READING
Register Information
Description
Offset
This register stores the data returned on this input channel
0x22
Bitfield Details
Field
Name
Description
Access
RO
Default
15:6
IN2_Data
0x0000
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NCT80
IN3_READING
Register Information
Description
Offset
This register stores the data returned on this input channel
0x23
Bitfield Details
Field
Name
Description
Access
RO
Default
15:6
IN3_Data
0x0000
IN4_READING
Register Information
Description
Offset
This register stores the data returned on this input channel
0x24
Bitfield Details
Field
Name
Description
Access
Default
15:6
IN4_Data
RO
0x0000
IN5_READING
Register Information
Description
Offset
This register stores the data returned on this input channel
0x25
Bitfield Details
Field
Name
Description
Access
RO
Default
15:6
IN5_Data
0x0000
IN6_READING
Register Information
Description
Offset
This register stores the data returned on this input channel
0x26
Bitfield Details
Field
Name
Description
Access
Default
15:6
IN6_Data
RO
0x0000
TEMP_READING
Register Information
Description
Offset
This register stores the data returned on the temperature channel
0x27
Bitfield Details
Field
Name
Description
Access
Default
15:4
Temp_Data
RO
0x0000
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NCT80
TACH1_READING
Register Information
Description
Offset
This register stores the number of counts on the TACH1 input pin.
0x28
Bitfield Details
Field
Name
Description
Access
Default
7:0
TACH1_Data
RO
0x00
TACH2_READING
Register Information
Description
Offset
This register stores the number of counts on the TACH2 input pin.
0x29
Bitfield Details
Field
Name
Description
Access
Default
7:0
TACH2_Data
RO
0x00
IN0_HIGH_LIMIT
Register Information
High limit register.
0x2A
Description
Offset
Bitfield Details
Description
Field
Name
Access
Default
7:0
HIGH_LIMIT
RW
0x00
IN0_LOW_LIMIT
Register Information
Description
Offset
Low limit register.
0x2B
Bitfield Details
Description
Field
Name
Access
Default
7:0
LOW_LIMIT
RW
0x00
IN1_HIGH_LIMIT
Register Information
Description
Offset
High limit register.
0x2C
Bitfield Details
Description
Field
Name
Access
Default
7:0
HIGH_LIMIT
RW
0x00
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NCT80
IN1_ LOW _LIMIT
Register Information
Description
Offset
Low limit register.
0x2D
Low limit register.
0x2D
Bitfield Details
Description
Field
Name
Access
Default
7:0
LOW_LIMIT
RW
0x00
IN2_HIGH_LIMIT
Register Information
High limit register.
0x2E
Description
Offset
Bitfield Details
Description
Field
Name
Access
Default
7:0
HIGH_LIMIT
RW
0x00
IN2_LOW_LIMIT
Register Information
Low limit register.
0x2F
Description
Offset
Bitfield Details
Description
Field
Name
Access
Default
7:0
LOW_LIMIT
RW
0x00
IN3_HIGH_LIMIT
Register Information
Description
Offset
High limit register.
0x30
Bitfield Details
Description
Field
Name
Access
Default
7:0
HIGH_LIMIT
RW
0x00
IN3_LOW_LIMIT
Register Information
Low limit register.
0x31
Description
Offset
Bitfield Details
Description
Field
Name
Access
Default
7:0
LOW_LIMIT
RW
0x00
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NCT80
IN4_HIGH_LIMIT
Register Information
Description
Offset
High limit register.
0x32
Bitfield Details
Description
Field
Name
Access
Default
7:0
HIGH_LIMIT
RW
0x00
IN4_LOW_LIMIT
Register Information
Description
Offset
Low limit register.
0x33
Bitfield Details
Description
Field
Name
Access
Default
7:0
LOW_LIMIT
RW
0x00
IN5_HIGH_LIMIT
Register Information
High limit register.
0x34
Description
Offset
Bitfield Details
Description
Field
Name
Access
Default
7:0
HIGH_LIMIT
RW
0x00
IN5_LOW_LIMIT
Register Information
Description
Offset
Low limit register.
0x35
Bitfield Details
Description
Field
Name
Access
Default
7:0
LOW_LIMIT
RW
0x00
IN6_HIGH_LIMIT
Register Information
High limit register.
0x36
Description
Offset
Bitfield Details
Description
Field
Name
Access
Default
7:0
HIGH_LIMIT
RW
0x00
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NCT80
IN6_LOW_LIMIT
Register Information
Description
Offset
Low limit register.
0x37
Bitfield Details
Description
Field
Name
Access
Default
7:0
LOW_LIMIT
RW
0x00
HOT_TEMP_HIGH_LIMIT
Register Information
Description
Offset
Hot temperature limit
0x38
Bitfield Details
Field
Name
HOT_TEMP_HIGH_LIMIT
Description
Access
Default
7:0
RW
0x55
HOT_TEMP_HYSTERESIS_LIMIT
Register Information
Hysteresis Temperature Limit (low)
0x39
Description
Offset
Bitfield Details
Field
Name
Description
Access
Default
7:0
HOT_TEMP_HYSTERESIS_LIMIT
RW
0x4B
OS_TEMP_HIGH_LIMIT
Register Information
Hot temperature limit
0x3A
Description
Offset
Bitfield Details
Description
Field
Name
HOT_TEMP_HIGH_LIMIT
Access
Default
7:0
RW
0x55
OS_TEMP_HYSTERESIS_LIMIT
Register Information
Hysteresis Temperature Limit (low)
0x3B
Description
Offset
Bitfield Details
Field
Name
Description
Access
Default
7:0
HOT_TEMP_HYSTERESIS_LIMIT
RW
0x4B
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23
NCT80
TACH1_COUNT_LIMIT
Register Information
Description
Offset
TACH1 speed limit.
0x3C
Bitfield Details
Description
Field
Name
TACH1_COUNT_LIMIT
Access
Default
7:0
RW
0xFF
TACH2_COUNT_LIMIT
Register Information
TACH2 speed limit.
0x3D
Description
Offset
Bitfield Details
Description
Field
Name
TACH2_COUNT_LIMIT
Access
Default
7:0
RW
0xFF
MANUFACTURERID
Register Information
Description
Offset
Manufacturer ID register. 0x1A for ON Semiconductor.
0x3E
Bitfield Details
Description
Field
Name
MANUFACTURER ID
Access
Default
7:0
RO
0x1A
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24
NCT80
Serial Bus Interface
3. When all data bytes have been read or written,
stop conditions are established. In WRITE mode,
the master will pull the data line high during the
10th clock pulse to assert a STOP condition. In
READ mode, the master device will override the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
will then take the data line low during the low
period before the tenth clock pulse, then high
during the tenth clock pulse to assert a STOP
2
Control of the NCT80 is carried out via the I C bus. The
NCT80 is connected to this bus as a slave device, under the
control of a master device. The NCT80 has a 7−bit serial bus
address. The upper 4 bits of the device address are 0101. The
lower 3 bits are set by pins 22, 23 and 24. Table 10 shows the
7−bit address for each of the pin states. The address pins are
sampled continuously, so any changes made while power is
on will result in the device address changing.
Table 10. I2C ADDRESS OPTIONS
A2
0
A1
0
A0
0
Address
0x28
condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation. In the case of the
NCT80, write operations contain either one or two bytes,
and read operations contain one byte and perform the
following functions. To write data to one of the device data
registers or read data from it, the Address Pointer Register
must be set so that the correct data register is addressed, and
then data can be written into that register or read from it. The
first byte of a write operation always contains an address that
is stored in the Address Pointer Register. If data is to be
written to the device, the write operation contains a second
data byte that is written to the register selected by the address
pointer register. This is illustrated in Figure 20. The device
address is sent over the bus followed by R/W set to 0. This
is followed by two data bytes. The first data byte is the
address of the internal data register to be written to, which
is stored in the Address Pointer Register. The second data
byte is the data to be written to the internal data register.
When reading data from a register there are two
possibilities:
0
0
1
0x29
0
1
0
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high−to−low
transition on the serial data line SDA while the
serial clock line, SCL, remains high. This indicates
that an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the START condition, and shift in the next eight
bits, consisting of a 7−bit address (MSB first) plus
an R/W bit, which determines the direction of the
data transfer, i.e., whether data will be written to
or read from the slave device. The peripheral
whose address corresponds to the transmitted
address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices
on the bus now remain idle while the selected
device waits for data to be read from or written to
it. If the R/W bit is a 0, the master will write to the
slave device. If the R/W bit is a 1, the master will
read from the slave device.
1. If the NCT80’s Address Pointer Register value is
unknown or not the desired value, it is first
necessary to set it to the correct value before data
can be read from the desired data register. This is
done by performing a write to the NCT80 as
before, but only the data byte containing the
register address is sent, as data is not to be written
to the register. This is shown in Figure 16. A read
operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data
byte read from the data register. This is shown in
Figure 18.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, as a low−to−high transition
when the clock is high may be interpreted as a
STOP signal. The number of data bytes that can be
transmitted over the serial bus in a single READ or
WRITE operation is limited only by what the
master and slave devices can handle.
2. If the Address Pointer Register is known to be
already at the desired address, data can be read
from the corresponding data register without first
writing to the Address Pointer Register, so
Figure 16 can be omitted.
To read from a register it is necessary to first write the
register address to the address pointer. The Byte Write
protocol is used for this.
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25
NCT80
1
2
3
4
5
6
SLAVE
ADDRESS
REGISTER
ADDRESS
S
A
A
P
W
Figure 15. Byte Write Protocol
1
0
9
1
9
SCL
SDA
D6
D2
1
0
1
1
1
0
D7
D5
D4
D3
D1
D0
R/W
ACK. BY
NCT80
ACK. BY
NCT80
START BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 16. Writing to the Address Pointer
1
2
3
4
5
6
SLAVE
S
R
A
DATA
P
A
ADDRESS
Figure 17. Read Byte Protocol
1
0
9
1
9
SCL
D6
D2
1
0
1
1
1
0
D7
D5
D4
D3
D1
D0
R/W
SDA
START BY
MASTER
NO ACK. BY
MASTER
ACK. BY
NCT80
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM NCT80
Figure 18. Reading a Byte from the NCT80
To write a byte to a particular register the following 3−byte sequence is used. The first byte is the 7−bit device address plus
the Write bit. The second byte is the register address to be written to and the third byte is the data to be written.
1
2
3
4
5
6
7
8
SLAVE
ADDRESS
REGISTER
ADDRESS
S
A
A
DATA
A
P
W
Figure 19. Write a Byte to a Register
1
0
9
1
9
SCL
SDA
D6
D2
1
0
1
1
1
0
D7
D5 D4 D3
D1
D0
R/W
ACK. BY
NCT80
ACK. BY
NCT80
START BY
MASTER
FRAME 2
FRAME 1
ADDRESS POINTER REGISTER BYTE
SERIAL BUS ADDRESS BYTE
1
9
SCL (CONTINUED)
D4 D3 D2 D1
D7 D6 D5
D0
SDA (CONTINUED)
ACK. BY STOP BY
NCT80 MASTER
FRAME 3
DATA BYTE
Figure 20. Writing a Byte to a Specified Address
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26
NCT80
PACKAGE DIMENSIONS
TSSOP24 7.8x4.4, 0.65P
CASE 948H
ISSUE B
NOTE 4
NOTES:
A
NOTE 6
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
D
NOTE 6
L2
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
DAMBAR PROTRUSION SHALL BE 0.08 MAX AT MMC. DAMBAR
CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
B
24
13
GAUGE
PLANE
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15
PER SIDE. DIMENSION D IS DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 PER SIDE. DIMENSION E1 IS DETERMINED
AT DATUM PLANE H.
L
NOTE 5
E1
C
E
DETAIL A
6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEAT-
ING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
PIN 1
REFERENCE
1
12
S
0.15 C B
e
2X 12 TIPS
24X b
MILLIMETERS
DIM MIN
MAX
1.20
0.15
0.30
0.20
7.90
M
S
S
A
0.10
C B
A
A1
b
---
0.05
0.19
0.09
7.70
NOTE 3
TOP VIEW
SIDE VIEW
A
c
DETAIL A
H
D
A1
0.05 C
0.10 C
E
6.40 BSC
E1
e
4.30
4.50
0.65 BSC
L
0.50
0.75
c
SEATING
L2
M
0.25 BSC
24X
C
M
END VIEW
PLANE
0
8
_
_
RECOMMENDED
SOLDERING FOOTPRINT
24X
0.42
24X
1.15
6.70
0.65
PITCH
DIMENSIONS: MILLIMETERS
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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