NCP81292MNTXG [ONSEMI]
50A, Hotswap Controller with Internal MOSFET and IMON function with paralleling capability in a thermally enhanced package.;
| 型号： | NCP81292MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | 50A, Hotswap Controller with Internal MOSFET and IMON function with paralleling capability in a thermally enhanced package. |
| 文件： | 总22页 (文件大小：1140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Hot Swap Smart Fuse
NCP81292
MARKING
DIAGRAM
1
NCP81292
AWLYYWWG
G
The NCP81292 is a 50 A, electronically re−settable, in−line fuses
for use in 12 V, high current applications such as servers, storage and
base stations. The NCP81292 offers a very low 0.65 mW integrated
MOSFET to reduce solution size and minimize power loss. It also
integrates a highly accurate current sensor for monitoring and
overload protection.
32
1
LQFN32 5x5, 0.5P
CASE 487AA
NCP81292 = Specific Device Code
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
Power Features
= Year
= Work Week
• Co−packaged Power Switch, Hotswap Controller and Current Sense
• Up to 50 A Continuous, 80 A Peak Output Current
• Vin Range: 4.5 V to 18 V
= Pb−Free Package
= (may or may not be present)
(Note: Microdot may be in either location)
• 0.65 mW, no R
Required
SENSE
Control Features
• Enable Input
• Optional Enable−controlled Output Pulldown when Disabled
• Programmable Soft−Start
• Programmable, Multi−level Current Limit
Reporting Features
• Accurate Analog Load Current Monitor
• Programmable Over Current Alert Output
• Analog Temperature Output
• Status Fault OK Output
PINOUT
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NCP81292
(TOP VIEW)
33
VIN
Other Features
For more details see Figure 1.
• 5 mm x 5 mm QFN32 Package
• Operating Temperature: −40°C to 125°C
• Can be Paralleled for Higher Current Applications
• Built−in Insertion Delay for Hotswap Applications
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• Auto−Retry Mode for Following Protection Features
♦ Current−limit after Delay
♦ Fast Short−circuit Protection
♦ Over−Temperature Shutdown
♦ Excessive Soft−start Duration
• Internal Switch Fault Diagnostics
• Low−power Auxiliary Output Voltage
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
April, 2023 − Rev. 3
NCP81292/D
NCP81292
CLREF
CS
NC4
1
2
3
4
5
6
7
8
24
23
NC5
D_OC
IMON
VDD
22
21
20
19
NCP81292
ON
GOK
NC1
VINF
NC2
(TOP VIEW)
33
VIN
GND
SS
VTEMP
GATE
18
17
Figure 1. Pin Configuration
Table 1. DEVICE ORDERING INFORMATION
†
Device
Package
Shipping
NCP81292MNTXG
QFN32
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
2
NCP81292
System VIN
VIN
VINF
VDD
GOK
D_OC
Fuse−protected
System VIN
ON
VOUT
NCP81292
VTEMP
IMON
CS
SS
GATE
CLREF
GND
Figure 2. Typical Application
Main
System
Power
Main Efuse
Input
Voltage
Main System
Main Efuse
E−Fuse
Control/
Monitor
E−Fuse
Control/
Monitor
PMBSUS Control and
Monitor
mController
E−Fuse
IMON
Standby
System
Power
Standby
System
Standby Efuse
E−Fuse
Control/
Monitor
Figure 3. Typical Application Diagram
www.onsemi.com
3
NCP81292
System VIN
VIN
VINF
VDD
NCP81292
mController
FAULT IN
GOK
OVERCURRENT IN
ENABLE OUT
D_OC
Fuse−protected
System VIN
ON
VOUT
GATE
TEMP MONITOR A/D IN
VTEMP
*
CURRENT MONITOR A/D IN
CURRENT LIMIT D/A OUT
IMON
SS
CS
CLREF
GND
VIN
VINF
VDD
NCP81292
GOK
D_OC
ON
VOUT
GATE
VTEMP
*
IMON
SS
CS
CLREF
GND
VIN
VINF
VDD
NCP81292
GOK
D_OC
ON
VOUT
GATE
VTEMP
*
IMON
SS
CS
CLREF
GND
Figure 4. Application Schematic − Parallel Fuse Operation with Controller
*For parallel NCP81292 applications, a BAS16, or equivalent, diode is recommended at each GATE pin to limit the negative voltage/current
during output fault conditions. Due to reverse leakage potential, a schottky diode should not be used.
www.onsemi.com
4
NCP81292
System VIN
VIN VINF
mController
FAULT IN
GOK
VDD
GATE
D_OC
OVERCURRENT IN
ENABLE OUT
ON NCP81292
Fuse Protected
System VIN
TEMP MONITOR A/D IN
VTEMP
VOUT
CS
SS
CLREF
IMON
CURRENT LIMIT D/A OUT
CURRENT MONITOR A/D IN
GND
Figure 5. Application Schematic − Single EFuse with Controller
System VIN
VIN VINF
GOK
VDD
GATE
D_OC
ON
NCP81292
Fuse Protected
System VIN
VOUT
VTEMP
CS
SS
CLREF
IMON
GND
Figure 6. Application Schematic − Stand−alone Single EFuse
www.onsemi.com
5
NCP81292
System VIN
VIN
VINF
VDD
NCP81292
GOK
D_OC
ON
Fuse−protected
System VIN
VOUT
GATE
VTEMP
*
IMON
SS
CS
CLREF
GND
VIN
VINF
VDD
NCP81292
GOK
D_OC
ON
VOUT
GATE
VTEMP
*
IMON
SS
CS
CLREF
GND
VIN
VINF
VDD
NCP81292
GOK
D_OC
ON
VOUT
GATE
VTEMP
*
IMON
SS
CS
CLREF
GND
Figure 7. Application Schematic − Stand−alone Parallel EFuse
*For parallel NCP81292 applications, a BAS16, or equivalent, diode is recommended at each GATE pin to limit the negative voltage/current
during output fault conditions. Due to reverse leakage potential, schottky diodes should not be used.
www.onsemi.com
6
NCP81292
VIN
9−16
VOUT > 90 % VIN
VOUT > 80 % VIN
SENSEFET
OUTPUT
MONITOR
1:5000
VOUT > 70 % VIN
VOUT > 40 % VIN
VINF
VDD
7
CHARGE
5V
PUMP
LDO
VINF+2XVDD
VOUT
25−32
21
770
EN
VDD
PD
VDD_UVR
5 mA
SS
19
ISC
AIMON
ACS
IMON
CS
22
23
VDD
VOUT>90%VIN
VOUT>70%VIN
DRAIN MON
GATE MON
5
mA
VDD
ON
4
10 mA
OVERCURRENT
TIMER
CLREF
24
3
V
SWON
D_OC
VCL_MAX
V
SWOFF
LOGIC
VCL_HI
VCL_LO
VDD
DIE TEMP
MONITOR
VOC_TH(85% CLREF)
VOUT>80%VIN
VOUT>40
%VIN
GOK
5
VTEMP
GND
18
20
50 mA
Figure 8. Block Diagram
www.onsemi.com
7
NCP81292
Table 2. PIN DESCRIPTION
Pin No.
Symbol
NC4
Description
1
2
3
No electrical connection internally. May connect to any potential
No electrical connection internally. May connect to any potential
NC5
D_OC
Overcurrent indicator output (open drain). Low indicates the NCP81292 is limiting current. The D_OC
output does not report current limiting during soft−start.
4
5
ON
Enable input and output pulldown resistance control.
OK status indicator output (open drain). Low indicates that the NCP81292 was turned off by a fault.
Test pin. Do not connect to this pin. Leave floating
Control circuit power supply input. Connect to VIN pins through an RC filter. (1 W / 0.1 mF)
Internal FET sense pin. Do not connect to this pin. Leave floating
Input of high current output switch
GOK
6
NC1
7
VINF
8
NC2
9
VIN09
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
VIN16
GATE
10
11
12
13
14
15
16
17
Input of high current output switch
Input of high current output switch
Input of high current output switch
Input of high current output switch
Input of high current output switch
Input of high current output switch
Input of high current output switch
Internal FET gate pin. Connect to the cathode of an anode grounded diode such as BAS16P2T5G. A
4.7 nF ceramic capacitor is reserved between this pin and GND for NCP81292 to mitigate the oscilla-
tion risk when small amount of output capacitance (< 100 mF) or long input/output cable (large L
OUT
/
IN
L
) happens.
18
19
20
21
22
23
VTEMP
SS
Analog temperature monitor output.
Soft Start time programming pin. Connect a capacitor to this pin to set the softstart time.
GND
VDD
IMON
CS
Ground
Linear regulator output
Analog current monitor output
Current sense feedback output (current). Scaling the voltage developed at this pin with a resistor to
ground makes this also an input for several current limiting functions and overcurrent indicator D_OC.
24
25
26
27
28
29
30
31
32
33
CLREF
VOUT25
VOUT26
VOUT27
VOUT28
VOUT29
VOUT30
VOUT31
VOUT32
VIN33
Current limit setpoint input for normal operation (after soft−start).
Output of high current output switch
Output of high current output switch
Output of high current output switch
Output of high current output switch
Output of high current output switch
Output of high current output switch
Output of high current output switch
Output of high current output switch
Input of high current output switch
www.onsemi.com
8
NCP81292
Table 3. MAXIMUM RATINGS
Rating
Symbol
Min
−0.3
−0.3
Max
20
Unit
V
VOUT Enabled
VOUT Disabled (Note 2)
Input Voltage Range
(VINx, VINF pins)
V
IN
, V
INF
30
V
Output Voltage Range
(VOUTx pins)
V
OUT
−0.3
−1 (<500 ms)
20
V
VDD Pin Voltage Range
GATE Pin Voltage Range
V
−0.3
6
V
V
DD
V
GATE
−0.3,
−0.8 (<1 ms)
30
V
−V
−20
−0.3
−40
−55
20
V
GATE
OUT
All Other Pins (Note 3)
V
+ 0.3
V
DD
Operating Junction Temperature Range
Storage Temperature Range
T
J
150
150
260
3.0
°C
°C
°C
kV
T
STG
Lead Soldering Temperature, Reflow, Pb−Free (Note 4)
T
SLD
Electrostatic Discharge, Human Body Model
(per EIA/JESD22−A114)
ESD
HBM
Electrostatic Discharge, Charged Device Model
(per EIA/JESD22−A115)
ESD
2.0
kV
CDM
Maximum Latch−Up Current Limit (per JESD78)
I
LU
100
mA
Moisture Sensitivity Level
MSL
3
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All signals referenced to GND unless noted otherwise.
2. Vout disable is the state of output OFF when internal FET has turned off by disable ON or FAULTs protection.
3. Pin ratings referenced to VDD apply with VDD at any voltage within the VDD Pin Voltage Range.
4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 4. THERMAL CHARACTERISTICS
Rating
Symbol
Value
30
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal Resistance, Junction−to−Ambient (Note 5)
Thermal Resistance, Junction−to−Top−Case
Thermal Resistance, Junction−to−Bottom−Case
Thermal Resistance, Junction−to−Board (Note 6)
Thermal Resistance, Junction−to−Case (Note 7)
R
θ
JA
R
50
θ
JCT
R
1.5
1.5
1.5
θ
JCB
R
θ
JB
R
θ
JC
2
5. R
6. R
7. R
is obtained by simulating the device mounted on a 500 mm , 1−oz Cu pad on a 80 mm x 80 mm, 1.6 mm thick 8−layer FR4 board.
q
q
q
JA
JB
JC
value based on hottest board temperature within 1 mm of the package.
≈ R
// R
(Two−Resistor Compact Thermal Model, JESD15−3).
q
q
JCT
JCB
Table 5. RECOMMENDED OPERATING RANGES
Parameter (Note 1)
Symbol
Min
Max
18
Unit
V
VIN, VINF Pin Voltage Range
Maximum Continuous Output Current
Peak Output Current
4.5
I
50
A
AVE
I
80
A
PEAK
VDD Output Load Capacitance Range
VTEMP Output Load Capacitance Range
Softstart Duration
C
2.2
0.1
10
10
mF
mF
ms
kW
V
VDD
C
VTEMP
T
100
4
SS
CS Load Resistance Range
R
1.8
0.2
−40
CS
CLREF Voltage Range
V
1.55
125
CLREF
Operating Junction Temperature
T
J(OP)
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
9
NCP81292
Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, V = 3.3 V, C
= 0.1 mF, C
= 4.7 mF, C = 0.1 mF,
VTEMP
ON
VINF
VDD
R
= 1 kW, C = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ T ≤ 125°C unless
VTEMP
S
S
J
noted otherwise, and are guaranteed by design and characterization through statistical correlation.
Parameter Symbol Test Conditions
VINF INPUT
Min
Typ
Max
Units
Quiescent Current
V
ON
V
ON
V
ON
V
ON
> 1.4 V, no load
> 1.4 V, fault
3.23
2.38
5.0
5.0
4.0
4.0
mA
mA
mA
mA
< 0.8 V
< 0.8 V, VINF = 16 V
VDD REGULATOR
VDD Output Voltage
VDD Load Capability
VDD Current Limit
VDD Dropout Voltage
UVLO threshold − rising
UVLO threshold − falling
ON INPUT
V
I
= 0 mA, VINF = 6 V
4.7
50
5.09
5.3
30
V
DD_NL
VDD
I
VINF = 5.5 V
mA
mA
mV
V
DDLOAD
I
VINF = 12 V and VINF = 6 V
70
85
DD_CL
I
= 25 mA, VINF = 4.5 V
200
4.5
4.2
VDD
V
4.1
3.8
4.3
4.0
DD_UVR
V
V
DD_UVF
Bias Current
I
From pin into a 0 V or 1.5 V source
4.0
5.0
1.4
1.2
6.0
mA
V
ON
Switch ON Threshold
V
1.33
1.13
1.47
1.27
SWON
Switch OFF/ Pulldown Up-
per Threshold
V
V
SWOFF
Pulldown Lower Threshold
Switch ON Delay Timer
V
0.8
1.0
V
PDOFF
t
From ON transitioning above V
start
to SS
0.6
2.8
2.5
ms
ON
SWON
Switch OFF Delay Time
(Note 8)
t
From ON transitioning below V
pulldown
to GATE
1.7
3.0
ms
V
OFF
SWOFF
ON Current Source Clamp
Voltage
V
t
Max pullup voltage of current source
ON_CLMP
PD_DEL
Load Pulldown Delay Timer
From ON transitioning into the range between
2.0
ms
kW
V
V
and V
PDOFF
SWOFF
Output Pulldown Resis-
tance
R
= 12 V, PD mode = 1
OUT
0.77
PD
SS PIN
Bias Current
I
From pin into a 0 V or 1 V source
0.1 mA into pin during ON delay
4.62
9.6
5.15
10
5.62
10.4
mA
V/V
mV
SS
Gain to VOUT
AV
SS
SS Pulldown Voltage
GOK OUTPUT
V
22
OL_SS
Output Low Voltage
Off−state Leakage Current
V
I
= 1 mA
0.1
1.0
V
OL_GOK
GOK
I
V
= 5 V
mA
LK_GOK
GOK
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design or characterization data. Not tested in production.
www.onsemi.com
10
NCP81292
Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, V = 3.3 V, C
= 0.1 mF, C
= 4.7 mF, C = 0.1 mF,
VTEMP
ON
VINF
VDD
R
= 1 kW, C = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ T ≤ 125°C unless
VTEMP
S
S
J
noted otherwise, and are guaranteed by design and characterization through statistical correlation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
IMON/CS OUTPUT
IMON or CS Current
(single EFuse)
I
/I
T = 0 to 125°C
IOUT = 5 A (Note 8)
IOUT = 10 A (Note 8)
IOUT = 25 A (Note 8)
IOUT = 50 A (Note 8)
IOUT = 8 A
50
mA
mA
mA
mA
%
IMON CS
J
100
250
500
Based on 10 mA/A
Accuracy (single EFuse)
T = 25°C
A
−3
−3
−5
2.8
3
3
5
IOUT > 8 A (Note 8)
IOUT ≥ 8 A (Note 8)
%
T = 0 to 85°C
A
%
IMON or CS Current Source
Clamp Voltage
V
V
/
Max pullup voltage of current source
3.0
V
IM_CLMP
CS_CLMP
CURRENT LIMIT & CLREF PIN
Current Limit Voltage
V
If V > VCL_TH current limiting regulation
95
98
101
12
%V
CLREF
CL_TH
CS
occurs via gate
Current Limit Enact Offset
Voltage
V
0.2 V < V
< 1.55 V
−70
−24
mV
ENACT
CLREF
Current Limit Clamp Voltage
V
VOUT < 40% VIN, V
> 0.165 V
143
480
152
504
162
520
mV
mV
CL_LO
CLREF
V
CL_HI
40% VIN < VOUT < 80% VIN
> 0.55 V
V
CLREF
Max Current Limit
Reference Voltage
V
VOUT > 80% VIN, V
> 1.65 V
1.55
1.6
1.65
10.4
V
CL_MX
CLREF
Response Time (Note 8)
CLREF Bias Current
t
V
CS
> V current limiting time
CLREF
200
10
ms
mA
V
CL_REG
I
CL
From pin into a 1.2 V source
9.6
2.8
CLREF Current Source
Clamp Voltage
V
Max pullup voltage of current source
3.0
CL_CLMP
FET Turn−off Timer
t
Delay between current limit detection and FET
250
85
ms
CL_LA
turn−off (GOK = 0)
D_OC OUTPUT
Overcurrent Threshold
Output Low Voltage
VOC_TH
If V > VOC_TH, the D_OC pin pulls low
82
89
0.1
1.0
%V
CLREF
CS
V
I
= 1 mA
V
OL_DOC
LK_DOC
DOC
Off−state Leakage Current
De−bounce Time (Note 8)
I
V
V
= 5 V
mA
ms
DOC
< limit until D_OC rising
3.0
CS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design or characterization data. Not tested in production.
www.onsemi.com
11
NCP81292
Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, V = 3.3 V, C
= 0.1 mF, C
= 4.7 mF, C = 0.1 mF,
VTEMP
ON
VINF
VDD
R
= 1 kW, C = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ T ≤ 125°C unless
VTEMP
S
S
J
noted otherwise, and are guaranteed by design and characterization through statistical correlation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
SHORT CIRCUIT PROTECTION
Current Threshold (Note 8)
Response Time (Note 8)
VTEMP OUTPUT
I
t
100
500
A
SC
From I
> I
LIMSC
until gate pulldown
ns
SC
OUT
Bias Voltage
V
At 25°C
450
10
1
mV
mV/°C
kW
VTEMP25
°
°
Gain (Note 8)
A TEMP
0 C ≤ T ≤ 125 C
V
J
Load Capability (Note 8)
Pulldown Current
THERMAL SHUTDOWN
R TEMP
At 25°C
At 25°C
V
I TEMP
50
mA
V
Temperature Shutdown
(Note 8)
T
TSD
GOK pulls down
140
°C
OUTPUT SWITCH (FET)
On Resistance
R
T = 25°C, I = 8 A
OUT
0.65
1.0
1.0
mW
mA
DSon
J
Off−state leakage current
FAULT detection
I
VIN = 16 V, V < 1.2 V, T = 25°C
ON J
DSoff
V
V
V
V
V
V
Short Threshold
VDS_TH
VDS_OK
VDG_TH
VDG_OK
VG_TH
Startup postponed if VOUT > VDS_TH at V
88.8
68.6
3.1
%VIN
DS
DS
GD
GD
ON
> V
transition
SWON
Short OK Threshold
Short Threshold
Startup resumed if VOUT < VDS_OK anytime
after postponed
%VIN
Startup postponed if V > VDG_TH at V
SWON
>
V
V
V
G
ON
V
transition
Short OK Threshold
Startup resumed if V < VDG_OK anytime af-
3.0
G
ter postponed
Low Threshold
Restart if V < VG_TH after t or
SSF_END
5.4
G
GD
t
GATE_FLT
Low Threshold
V
Restart if V
< VOUTL_TH after t
SSF_END
90
%VIN
ms
OUT
OUTL_TH
OUT
Gate Fault Timer (Note 8)
t
Time from V < V
SSF_END
transition after
200
GATE_FLT
GD
G_TH
t
completed
Startup Timer Failsafe
(Note 8)
t
Time from V > V
Max programmable softstart time
transition,
200
ms
SSF_END
ON
SWON
AUTO−RETRY
Auto−Retry Delay
t
Delay from power−down to retry of startup
1000
ms
DLY_RETRY
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design or characterization data. Not tested in production.
www.onsemi.com
12
NCP81292
TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R
= 121 kW, R = 2 kW, T = 25°C, unless otherwise specified.
IMON A
CLREF
600
600
500
400
300
200
500
400
300
200
100
100
0
0
0
0
10
20
30
40
50
60
10
20
30
40
50
60
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 9. Ics vs. Load Current
Figure 10. Imon vs. Load Current
5
4
3
2
1
0
1.0
0.9
0.8
0.7
+85°C
+25°C
0°C
0.6
0.5
0.4
0.3
0.2
0.1
0
−60 −40 −20
0
20 40
60 80 100 120 140
0
10
20
30
40
50
Load Current (A)
TEMPERATURE (°C)
Figure 11. IIMON/ ICS Accuracy vs. Load Current
Figure 12. Output Switch RDS(on) @ 22 A vs.
Temperature
1600
1400
1200
1000
800
600
400
200
0
−60 −40 −20
0
20 40 60
80 100 120 140
TEMPERATURE (°C)
Figure 13. Vtemp vs. Temperature (no load)
www.onsemi.com
13
NCP81292
TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R
= 121 kW, R
= 2 kW, T = 25°C, unless otherwise specified.
CLREF
IMON
A
0
2500
−1
2000
1500
1000
500
−2
−3
−4
Power Loss
−5
−6
0
0
−60 −40 −20
0
20 40 60 80 100 120 140
10
20
30
40
50
60
TEMPERATURE (°C)
OUTPUT CURRENT (A)
Figure 14. Output Switch Off−state Leakage
Figure 15. Power Loss vs. Load Current
vs. Temperature
1000
100
10
100 ms
250 ms
1 ms
10 ms
100 ms
1 s
1
R
Limit
DS(ON)
10 s
Single Pulse
= 24.8 °C/W
T = 25°C
A
0.1
Dotted Lines: Measured SOA
Solid Lines: Calculated SOA
R
q
JA
0.01
0.1
1
10
20
V
DS
, DRAIN−SOURCE VOLTAGE (V)
Figure 16. Internal FET’s Safe Operating Area (SOA)
100k
250
200
150
10k
1k
T = 25°C
A
100
50
0
100
10
1
T = 25°C
A
T = 85°C
A
T = 85°C
A
0.00001 0.0001 0.001 0.01
0.1
1.0
10
100
1k
0.01
0.2 0.3
0.4 0.5
0.6 0.7
0.8 0.9
0.1
PULSE WIDTH (s)
PULSE WIDTH (s)
Figure 17. Single Pulse Power Rating (10 ms −
1000 s, Junction−to−Ambient, Note 4)
Figure 18. Single Pulse Power Rating (10 ms −
100 ms, Junction−to−Ambient, Note 4)
www.onsemi.com
14
NCP81292
TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R
= 121 kW, R = 2 kW, T = 25°C, unless otherwise specified.
IMON A
CLREF
Figure 19. Start Up by VIN (Iout = 0 A)
Figure 20. Shut Down by VIN (Iout = 0 A)
Figure 21. Start Up by VIN (Iout = 15 A)
Figure 22. Shut Down by VIN (Iout = 15 A)
Figure 23. Start Up by EN (Iout = 0 A)
Figure 24. Shut Down by EN (Iout = 0 A)
www.onsemi.com
15
NCP81292
TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R
= 121 kW, R = 2 kW, T = 25°C, unless otherwise specified.
IMON A
CLREF
Figure 25. Start Up by EN (Iout = 15 A)
Figure 26. Shut Down by EN (Iout = 15 A)
Figure 27. Short Circuit during Normal
Operation (Iout = 0 A)
Figure 28. Short Circuit during Normal
Operation (Iout = 50 A)
Figure 29. Short FET’s Gate During Normal
Operation (Iout = 2.5 A)
Figure 30. DOC Index for Current Limit during
Normal Operation (Iout = 51.8 A)
www.onsemi.com
16
NCP81292
TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, R
= 121 kW, R = 2 kW, T = 25°C, unless otherwise specified.
IMON A
CLREF
Figure 31. OCP during Normal
Operation(Iout=60.2A)
Figure 32. OCP during Power Up by Enable
www.onsemi.com
17
NCP81292
General Information
The typical C values for different t are listed below:
SS
SS
The NCP81292 is an N−channel MOSFET co−packaged
with a smart hotswap controller. It is suited for high−side
current limiting and fusing in hot−swap applications. It can
be used either alone, or in a paralell configuration for higher
current applications.
t
(ms)
C
(nF)
t
(ms)
C
(nF)
SS
SS
SS
SS
10
47
60
270
20
30
40
50
82
70
80
330
330
470
470
120
180
220
VDD Output (Auxiliary Regulated Supply)
An internal linear regulator draws current from the VINF
pin to produce and regulate voltage at the VDD pin. This
90
100
auxiliary output supply is current−limited to I
. A
DD_CL
The maximum load capacitor value NCP81292 can power
up depends on the device soft−start time. When V = 12 V,
ceramic capacitor in the range of 2.2 mF to 10 mF must be
placed between the VDD and GND pins, as close to the
NCP81292 as possible. The voltage difference between VIN
and VINF pin voltage should be within 0.4 V for better
CS/IMON performance. Small time constant R/C filter such
as 1 W/0.1 mF on the VINF pin is recommended.
IN
R
CS
= 2 kW, R
= 2.4 W, their relationship for different
LOAD
paralleled operations are shown as below chart (above line
device shuts down safely due to protection, below line
device powers up successfully without trigger protection):
Maximum CLOAD vs SoftStart Time (CS = 2kW, RLOAD = 2.4W, VIN = 12V)
ON Input (Device Enable)
When the ON pin voltage (V ) is higher than V
,
ON
SWON
and no undervoltage (UVLO) or output switch faults are
present, the output switch turns on. When V is lower than
ON
V
SWOFF
, the output switch is off. If V is between V
ON PDOFF
and V
for longer than t , the output switches
PD_DEL
SWOFF
off, and a pulldown resistance to ground, of R , is applied
PD
to VOUT. In other words, there is behavior as follows:
• When V < 0.8 V, FET turns off.
ON
• When 0.8 V < V < 1.2 V, VOUT will discharge with
ON
ꢀ 15 mA.
• When V > 1.2 V, FET turns on.
ON
For standalone applications, the ON pin sources current
I
, which can be used to delay output switch turn−on for
ON
GOK Output (Gate OK)
The GOK pin is an open−drain output that is pulled low to
report the fault under the following conditions:
some time after the appearance of input voltage by
connecting a capacitor from the ON pin to ground.
A bi−level control signal driving to ground can be biased
up with a resistive divider to produce ON input levels
• V voltage is below UVLO voltage at any time.
DD
between V
< V < V
and V > V
in
• V disabled and V
is false
PDOFF
ON
SWON
ON
SWON
ON
DS_OK
order to always apply the output pulldown when the output
switch is off.
(indicates a short from VIN to VOUT).
• V disabled and V is false
ON
DG_OK
(indicates a short from GATE to VIN).
• V enabled and V is false at t
SS Output (Soft−Start)
When the output switch first turns on, it does so in a
controlled manner. The output voltage (VOUT) follows the
ON
SS_OK
SSF_END
(indicates VOUT < 90% after soft−start completes).
• V enabled and V is below V at t
voltage at the SS pin, produced by current I into a capacitor
SS
ON
G
G_TH
SSF_END
from SS to ground. The duration of soft−start can be
programmed by selection of the capacitor value. In parallel
fuse applications, the SS pins of all fuses should be shorted
together to one shared SS capacitor. Internal soft−start load
balancing circuity will ensure the soft−start current is shared
between paralleled devices, so as not to stress one device
more than another or hit a soft start−current limit.
(indicates leakage on GATE in startup).
after t
GATE_FLT
• V enabled and V is below V
ON
G
G_TH
(indicates leakage on GATE during normal operation).
• V enabled and a current−limiting condition lasts
ON
longer than t
OC_LA
• V enabled and device temperature is above T
ON
TSD
(indicates an over−temperature is detected).
The soft−start capacitor value can be calculated by:
Usually GOK can’t be used as power good to indicate the
output voltage is in the normal range.
C
SS
= (t * I * AV )/VIN (where t is the target
SS SS SS SS
soft−start time). The recommended range of t is 10 −
SS
100 ms.
www.onsemi.com
18
NCP81292
IMON Output (Current Monitor)
The IMON pin sources a current that is A
times the VOUT output current. A resistor connected from
the IMON pin to ground can be used to monitor current
During startup (V > V
current limit reference voltage is clamped according to the
following:
for less than t
), the
ON
SWON
SS_END
(10 mA/A)
IMON
• When VOUT < 40% of VIN, V
= V
or
CL_TH
CL_LO
information as a voltage up to V
. A capacitor of any
IM_CLMP
V
CLREF
(whichever is lower).
value in parallel with the IMON resistor can be used to
low−pass filter the IMON signal without affecting any
internal operation of the device.
• When VOUT is between 40% and 80% of VIN,
= V or V (whichever is lower).
V
CL_TH
CL_HI
CLREF
• When VOUT exceeds 80% of VIN, V
= V
CL_MX
CL_TH
or V
(whichever is lower).
CLREF Pin (Current Limit and Over−Current Reference)
The CLREF pin voltage determines the current−limit
regulation point and over−current indication point via its
interaction with the CS pin voltage. The CLREF voltage can
be applied by an external source, such as a hot−swap
controller or D−to−A converter, or developed across a
programming resistor to ground by the CLREF bias current,
CLREF
During soft−start, current is actively limited to V
CL_TH
for up to t
before the device shuts off and
CL_REG
automatically restarts. Once t
exceeding the limit established by V
results in device shutdown and automatic restart.
The CS pin must have no capacitive loading other than
parasitic device/board capacitance to function correctly. The
elapses, current
SS_END
for > t
CLREF
CL_LA
I
. The recommended range of CLREF voltage is 0.2 −
CL
1.55 V.
recommended range of R is 1.8 − 4 kW.
CS
CS Input/Output (Current Set)
The CS pin is both an input and an output. The CS pin
CS AMP
NCP81292 uses an auto−zero Op−Amp to sense current in
FET with high−accuracy. The internal IMON and CS
current source follow below relationship:
sources a current that is A (10 mA/A) times the VOUT
CS
current. This produces a voltage on the CS pin that is the
product of the CS pin current and an external CS pin
resistance to ground.
ICS
IOUT
+
(eq. 3)
10 m
The voltage generated on V determines the D_OC
CS
over−current indicator trip point and the current−limit
regulation point, via its interaction with the voltage on
CLREF pin.
and
IMON
+
(eq. 4)
IOUT
10 m
When the voltage on the CS pin is higher than V
,
OC_TH
D_OC is pulled low. If the CS pin voltage drops below
, the D_OC pin is released to and gets pulled high by
the external pullup resistor. D_OC transitions based on the
following formula:
D_OC Output (Over−current Indicator)
V
OC_TH
The D_OC pin is an open−drain output that indicates
when an over−current condition exists after soft−start is
complete. When the voltage on the CS pin is higher than
V
)V
OC_TH
ENACT
V
V
, D_OC is pulled low. If output current drops below
, the D_OC pin is released and gets pulled high by
OC_TH
R
CS
OC_TH
(eq. 1)
IOUT
+
10 m
an external pullup resistor.
The V
(86%).
trip point is based on a percentage of V
CLREF
OC_TH
VTEMP Output (Temperature Indicator)
VTEMP is a voltage output proportional to device
temperature, with an offset voltage. The VTEMP output can
source much more current than it can sink, so that if multiple
VTEMP outputs are connected together, the voltage of all
VTEMP outputs will be driven to the voltage produced by
the hottest NCP81292. A 100 nF capacitor or greater must
be connected from the VTEMP pin to ground.
During normal operation (V > V
for longer than
CL_TH
> V ), then
CL_MX
SWON
ON
t
), if the voltage on the CS pin is above V
SS_END
(V
is clamped at V
if V
CL_TH
CL_MX
CL_TH
the gate voltage of the FET is modulated to limit current into
the output based on the following formula:
V
)V
CL_TH
ENACT
R
CS
(eq. 2)
IOUT
+
10 m
The V
regulation point is equal to V
.
CL_TH
CLREF
www.onsemi.com
19
NCP81292
Auto−Retry Restart
FET Fault Detection
Under certain fault conditions, the FET is turned off and
The device contains various FET monitoring circuits:
another soft−start procedure takes place. Between the fault
• VIN to VOUT short: If the device is disabled and
and the new soft−start, there is a delay of t . The
DLY_RETRY
VOUT > V
then GOK is pulled low and the
DS_TH
protection features that use this hiccup mode restart are:
device is prevented from powering up. The device is
allowed to power up once VOUT < V
• Over−Current
• Short−Circuit Detection
• Over−Temperature
• Excessive Soft−Start Duration
• Gate Leakage
.
DS_OK
• GATE to VIN short: If the device is disabled and
GATE (Pin 8) > V , then GOK is pulled low and
DG_TH
device is prevented from powering up. The device
allowed to power up once GATE < V
DG_OK.
• GATE leakage − startup.
If (GATE – VINF) < V
at t
, then GOK is
Protection Features
G_TH
SSF_END
pulled low and FET restarts.
• GATE leakage − normal operation.
If (GATE – VINF) < V for t
For the following protection features, the FET turns off
and initiates a restart, unless noted otherwise.
time after
GATE_FLT
G_TH
Excessive Current Limiting
If a current limiting condition exists anytime for a
the soft−start timer completes, then GOK is pulled low
and device restarts.
continuous duration > t
, then the FET restarts.
CL_LA
FET SOA Limits
Excessive Soft−Start Duration
In−built timed current limits and fault−monitoring circuits
ensure the co−packaged FET is always kept within SOA
limits.
The NCP81292 is rated for 50 A continuous current. For
repetitive pulsed loads up to 80 A with a period less than
200 ms, 50 A RMS is supported.
During soft−start, current is actively limited to V
CL_TH
for up to t
before the device shuts off and
CL_REG
automatically restarts. Once t
elapses, current
SS_END
exceeding the limit established by V
for > t
CLREF
CL_LA
results in device shutdown and automatic restart.
Short Circuit Detection
If switch current exceeds I , the device reacts within t
and the FET restarts. The short−circuit current monitor is
independent of CS, CLREF, IMON and current limit setting
(cannot be changed externally).
Multiple Fuse Power Up
When multiple NPC81292 are paralleled together as
shown in Figure 4, they will turn on together.
For stand−alone parallel applications, the ON and GOK
pins should be connected as shown in Figure 7 to
synchronize hiccup timing and prevent cascading faults.
When using system mController for parallel applications
(Figure 4), the mController should be provisioned such that
ON is not asserted until GOK is released to high state.
,
SC
SC
Over−Temperature Shutdown
If the FET controller temperature > T
restarts.
, then the FET
TSD
www.onsemi.com
20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LQFN32 5x5, 0.5P
CASE 487AA
ISSUE A
DATE 03 OCT 2017
32
SCALE 2:1
1
A
B
D
NOTES:
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
DETAIL A
ALTERNATE
E
CONSTRUCTION
MILLIMETERS
DIM MIN
MAX
1.40
0.05
0.10
C
A
A1
A3
b
1.20
−−−
0.20 REF
0.18
A3
0.10
C
0.30
3.50
3.50
0.50
TOP VIEW
D
5.00 BSC
D2 3.30
A1
E
5.00 BSC
DETAIL B
(A3)
E2 3.30
DETAIL B
0.10
0.05
C
C
e
L
0.50 BSC
0.30
ALTERNATE
CONSTRUCTION
A
L2
0.13 REF
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
A1
NOTE 4
L2
C
SIDE VIEW
1
D2
DETAIL A
L2
K
9
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
DETAIL C
17
24
4 PLACES
32X
L
E2
DETAIL C
XXXXX = Specific Device Code
1
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
32
25
WL
YY
WW
G
32X b
e
e/2
M
M
0.10
C A B
NOTE 3
0.05
C
BOTTOM VIEW
(Note: Microdot may be in either location)
RECOMMENDED
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some prod-
ucts may not follow the Generic Marking.
SOLDERING FOOTPRINT*
5.30
32X
0.63
3.60
3.60
5.30
0.50
PITCH
32X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11454G
LQFN32, 5x5, 0.5P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
©2020 ICPDF网 联系我们和版权申明