NCP81142MNTXG [ONSEMI]
VR 多相控制器;
ONSEMI 
NCP81142
Multiple-Phase Controller
with SVID Interface for
Desktop and Notebook CPU
Applications
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MARKING
The NCP81142 Multi−Phase buck solution is optimized for
Intel® VR12.5 compatible CPUs with user configurations of 4/3/2/1
phases. The controller combines true differential voltage sensing,
differential inductor DCR current sensing, input voltage
feed−forward, and adaptive voltage positioning to provide accurately
regulated power for both Desktop and Notebook applications. The
control system is based on Dual−Edge pulse−width modulation
(PWM) combined with DCR current sensing providing the fastest
initial response to dynamic load events at reduced system cost. It has
the capability to shed to single phase during light load operation and
can auto frequency scale in light load conditions while maintaining
excellent transient performance.
High performance operational error amplifiers are provided to
simplify compensation of the system. Patented Dynamic Reference
Injection further simplifies loop compensation by eliminating the need
to compromise between closed−loop transient response and Dynamic
VID performance. Patented Total Current Summing provides highly
accurate digital current monitoring.
DIAGRAM
NCP
81142
ALYWG
G
1
QFN32
CASE 485CD
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
Features
• Meets Intel VR12.5 Specifications
• Current Mode Dual Edge Modulation for Fastest Initial Response to
Transient Loading
• High Performance Operational Error Amplifier
• Digital Soft Start Ramp
• Dynamic Reference Injection
• Accurate Total Summing Current Amplifier
• Dual High Impedance Differential Voltage and Total
Current Sense Amplifiers
• Power Saving Phase Shedding
• Vin Feed Forward Ramp Slope
• Phase−to−Phase Dynamic Current Balancing
• “Lossless” DCR Current Sensing for Current Balancing
• True Differential Current Balancing Sense Amplifiers
for Each Phase
• Over Voltage Protection (OVP) & Under Voltage
Protection (UVP)
• Over Current Protection (OCP)
• VR−RDY Output with Internal Delays
• These are Pb−Free Devices
• Adaptive Voltage Positioning (AVP)
• Switching Frequency Range of 290 kHz – 590 kHz
Applications
• Startup into Pre−Charged Loads While Avoiding False
• Desktop and Notebook Processors
OVP
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
NCP81142/D
August, 2018 − Rev. 3
NCP81142
CS
Amp
Current
Measurement
& Limit
VSN
VSP
+
−
DAC
GND
Error
Amp
DIFFAMP
CSREF
VSP
VSN
OVP
TSENSE
VRHOT
Thermal
Monitor
OVP
VSP−VSN
TSENSE
VBOOT
IOUT
SDIO
SVID Interface
Data
Registers
MUX
ALERT
ADC
SCLK
IMAX
ADDR
CSN4
DAC
DAC
CSP4
CSN2
CSP2
CSN3
CSP3
Enable
IPH4
VR Ready
Comparator
VSP
VSN
VRDY
IPH3
IPH2
IPH1
Current
Balance
DAC
CSN1
CSP1
RAMP1
RAMP2
RAMP3
RAMP4
OVP
PWM
Generators
COMP
Enable
Enable
GND
Ramp
Generators
Enable
UVLO & EN
VCC
ENABLE
Power State
Stage
NCP81142
Figure 1. Block Diagram for NCP81142
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2
NCP81142
32
31
30
29
28
27
26
25
ENABLE
VCC
1
2
24 CSCOMP
CSSUM
CSREF
CSN4
CSP4
23
22
21
20
19
18
17
VR_HOT#
SDIO
3
4
5
6
7
8
NCP81142
ALERT#
SCLK
CSN2
CSP2
VR_RDY
TSENSE
CSN3
9
10
11
12
13
14
15
16
Figure 2. NCP81142 Pin Configurations
NCP81142 PIN DESCRIPTIONS
Pin No.
Symbol
ENABLE
VCC
Description
1
2
Logic input. Logic high enables the output and logic low disables the output.
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground
Thermal logic output for over temperature
3
VR_HOT#
SDIO
4
Serial VID data interface
5
ALERT#
Serial VID ALERT#.
6
SCLK
Serial VID clock
7
VR_RDY
TSENSE
PWM4/ROSC
PWM2/VBOOT
Open drain output. High indicates that the output is regulating
Temp Sense input for the multiphase converter
8
9
Phase 4 PWM output. A resistance from this pin to ground programs the oscillator frequency
10
Phase 2 PWM output. Also as VBOOT input pin to adjust the boot−up voltage. During start up it is
used to program VBOOT with a resistor to ground
11
12
PWM3/IMAX
Phase 3 PWM output. Also as ICC_MAX Input Pin. During start up it is used to program ICC_MAX
with a resistor to ground
PWM1/INT_SEL
Phase 1 PWM output. Also as Int_sel program pin. A resistor to ground on this pin programs the
INT_Select value
13
14
15
16
DRON
CSP1
CSN1
CSP3
Bidirectional gate drive enable output
Non−inverting input to current balance sense amplifier for phase 1
Inverting input to current balance sense amplifier for phase 1
Non−inverting input to current balance sense amplifier for phase 3
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NCP81142
NCP81142 PIN DESCRIPTIONS
Pin No.
Symbol
Description
17
CSN3
Inverting input to current balance sense amplifier for phase 3. Pull this Pin to VCC, configure as
1−phase operation
18
19
CSP2
CSN2
Non−inverting input to current balance sense amplifier for phase 2
Inverting input to current balance sense amplifier for phase 2. Pull this Pin to VCC, configure as
2−phase operation
20
21
CSP4
CSN4
Non−inverting input to current balance sense amplifier for phase 4
Inverting input to current balance sense amplifier. Pull this Pin to VCC, configure as 3−phase op-
eration
22
CSREF
Total output current sense amplifier reference voltage input, a capacitor on this pin is used to en-
sure CSREF voltage signal integrity
23
24
25
26
27
CSSUM
CSCOMP
ILIM
Inverting input of total current sense amplifier
Output of total current sense amplifier
Over current shutdown threshold setting. Resistor to CSCOMP to set threshold
Total output current monitor.
IOUT
VRMP
Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used
to control the ramp of PWM slope
28
29
30
31
32
33
COMP
FB
Output of the error amplifier and the inverting inputs of the PWM comparators
Error amplifier voltage feedback
DIFFOUT
VSN
Output of the differential remote sense amplifier
Inverting input to differential remote sense amplifier
Non−inverting input to the differential remote sense amplifier
Power supply return (QFN Flag)
VSP
FLAG / GND
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NCP81142
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
V
MAX
V
MIN
COMP
VCC + 0.3 V
VCC + 0.3 V
GND + 300 mV
VCC + 0.3 V
VCC + 0.3 V
6.5 V
−0.3 V
−0.3 V
CSCOMP
VSN
GND – 300 mV
−0.3 V
DIFFOUT
VR_RDY
−0.3 V
VCC
−0.3 V
IOUT
2.0 V
−0.3 V
VRMP
+25 V
−0.3 V
All Other Pins
VCC + 0.3 V
−0.3 V
*All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Description
Symbol
Typ
Unit
Thermal Characteristic
QFN Package (Note 1)
R
68
_C/W
q
JA
Operating Junction Temperature Range (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Max Power Dissipation
T
−40 to +125
−40 to +100
−40 to +150
110 to 131
1
_C
_C
J
T
_C
STG
Pd
mW
Moisture Sensitivity Level
QFN Package
MSL
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
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NCP81142
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; V = 5 V; C = 0.1 mF
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Input Bias Current
Open Loop DC Gain
@ 1.3 V
−27
27
mA
CL = 20 pF to GND,
RL = 10 kW to GND
80
20
20
dB
Open Loop Unity Gain Bandwidth
Slew Rate
CL = 20 pF to GND,
RL = 10 kW to GND
MHz
DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND,
V/ms
DC Load = 10k to GND
Maximum Output Voltage
Minimum Output Voltage
I
= 2.0 mA
3.5
V
V
SOURCE
I
= 2.0 mA
1
SINK
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
VSP, VSN = 1.3 V
−15
−0.3
−0.3
15
3.0
0.3
uA
V
VSP Input Voltage Range
VSN Input Voltage Range
V
CL = 20 pF to GND,
RL = 10 kW to GND
−3dB Bandwidth
10
MHz
V/V
VS+ to VS− = 0.5 to 1.3 V
Closed Loop DC gain
1.0
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos)
−300
−10
300
10
mV
mA
dB
Input Bias Current
CSSUM = CSREF= 1 V
Open Loop Gain
80
10
C = 20 pF to GND,
L
Current Sense Unity Gain Bandwidth
MHz
R = 10 kW to GND
L
CURRENT BALANCE AMPLIFIER
Maximum CSCOMP Output Voltage
Minimum CSCOMP Output Voltage
Input Bias Current
I
= 2 mA
3.5
V
V
source
I
= 500 mA
0.1
50
sink
CSP
= CSN
= 1.2
nA
1−4
1−4
−50
Common Mode Input Voltage Range
Differential Mode Input Voltage Range
Input Offset Voltage Matching
CSPx = CSNx
CSNx = 1.2 V
0
2.3
100
1.5
V
−100
−1.5
mV
mV
CSPx = CSNx = 1.2 V,
Measured from the average
Current Sense Amplifier Gain
Multiphase Current Sense Gain Matching
−3dB Bandwidth
0 V < CSPx − CSNx < 0.1 V,
CSP−CSN = 10 mV to 30 mV
5.7
−3
6.0
8
6.3
3
V/V
%
MHz
INPUT SUPPLY
Supply Voltage Range
4.75
5.25
V
VCC Quiescent Current
EN = high, PS0,1,2 Mode
EN = high, PS3 Mode
EN = low
25
15
30
mA
mA
mA
3. Guaranteed by design or characterization data, not in production test.
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NCP81142
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; V = 5 V; C = 0.1 mF
A
CC
VCC
Parameter
Test Conditions
Min
4
Typ
Max
Unit
INPUT SUPPLY
UVLO Threshold
VCC rising
VCC falling
4.5
V
V
VCC UVLO Hysteresis
UVLO Threshold
160
mV
V
VRMP rising
VRMP failing
4.2
3
V
DAC SLEW RATE
Soft Start Slew Rate
Slew Rate Slow
Slew Rate Fast
5
5
mv/ms
mv/ms
mv/ms
20
ENABLE INPUT
Enable High Input Leakage Current
Upper Threshold
External 1k pull−up to 3.3 V
1.0
0.3
5
mA
V
V
0.8
UPPER
LOWER
Lower Threshold
V
V
Total Hysteresis
V
– V
90
mV
ms
UPPER
LOWER
Enable Delay Time
Measure time from Enable
transitioning HI to when DRON goes
high
DRON
Output High Voltage
Output Low Voltage
Sourcing 500 mA
Sinking 500 mA
3.0
V
V
0.1
CL (PCB) = 20 pF,
DVo = 10% to 90%
Rise Time
156
ns
Fall Time
55
70
ns
Internal Pull Down Resistance
IOUT OUTPUT
EN = Low
kW
Input Referred Offset Voltage
Output Source Current
Current Gain
Ilimit to CSREF
−3.5
9.5
3.5
850
10.5
mV
Ilimit sink current = 80 mA
mA
(IOUT
) / (ILIMIT
),
10
CURRENT
= 20k, R
CURRENT
R
= 5.0k , DAC =
ILIM
IOUT
0.8 V, 1.25 V, 1.52 V
OSCILLATOR
Switching Frequency Range
4 Phase Operation
290
590
600
KHz
kHz
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Over Voltage Threshold During Soft Start
Over Voltage Threshold Above DAC
Over Voltage Delay
CSREF
2.75
350
2.9
400
50
3
V
VSP rising
425
mV
ns
VSP rising to PWMx low
Ckt in development
Ckt in development
Under Voltage
300
5
mV
ms
Under−voltage Delay
3. Guaranteed by design or characterization data, not in production test.
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NCP81142
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; V = 5 V; C = 0.1 mF
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
OVERCURRENT PROTECTION
ILIM Threshold Current (OCP shutdown after 50 ms
delay)
(PS0) Rlim = 20k
(PS0) Rlim = 20k
9.0
10
11.0
16.5
mA
ILIM Threshold Current (immediate OCP shutdown)
13.5
15
mA
mA
ILIM Threshold Current (OCP shutdown after 50 ms
(PS1, PS2, PS3) Rlim = 20k,
10/N
delay)
N = number of phases in PS0 mode
ILIM Threshold Current (immediate OCP shutdown)
(PS1, PS2, PS3) Rlim = 20k,
N = number of phases in PS0 mode
15/N
mA
MODULATORS (PWM Comparators)
0% Duty Cycle
COMP voltage when the PWM
outputs remain LO
1.3
2.5
V
V
100% Duty Cycle
COMP voltage when the PWM
outputs remain HI VRMP = 12.0 V
PWM Ramp Duty Cycle Matching
PWM Phase Angle Error
Ramp Feed−forward Voltage range
VR_HOT#
COMP = 2 V, PWM Ton matching
1
5
%
deg
V
Between adjacent phases at 25°
5
20
Output Low Voltage
I_VRHOT = −4 mA
0.3
1.0
V
Output Leakage Current
TSENSE
High Impedance State
−1.0
mA
Alert# Assert Threshold
Alert# De−assert Threshold
VRHOT Assert Threshold
VRHOT Rising Threshold
TSENSE Bias Current
ADC
491
513
472
494
120
mV
mV
mV
mV
mA
115
125
Voltage Range
0
2
+1
1
V
%
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Power Supply Sensitivity
Conversion Time
−1
8−bit
LSB
%
1
30
90
ms
Round Robin
ms
VR_RDY, (Power Good) OUTPUT
Output Low Saturation Voltage
I
= 4 mA
0.3
V
VR_RDY
External pull−up of 1 kW to 3.3 V,
= 45 pF, DVo = 10% to 90%
Rise Time
Fall Time
100
ns
C
TOT
External pull−up of 1 kW to 3.3 V,
= 45 pF, DVo = 90% to 10%
10
ns
C
TOT
Output Voltage at Power−up
Output Leakage Current When High
VR_RDY Delay (rising)
VR_RDY pulled up to 5 V via 2 kW
VR_RDY = 5.0 V
1.0
V
−1.0
1.0
mA
ms
ms
DAC=TARGET to VR_RDY
From OCP or OVP
5
5
VR_RDY Delay (falling)
3. Guaranteed by design or characterization data, not in production test.
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NCP81142
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −40°C < T < 100°C; V = 5 V; C = 0.1 mF
A
CC
VCC
Parameter
Test Conditions
Min
Typ
Max
Unit
PWM OUTPUTS
VCC
–
Output High Voltage
Sourcing 500 mA
−
−
V
0.2V
Output Mid Voltage
Output Low Voltage
No Load, SetPS = 02
1.9
2.0
2.1
0.7
V
V
Sinking 500 mA
CL (PCB) = 50 pF,
DVo = GND to VCC
Rise and Fall Time
10
ns
PHASE DETECTION
CSN Pin Threshold Voltage
Phase Detect Timer
4.5
50
V
ms
3. Guaranteed by design or characterization data, not in production test.
STATE TRUTH TABLE
Error AMP
Method of
Comp Pin
Reset
STATE
VR_RDY Pin
OVP & UVP
DRON Pin
POR
N/A
N/A
N/A
Resistive pull down
0 < VCC < UVLO
Disabled
EN < threshold
UVLO > threshold
Low
Low
Low
Low
Disabled
Disabled
Low
Low
Start up Delay &
Calibration
EN > threshold
UVLO > threshold
DRON Fault
EN > threshold
UVLO > threshold
DRON < threshold
Low
Low
High
Low
Disabled
Resistive pull up
High
Driver must
release DRON
to high
Soft Start
Operational
Operational
Active /
EN > threshold
UVLO > threshold
DRON > High
No latch
Normal Operation
EN > threshold
UVLO >threshold
DRON > High
Active /
High
N/A
Latching
Over Voltage
Over Current
Low
Low
N/A
DAC + 150 mV
Last DAC Code
Disabled
High
Low
Operational
V
OUT
= 0 V
Low: if Reg34h:bit0 = 0;
High:if Reg34h:bit0 = 1
Clamped at
0.9 V
High, PWM outputs
in low state
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NCP81142
(VCCANDVRMP) > UVLO
Disable
EN = 1
Controller
POR
VCC < UVLO OR
VRMP < UVLO
Calibrate
Cal Done
Phase Detection and
Power On Configuration
POC done
Set DRVON High
VCCP > UVLO and DRVON High
EN = 0
Check VBoot
VBoot > 0V
DRVON
Pulled Low
VBoot = 0 V
DRVON Latch off
Turn off Drive
Wait for SVID
command
EN = 0
DRVON
Pulled Low
First VID code programmed
DRVON Pulled Low
EN = 0
Boost Cap Refresh
Boost cap done
CSREF OVP
Current Limit
Occurs
OVP Latch off.
Turn off Drive
VR_RDY = Low.
Maintain DAC voltage
and monitor for OVP
Soft Start Ramp
VR_RDY = Low
Ramp output to 0V
then force LS ON
Soft start done
(DAC + 400mV) OVP
or CSREF OVP occurs
Current Limit
Occurs
(DAC + 400mV) OVP or
CSREF OVP occurs
Normal Operation,
VR_RDY = High
DRVON Pulled
Low
DAC = VID/offset programmed.
Power state = PS programmed
EN = 0
UVP Occurs
VR_RDY = Low
DAC = VID/offset programmed.
Power state = PS programmed
Figure 3.
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NCP81142
General
The NCP81142 is a four phase dual edge modulated multiphase PWM controller, designed to meet the Intel VR12.5
specifications with a serial SVID control interface. It is designed to work in notebook, desktop, and server applications.
Serial VID interface (SVID)
For SVID Interface communication details please contact Intel Inc.
BOOT VOLTAGE PROGRAMMING
The NCP81142 has a Vboot voltage that can be externally programmed. The Boot voltage for the NCP81142 is set using
VBOOT pin on power up. A 10uA current is sourced from the VBoot pin and the resulting voltage is measured. This is
compared with the thresholds in table below. This value is set on power up and cannot be changed after the initial power up
sequence is complete.
BOOT VOLTAGE TABLE
R
VBoot
0 V
Phase Number in PS1
30.1k
49.9k
69.8k
90.9k
130k
150k
169k
Open
1
1
1
1
2
2
2
2
1.65 V
1.70 V
1.75 V
0 V
1.65 V
1.70 V
1.75 V
Remote Sense Amplifier
A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of
the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to
ǒ
Ǔ
ǒ
Ǔ
ǒ
Ǔ
VDIFOUT + VVSP * VVSN ) 1.3 V * VDAC ) VDROOP * VCSREF
This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The
non−inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier
output bias.
High Performance Voltage Error Amplifier
The Remote Sense Amplifier output is applied to a Type 3 compensation network formed by the error amplifier and external
tuning components. The non−inverting input of the error amplifier is connected to the same reference voltage used to bias the
Remote Sense Amplifier output. The integrating function of the Type 3 feedback compensation is performed internally and
does not require external capacitor Cf1 (see below).
Cf
Cf
Rin1
Rin1
Cin
Cf1
Rf
Cin
Rin2
Rin2
Rf
_
_
COMP
ERROR
COMP
ERROR
+
+
Vbias
Vbias
Figure 4. Traditional Type 3 External Compensation
Figure 5. NCP81142 Modified Type 3 External
Compensation
Initial tuning should be based on traditional Type 3 compensation. When ideal Type 3 component values have been
determined, the closest setting for the internal integrator is should be chosen based on the following table and Rin value used.
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11
NCP81142
Rin1 = 1k, Rf = 3k IN NEW CONTROLLER
Divider Gain from Digital
Equivalent Cf1 in Type III
Network
Equivalent Rf in Type III
Network
Integrator
Address Resistor
10k
22k
1
2
0.079n
0.157n
0.32n
0.63n
0.79n
0.95n
1.26n
2.52n
5.04n
3000
3000
3000
3000
3000
3000
3000
3000
3000
26k
4
51k
8
68k
10
12
16
32
64
91k
120k
160k
220k
Rin1 = 1k, Rf = 5k IN NEW CONTROLLER
Divider Gain from Digital
Equivalent Cf1 in Type III
Network
Equivalent Rf in Type III
Network
Integrator
Address Resistor
10k
22k
1
2
0.047n
0.094n
0.19n
0.38n
0.47n
0.57n
0.76n
1.51n
3.02n
5000
5000
5000
5000
5000
5000
5000
5000
5000
26k
4
51k
8
68k
10
12
16
32
64
91k
120k
160k
220k
Rin1 = 1k, Rf = 7.5k IN NEW CONTROLLER
Divider Gain from Digital
Equivalent Cf1 in Type III
Network
Equivalent Rf in Type III
Network
Integrator
Address Resistor
10k
22k
1
2
0.031n
0.063n
0.13n
0.25n
0.32n
0.38n
0.50n
1.01n
2.02n
7500
7500
7500
7500
7500
7500
7500
7500
7500
26k
4
51k
8
68k
10
12
16
32
64
91k
120k
160k
220k
Rin1 = 1k, Rf = 10k IN NEW CONTROLLER
Divider Gain from Digital
Equivalent Cf1 in Type III
Network
Equivalent Rf in Type III
Network
Integrator
Address Resistor
10k
22k
26k
1
2
4
0.024n
0.047n
0.09n
10000
10000
10000
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NCP81142
Rin1 = 1k, Rf = 10k IN NEW CONTROLLER
Divider Gain from Digital
Equivalent Cf1 in Type III
Network
Equivalent Rf in Type III
Network
Integrator
Address Resistor
51k
68k
8
0.19n
0.24n
0.28n
0.38n
0.76n
1.51n
10000
10000
10000
10000
10000
10000
10
12
16
32
64
91k
120k
160k
220k
Optimization of the traditional Type 3 compensation should be rechecked using the closest Type 3 Cf1 equivalent in order
to determine if readjustment of other component values is needed.
Differential Current Feedback Amplifiers
Each phase has a low offset differential amplifier to sense that phase current for current balance. The inputs to the CSNx and
CSPx pins are high impedance inputs. It is recommended that any external filter resistor RCSN does not exceed 10 kW to avoid
offset issues with leakage current. It is also recommended that the voltage sense element be no less than 0.5 mW for accurate
current balance. Fine tuning of this time constant is generally not required. The individual phase current is summed into the
PWM comparator feedback this way current is balanced via a current mode control approach.
RCSN
DCR
CCSN
LPHASE
RCSN
+
CCSN * DCR
SWNx
VOUT
LPHASE
1
2
Figure 6.
Total Current Sense Amplifier
The NCP81142 uses a patented approach to sum the phase currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP
and CSREF. The Ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground,
the capacitor is used to ensure that the CSREF voltage signal integrity. The amplifier actively filters and gains up the voltage
applied across the inductors to recover the voltage drop across the inductor series resistance (DCR). Rth is placed near an
inductor to sense the temperature of the inductor. This allows the filter time constant and gain to be a function of the Rth NTC
resistor and compensate for the change in the DCR with temperature.
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13
NCP81142
Rref1 10
CSN1
CSN2
CSN3
Rref2
10
10
Cref
1nF
Rfer3
Rref4
0
U1A
10
CSN4
CSREF
+
CSCOMP
CSSUM
−
Ccs1
Rph1
SWN1
SWN2
SWN3
SWN4
Ccs2
Rph2
Rph3
Rph4
R10
R
R9
R
RT1
100k
Figure 7.
The DC gain equation for the current sensing:
Rcs1*Rth
Rcs2 ) Rcs1)Rth
ǒ * DCRǓ
* IoutTotal
VCSCOMP−CSREF
+
Rph
Set the gain by adjusting the value of the Rph resistors. The DC gain should be set to the output voltage droop. If the voltage
from CSCOMP to CSREF is less than 100 mV at ICCMAX then it is recommend increasing the gain of the CSCOMP amp.
This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. When no droop is needed, the gain
of the amplifier should be set to provide ~100mV across the current limit programming resistor at full load. The values of Rcs1
and Rcs2 are set based on the 100k NTC and the temperature effect of the inductor and should not need to be changed. The
NTC should be placed near the closest inductor. The output voltage droop should be set with the droop filter divider.
The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit
to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time
constant using commonly available values. It is best to fine tune this filter during transient testing.
DCR@25° C
Fz +
2 * PI * LPhase
Programming the Current Limit
The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors
the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the
current limit comparators. The 100% current limit trips if the ILIMIT sink current exceeds 10 mA for 50 ms. The 150% current
limit trips with minimal delay if the ILIMIT sink current exceeds 15 mA. Set the value of the current limit resistor based on
the CSCOMP−CSREF voltage as shown below.
Rcs1*Rth
Rcs2)
Rcs1)Rth
ǒ
Ǔ
* IoutLIMIT * DCR
lVCSCOMP−CSREF@ILIMIT
Rph
RLIMIT
+
or RLIMIT +
10m
10m
Programming IOUT
The IOUT pin sources a current in proportion to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the
internal A/D converter and should be scaled with an external resistor to ground such that a load equal to ICCMAX generates
a 2 V signal on IOUT. A pull−up resistor from 5 V V can be used to offset the IOUT signal positive if needed.
CC
2.0 V * RLIMIT
RIOUT
+
Rcs1*Rth
Rcs2)
Rcs1)Rth
ǒ
* DCRǓ
10 *
* IoutICC_MAX
Rph
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14
NCP81142
Programming ICC_MAX
A resistor to Ground is monitored on startup and this sets the ICC_MAX value. 10 mA is sourced from these pins to generate
a voltage on the program resistor. The resistor value should be no less than 10k.
R * 10 mA * 256 A
ICC_MAX +
2 V
Programming TSENSE
A temperature sense inputs are provided. A precision current is sourced out the output of the TSENSE pin to generate a
voltage on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter.
A 100k NTC similar to the VISHAY ERT−J1VS104JA should be used. Rcomp1 is mainly used for noise. See the specification
table for the thermal sensing voltage thresholds and source current.
TSENSE
Rcomp1
0.0
Cfilter
0.1uF
Rcomp2
8.2K
RNTC
100K
AGND
AGND
Figure 8.
Precision Oscillator
A programmable precision oscillator is provided. The clock oscillator serves as the master clock to the ramp generator circuit.
This oscillator is programmed by a resistor to ground on the ROSC pin. The oscillator frequency range is between 280 kHz
to 650 kHz on the NCP81142 The graph below lists the resistor options and associated frequency setting.
NCP81142 Operating Frequency vs. R
osc
Figure 9. NCP81142 Rosc vs. Frequency
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15
NCP81142
The oscillator generates triangle ramps that are 0.5~2.5 V in amplitude depending on the VRMP pin voltage to provide input
voltage feed forward compensation. The ramps are equally spaced out of phase with respect to each other.
Programming the Ramp Feed−Forward Circuit
The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage
feed−forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 4 V
UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when
the controller is disabled.
The PWM ramp time is changed according to the following,
VRAMPpkäpkPP + 0.1 * VVRMP
Vin
Vramp_pp
Comp−IL
Duty
PWM Comparators
The noninverting input of the comparator for each phase is connected to the summed output of the error amplifier (COMP)
and each phase current (I *DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage
L
with a 1.3 V offset. The operating input voltage range of the comparators is from 0 V to 3.0 V and the output of the comparator
generates the PWM output.
During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty
cycle is still calculated by approximately Vout/Vin. During a transient event, the controller will operate in a hysteretic mode
with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps.
PHASE DETECTION SEQUENCE
During start−up, the number of operational phases and their phase relationship is determined by the internal circuitry
monitoring the CSN Pins. Normally, NCP81142 operates as a 4−phase Vcore PWM controller. Connecting CSN4 pin to V
CC
programs 3−phase operation, connecting CSN2 and CSN4 pin to V programs 2−phase operation, connecting CSN2, CSN3
CC
and CSN4 pin to V programs 1−phase operation. Prior to soft start, while ENABLE is high, CSN4 to CSN2 pins sink
CC
approximately 50 mA. An internal comparator checks the voltage of each pin versus a threshold of 4.5 V. If the pin is tied to
V , its voltage is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold.
CC
PWM1 is low during the phase detection interval, which takes 30 ms. After this time, if the remaining CSN outputs are not
pulled to V , the 50 mA current sink is removed, and NCP81142 functions as normal 4 phase controller. If the CSNs are pulled
CC
to V , the 50 mA current source is removed, and the outputs are driven into a high impedance state.
CC
The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the NCP5901 and
NCP5911 .Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition,
more than one PWM output can be on at the same time to allow overlapping phases.
PROTECTION FEATURES
Under voltage Lockouts
There are several under voltage monitors in the system. Hysteresis is incorporated within the comparators. NCP81142
monitors the VCC Shunt supply. The gate driver monitors both the gate driver V and the BST voltage. When the voltage
CC
on the gate driver is insufficient it will pull DRON low and prevents the controller from being enabled. The gate driver will
hold DRON low for a minimum period of time to allow the controller to hold off it’s startup sequence. In this case the PWM
is set to the MID state to begin soft start.
Gate Driver UVLO Restart
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16
NCP81142
Figure 10.
Soft Start
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table. The PWM signals will start out open with a test current to collect data on phase count and
for setting internal registers. After the configuration data is collected, if the controller is enabled the PWMs will be set to 2.0 V
MID state to indicate that the drivers should be in diode mode. DRON will then be asserted. As the DAC ramps the PWM
outputs will begin to fire. Each phase will move out of the MID state when the first PWM pulse is produced. When the controller
is disabled the PWM signal will return to the MID state.
Figure 11.
Over Current Latch− Off Protection
The NCP81142 compares a programmable current−limit set point to the voltage from the output of the current−summing
amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external
resistor connected between ILIM and CSCOMP is then compared to the internal current limit current I . If the current
CL
generated through this resistor into the ILIM pin (Ilim) exceeds the internal current−limit threshold current (I ), an internal
CL
latch−off counter starts, and the controller shuts down if the fault is not removed after 50 ms (shut down immediately for 150%
load current) after which the outputs will remain disabled until the V voltage or EN is toggled.
CC
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17
NCP81142
On startup a clim1/clim2 current limit protection is enabled once the output voltage has exceeded 250 mV or if the internal
DAC voltage has increased above 300 mV, this allow for protection again a Vout short to ground. This is necessary because
the voltage swing of CSCOMP cannot go below ground. This limits the voltage drop across the DCR through the current
balance circuitry.
The over−current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following
equation:
I
LIM * DCR * RCSńRPH
RILIM
+
ICL
Where I = 10 mA
CL
CSSUM
RCS
RPH
RPH
RPH
RPH
CSCOMP
RLIM
ILIM
CSREF
Figure 12.
Under Voltage Monitor
The output voltage is monitored at the output of the differential amplifier for UVLO. If the output falls more than 300mV
below the DAC−DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low.
Over Voltage Protection
The output voltage is also monitored at the output of the differential amplifier for OVP. During normal operation, if the output
voltage exceeds the DAC voltage by 400 mV, the VR_RDY flag goes low, and the DAC will be ramped down to 0 V. At the
same time, the high side gate drivers are all turned off and the low side gate drivers are all turned on until the voltage falls to
new DAC voltage 0.2 V. The part will stay in this mode until the V voltage or EN is toggled.
CC
OVP Threshold Behavior
VCC
UVLO RISING
OVP Threshold
DAC + ~400 mV
2.9 V
DAC
DRON
Figure 13. OVP Threshold Behavior
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18
NCP81142
OVP Behavior at Startup
OVP Threshold
2.9 V
Vout
DAC
DRON
PWM
Figure 14. OVP Behavior at Startup
OVP Threshold
DAC
VSP_VSN
OVP
Triggered
PWM
Latch Off
Figure 15. OVP During Normal Operation Mode
During start up, the OVP threshold is set to 2.9 V. This allows the controller to start up without false triggering the OVP.
ORDERING INFORMATION
†
Device
NCP81142MNTXG
Package
Shipping
QFN32
4000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.
www.onsemi.com
19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32 4x4, 0.4P
CASE 485CD
ISSUE A
1
DATE 09 OCT 2012
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
B
E
A
D
L
L
PIN ONE
REFERENCE
L1
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
DETAIL A
MILLIMETERS
ALTERNATE TERMINAL
CONSTRUCTIONS
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
0.15
0.25
D
D2
E
E2
e
K
K2
L
L1
4.00 BSC
0.10
0.10
C
EXPOSED Cu
MOLD CMPD
2.60
2.80
4.00 BSC
C
2.60
2.80
TOP VIEW
0.40 BSC
0.30 REF
0.45 REF
A
DETAIL B
0.05
C
ALTERNATE
A3
0.25
−−−
0.45
0.15
CONSTRUCTION
GENERIC
MARKING DIAGRAM*
0.05
C
DETAIL B
NOTE 4
A1
SEATING
PLANE
C
SIDE VIEW
XXXXXX
XXXXXX
ALYWG
G
C
A
B
0.10
DETAIL A
D2
K
9
4X
K2
XXXXX = Specific Device Code
A
L
Y
W
G
17
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
32X L
DETAIL C
CORNER LEAD
CONSTRUCTION
E2
(Note: Microdot may be in either location)
1
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
C
B
A
B
0.10
25
32X
DETAIL C
b
0.07
e
M
M
C
A
RECOMMENDED
MOUNTING FOOTPRINT
C
0.05
NOTE 3
BOTTOM VIEW
4.30
2.80
32X
0.58
PACKAGE
OUTLINE
1
2.80
4.30
8X
C0.08
32X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON66248E
QFN32 4X4, 0.4P
PAGE 1 OF 1
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