NCP339 [ONSEMI]
3 A Ultra-Small Controlled Load Switch;
| 型号： | NCP339 |
| 厂家： | 
ONSEMI |
| 描述： | 3 A Ultra-Small Controlled Load Switch |
| 文件： | 总10页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP339
3 A Ultra-Small Controlled
Load Switch with
Auto-Discharge Path and
Reverse Current Control
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The NCP339 is a very low Ron MOSFET controlled by external
logic pin, allowing optimization of battery life, and portable device
autonomy.
Indeed, due to a current consumption optimization with PMOS
structure, leakage currents are eliminated by isolating connected IC on
the battery when not used.
WLCSP6, 1.00x1.50
CASE 567FH
Reverse blocking control is automatically engage if OUT pin
voltage is higher than IN pin voltage, eliminate leakages current from
OUT to IN.
MARKING DIAGRAM
Proposed in a wide input voltage range from 1.2 V to 5.5 V, in a
small 1 x 1.5 mm WLCSP6, pitch 0.5 mm.
XX
AYWG
G
Features
• 1.2 V − 5.5 V Operating Range
• 19 mꢀ P MOSFET at 4.5 V
• DC Current up to 3 A
• Soft Start Control
• Low Quiescent Current
• Reverse Blocking
XX
A
Y
W
G
= NP or DP
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
• Active High EN pin
• WLCSP6 1 x 1.5 mm
• This is a Pb−Free Device
PACKAGE PINOUT DIAGRAM
1
2
A
OUT
IN
Typical Applications
• Mobile Phones
• Tablets
B
C
OUT
GND
IN
• Digital Cameras
• GPS
EN
• Portable Devices
• Computers
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
November, 2013 − Rev. 2
NCP339/D
NCP339
VCC
V+
LS
NCP339
DCDC Converter
or LDO
A2
B2
A1
B1
SMPS
IN OUT
IN OUT
Platform IC’n
C2
EN
100n
1
ꢁ
F
ENy
ENx
0
LS
Platform IC’n+1
Figure 1. Typical Application Circuit
Table 1. PIN FUNCTION DESCRIPTION
Pin Name
Pin Number
Type
Description
IN
A2, B2
POWER
Load-switch input voltage; connect a 1 ꢁ F or greater ceramic capacitor from IN to GND
as close as possible to the IC.
GND
EN
C1
C2
POWER
INPUT
Ground connection.
Enable input, logic high turns on power switch.
OUT
A1, B1
OUTPUT
Load-switch output; connect a 100 nF ceramic capacitor from OUT to GND as close as
possible to the IC is recommended.
IN: pin A2, B2
OUT: pin A1, B1
Gate driver and soft
start control
Control
logic
Optional
EN: C2
EN block
7 M
GND: C1
Figure 2. Block Diagram
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2
NCP339
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
-0.3 to +7.0
-7.0 to +7.0
4000
Unit
V
IN, OUT, EN, Pins: (Note 1)
V
V
V
V
EN, IN, OUT
From IN to OUT Pins: Input/Output (Note 1)
Human Body Model (HBM) ESD Rating are (Note 1 and 2)
Machine Model (MM) ESD Rating are (Note 1 and 2)
V
V
IN, OUT
ESD HBM
ESD MM
LU
V
250
V
Latch-up protection (Note 3)
− Pins IN, OUT, EN
100
mA
Maximum Junction Temperature
Storage Temperature Range
Moisture Sensitivity (Note 4)
T
T
-40 to +125
-55 to +150
Level 1
°C
°C
J
STG
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. OPERATING CONDITIONS
Symbol
Parameter
Operational Power Supply
Enable Voltage
Conditions
Min
1.2
0
Typ
Max
5.5
Unit
V
IN
V
V
EN
5.5
T
Ambient Temperature Range
Junction Temperature Range
Decoupling input capacitor
Decoupling output capacitor
Thermal Resistance Junction to Air
Maximum DC current
-40
-40
1
25
25
+85
+125
°C
°C
A
T
J
C
ꢁ F
nF
°C/W
A
IN
C
R
100
OUT
WLCSP package (Note 3)
100
ꢂ
JA
I
3
OUT
P
D
Power Dissipation Rating (Note 4)
T
A
≤ 25 °C
WLCSP package
1
W
T = 85 °C
A
WLCSP package
0.4
W
1. According to JEDEC standard JESD22-A108.
2. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020.
3. The R is dependent of the PCB heat dissipation and thermal via.
ꢂ
JA
4. The maximum power dissipation ( ) is given by the following formula:
PD
TJMAX*TA
PD
+
Rꢂ JA
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3
NCP339
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T between −40°C to +85°C for V between 1.2 V to 5.5 V (Unless otherwise noted).
A
IN
Typical values are referenced to T = +25°C and V = 5 V (Unless otherwise noted).
A
IN
Symbol
Parameter
Conditions
Min
Typ
18
19
22
27
37
48
70
Max
Unit
POWER SWITCH
R
Static drain-source
on-state resistance
Vin = 5.5 V
Vin = 5.5 V
Vin = 4.5 V
Iout = 200 mA, T = 25°C
mꢀ
DSON
A
Tj = 125°C
30
30
30
40
60
Iout = 200 mA, T = 25°C
A
Tj = 125°C
Vin = 3.3 V
Vin = 2.5 V
Vin = 1.8 V
Vin = 1.5 V
EN = low
Iout = 200 mA, T = 25°C
A
Tj = 125°C
Iout = 200 mA, T = 25°C
A
Tj = 125°C
Iout = 200 mA, T = 25°C
A
Tj = 125°C
Iout = 200 mA, T = 25°C
A
Tj = 125°C
110
90
Rdis
Output discharge path
High-level input voltage
Low-level input voltage
EN pull down resistor
Discharge path option
ꢀ
V
1.2
5.5
V
IH
IL
V
0.8
9.5
R
7.1
Mꢀ
pd
REVERSE CURRENT BLOCKING
V
Reverse threshold
Vout-Vin
40
60
mV
mV
rev_thr
V
Reverse threshold hys-
teresis
rev_hyst
T
rev
Reverse comparator re-
sponse time
Vout-Vin > V
2.5
ꢁ
s
rev_thr
QUIESCENT CURRENT
Istd Standby current
Vin = 4.2 V
Vin = 4.2 V
Vin = 4.2 V
Vout = 4.2 V
EN = low, No load, GND current
EN = low, Vout = GND, Vout current
EN = high, No load, GND current
Vin = GND
0.35
9
0.6
200
1.5
ꢁ A
nA
ꢁ A
nA
I
Mos leakage current
Quiescent current
in_leak
Iq
1.0
16
I
Output leakage current
200
out_leak
TIMINGS
T
T
T
T
T
T
T
T
Enable time
Vin = 4.2 V
(Note 6)
R = 5 ꢀ, Cout = 100 ꢁ F
1.7
2.7
4.4
ms
EN
R
L
Output rise time
ON time (T + T )
ON
F
EN
R
Output fall time
1.5
1.0
1.5
2.5
0.06
Enable time
Vin = 4.2 V
(Note 6)
R = 25 ꢀ, Cout = 1 ꢁ F
L
0.5
0.4
0.9
2.5
2.3
4.8
0.1
ms
EN
R
Output rise time
ON time (T + T )
ON
F
EN
R
Output fall time
5. Guaranteed by design and characterization.
6. Parameters are guaranteed for C and R
connected to the OUT pin with respect to the ground.
LOAD
LOAD
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4
NCP339
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T between −40°C to +85°C for V between 1.2 V to 5.5 V (Unless otherwise noted).
A
IN
Typical values are referenced to T = +25°C and V = 5 V (Unless otherwise noted).
A
IN
Symbol
Parameter
Enable time
Output rise time
ON time (T + T )
Conditions
R = 150 ꢀ, Cout = 100 ꢁ F
Min
Typ
1.7
1.5
3.2
1.8
4
Max
Unit
T
Vin = 4.2 V
(Note 6)
ms
EN
R
L
T
T
T
T
T
ON
DIS
F
EN
R
Disable time
Fall time
Output fall time
42
OFF
(T + T
)
F
DIS
5. Guaranteed by design and characterization.
6. Parameters are guaranteed for C
and R
connected to the OUT pin with respect to the ground.
LOAD
LOAD
Vin
EN
Vout
T
EN
T
R
T
DIS
T
F
T
ON
T
OFF
Figure 3. Timings
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5
NCP339
TYPICAL CHARACTERISTICS
Figure 4. Standby Current (mA) versus Vin (V)
Figure 5. Quiescent Current (mA) versus Vin (V)
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6
NCP339
Figure 6. Reverse Current (nA) versus Vin (V)
Figure 7. RDSON (mW) versus Temperature (ILOAD = 100 mA)
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7
NCP339
Figure 8. RDSON (mW) versus Vin (V)
FUNCTIONAL DESCRIPTION
Overview
Table 5. CONTROL LOGIC
The NCP339 is a high side P channel MOSFET power
distribution switch designed to isolate ICs connected on the
battery in order to save energy. The part can be turned on,
with a wide range of battery from 1.2 V to 5.5 V. Reverse
blocking from output to input control is embedded in the IC
to eliminate leakage current if Vout voltage exceed front end
power supply.
V
V
EN
Low
High
x
IN
OUT
Present
Present
Mos OFF
Mos ON
Mos OFF
V
> V
OUT IN
Auto Discharge (Optional)
Enable Input
NMOS FET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
The auto-discharge is activated when EN pin is set to low
level (disable state).
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing P MOS switch off.
The IN/OUT path is activated with a minimum of Vin of
1.2 V and EN forced to high level.
The discharge path ( Pull down NMOS) stays activated
as long as EN pin is set at low level and Vin > 1.2 V.
In order to limit the current across the internal discharge
Nmosfet, the typical value is set at 70 ꢀ.
Blocking Control
The reverse blocking feature allows to avoid reverse
current, through the PMOS fet if a voltage is applied on Vout
pin, and V
above the Vin pin. This function is
rev_thr
available, whatever the EN logic pin state (High or low). To
retrieve normal state, Vin-Vout must be higher to hysteresis
Cin and Cout Capacitors
Cin 1 ꢁ F and Cout 100 nF , at least, capacitors must be
placed as close as possible the part to for stability
improvement.
of the reverse blocking comparator (V . The reverse
rev_hyst)
blocking comparator response time is set to T
rev.
For inrush effects at start up, it’s recommended to respect
Cin > Cout size.
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NCP339
APPLICATION INFORMATION
Power Dissipation
Example of application definition.
T − T = R × P = R × R × I
DSON
2
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
J
A
ꢂ JA
D
ꢂ JA
T : junction temperature.
J
T : ambient temperature.
A
R = Thermal resistance between IC and air, through PCB.
ꢂ
equations:
R : intrinsic resistance of the IC Mosfet.
DSON
2
• P = R
× (I
)
D
DS(on)
OUT
I: load DC current.
P
= Power dissipation (W)
D
R
I
= Power MOSFET on resistance (ꢀ)
= Output current (A)
DS(on)
OUT
Taking into account of R obtain with:
ꢂ
• 1 oz, 2 layers: 100°C/W.
At 3 A, 25°C ambient temperature, R
20 mꢀ @
DSON
• T = P × R
+ T
J
D
ꢂ
J
A
A
Vin 5 V, the junction temperature will be:
T
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
J
2
T = T + R × P = 25 + (0.02 × 3 ) × 100 = 43°C
J
A
ꢂ
D
R
T
ꢂ JA
A
Taking into account of R obtain with:
ꢂ
• 2 oz, 4 layers: 60°C/W.
PCB Recommendations
At 3 A, 65°C ambient temperature, R
24 mꢀ @
DSON
The NCP339 integrates an up to 3 A rated PMOS FET, and
the PCB design rules must be respected to properly
evacuate the heat out of the silicon. By increasing PCB
Vin 5 V, the junction temperature will be:
2
T = T + R × P = 65 + (0.024 × 3 ) × 60 = 78°C
J
A
ꢂ
D
area, especially around IN and OUT pins, the R
of the
ꢂ
J
A
package can be decreased, allowing higher power
dissipation.
Routing example: 2 oz, 4 layers with vias across 2 internal
inners.
Figure 9.
ORDERING INFORMATION
†
Device
Marking
Option
Package
Shipping
NCP339AFCT2G
NP
Without Auto−discharge
WLCSP6, 1 x 1.5 mm
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NCP339BFCT2G
DP
With Auto−discharge
WLCSP6, 1 x 1.5 mm
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCP339
PACKAGE DIMENSIONS
WLCSP6, 1.00x1.50
CASE 567FH
ISSUE O
D
A
NOTES:
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN A1
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
E
MILLIMETERS
DIM
A
A1
A2
b
MIN
0.54
0.22
MAX
0.63
0.28
2X
0.05
0.05
C
0.33 REF
0.29
0.34
2X
C
TOP VIEW
SIDE VIEW
D
E
e
1.00 BSC
1.50 BSC
0.50 BSC
A2
0.05
C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.05
C
A1
SEATING
PLANE
PACKAGE
OUTLINE
NOTE 3
C
A1
eD/2
eD
6X
b
eE
0.05
0.03
C
C
A B
C
0.50
6X
0.25
PITCH
B
A
0.50
PITCH
DIMENSIONS: MILLIMETERS
1
2 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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NCP339/D
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