NCP1871_技术文档

NCP1871

Narrow Voltage DC Battery

Charger

The NCP1871 is a NVDC switching battery charger designed for

2−3−4 battery cell applications such as ultra books or tablets. It is

optimized for use with the mobile computing chipsets, and is also

compatible with most mobile solutions.

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The NCP1871 is designed around a full NMOS DC to DC controller

that brings down the high voltage charger adapter voltage to a

regulated system supply that is in the same range as the battery pack

voltage. This limits the variation on the system supply voltage, and

improves the efficiency of the core converters. The device includes a

voltage droop monitor, charger adapter validation and blocking as well

as an intelligent battery connection control. The adapter current,

charge current and system current are closely monitored and an image

is provided to the host. The NCP1871 is fully programmable through

1

QFN20

MN SUFFIX

CASE 485CP

MARKING DIAGRAM

2

an I C friendly SMBus Interface.

XXXXX

ALYWG

G

Features

• SMBus Host−controlled NVDC−1 2S−4S Battery Charge Controller

• Instant−on Works with No Battery or Deeply Discharged Battery

• Automatic Supplement Mode with BATFET Control

• Battery Removal Sensor

XXXXX = Specific Device Code

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Programmable Switching Frequency

2

• SMBUS Clock up to 400 kHz (I C compatible)

(Note: Microdot may be in either location)

• Programmable Charge Current, Charge Voltage, Input Current Limit

with Interrupt Management

♦

0.5% Charge Voltage Regulation up to 18.08 V

3% Input/Charge Current Regulation up to 8.064 A

PIN CONFIGURATION

• Support Battery LEARN Function

• Support Shipping Mode and Hard System Reset

• Ultra−Low Quiescent Current of 10 mA at OFF Mode and High PFM

Light Load Efficiency 80% at 20 mA Load to Meet Energy Star and

ErP Lot6

20 19 18 17 16

1

2

3

4

5

15

14

13

12

11

ACSP

RBDRV

VIN

LSDRV

BCSP

GND

BCSN

• Full NMOS Solution

• Current and Power Monitoring

VSEL

BATDRV

VBAT

VINOK

6

7

8

9

10

• 3.5 mm x 3.5 mm QFN−20 Package

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

(Top View)

Typical Applications

• Ultrabook

• Notebook

ORDERING INFORMATION

• Tablet PC

†

Device

NCP1871MNTXG

Package

Shipping

QFN20

(Pb−Free)

3000 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

1

Publication Order Number:

June, 2016 − Rev. 0

NCP1871/D

NCP1871

RIN

CIN

L_X

COUT1

AC

ADAPTOR

QLS

RAC

SYSTEM

LOAD

QAC

QRB

CAC

QHS

DF

CBOOT

COUT2

RBC

RCELL

VIN

RBDRV

ACSP ACSN HSDRV

SW CBOOT LSDRV

BCSP

VDD

VSEL

10k

BCSN

BATDRV

VINOK

SDA

HOST

QBAT

NCP1871

SCL

VBAT

RTS

PRHOTB

PMO

CBAT

TS

BATTERY

PACK

RPMO

VCORE

GND

CCORE

+5V

Figure 1. Typical Application Circuit

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2

NCP1871

20 19 18 17 16

1

2

3

4

5

15

ACSP

RBDRV

VIN

LSDRV

BCSP

14

13

12

11

GND

BCSN

VSEL

BATDRV

VBAT

VINOK

6

7

8

9

10

Figure 2. Pin Out Description (Top View)

Table 1. PIN FUNCTIONAL DESCRIPTION

Name

Type

Description

1

ACSP

ANALOG INPUT

Charger Adapter Current Sense Positive terminal. Use a 10 mW sense resistor

RAC. Bypass ACSP with a 10 mF capacitor

2

RBDRV

ANALOG OUTPUT

Reverse Blocking FET Driver. Drives the gate of the RBFET NMOS

Can also drive gate optional ACFET NMOS.

3

4

VIN

ANALOG INPUT

Charger Adapter Input. Bypass with a Damping network

VSEL

Adapter detection input. Program adapter valid input threshold by connecting a

resistor divider from adapter input to VSEL pin to GND pin. Connect a serial resis-

tance of 220 kW to select 3−4 Cells default setting.

5

VINOK

OPEN DRAIN OUTPUT

Charge Adapter Valid Output. Signals the VIN is within the target range.

Open drain output requiring an external pull up. Also use for short pulse signal inter-

rupt generation

6

7

PRHOTB

PMO

OPEN DRAIN OUTPUT

ANALOG OUTPUT

Processor Hot Signal Output. Pulled low to reduce processor speed based on BCSP.

Current based indication of system power. Amplified version of the adapter power,

the battery power or sum of both.

8

SDA

SCL

DIGITAL IN/OUT

DIGITAL INPUT

Control Bus Data Line.

9

Control Bus Clock Line.

10

11

12

13

14

15

16

17

18

19

TS

ANALOG INPUT

ANALOG IN/OUT

ANALOG OUTPUT

ANALOG INPUT

ANALOG OUTPUT

ANALOG IN/OUT

ANALOG OUTPUT

Battery Presence Detection. Connect this pin to the battery thermistor sensor.

Battery Connection. Bypass with at least 10 mF capacitor.

Battery FET Driver.

VBAT

BATDRV

BCSN

BCSP

LSDRV

VCORE

CBOOT

SW

Battery Current Sense Negative Terminal. Use a 10 mW sense resistor RBC.

Battery Current Sense Positive Terminal. Use a 10 mW sense resistor RBC.

Low Side Switch Driver. Drives the gate of the DC to DC low side NMOS.

Core Voltage. Do not connect load on this pin. Bypass with a 2.2 mF capacitor

Bootstrap Capacitor Connection.

Switching Node. Connection to the 2.2 mH inductor.

HSDRV

High Side Switch Driver. Drives the gate of the DC to DC high side NMOS. Supplied

from the bootstrap capacitor.

20

−

ACSN

ANALOG INPUT

GROUND

Charger Adapter Current Sense Negative terminal.

Use a 10 mW sense resistor RAC.

EXPOSE

PAD

Internally connected to ground

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3

NCP1871

Table 2. MAXIMUM RATINGS

Rating

Symbol

Value

Unit

V

VIN , RBDRV (Note 1)

V

−0.3 to +30

−0.3 to +7.0

MR_AC

ACSP, ACSN, HSDRV, SW, CBOOT, BCSP, BCSN, BATDRV, VBAT (Note 1)

TS (Note 1)

V

MR_ACS

MR_DRP

V

CBOOT with respect to SW (JEDEC standard JESD22−A108)

LSDRV, VCORE, PRHOTB, PMO, VINOK, VSEL (Note 1)

V

MR_CBOOT

V

MR_LV

V

Digital Input: SCL, SDA (Note 1)

Input Voltage

V

−0.3 to +7.0 V

20

V

DG

Input Current

I

mA

DG

Human Body Model (HBM) ESD Rating are (Note 2)

Charged Device Model (CDM) ESD Rating are (Note 2)

Latch up Current (Note 3):

ESD HBM

ESD CDM

1500

750

V

I

LU

mA

All Digital pins( V

VINOK, VSEL

All others pins.

)

DG

10

30

100

Storage Temperature Range

T

−65 to + 150

−40 to + TSD

Level 1

°C

STG

Maximum Junction Temperature (Note 4)

Moisture Sensitivity (Note 5)

T

J

MSL

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. With Respect to GND. According to JEDEC standard JESD22−A108.

2. This device series contains ESD protection and passes the following tests:. Human Body Model (HBM) 1.5 kV per JEDEC standard:

JESD22−A114. Charged Device Model (CDM) 750 V per JEDEC standard: JESD22−C101.

3. Latch up Current Maximum Rating: 100 mA or per 10 mA JEDEC standard: JESD78 class II.

4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation.

5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.

Table 3. OPERATING CONDITION

Symbol

Parameter

Operational Power Supply

Digital input voltage level

Ambient Temperature Range

VINOK sink current

Conditions

Min

4.5

0

Typ

Max

Unit

V

IN

V

INOV

V

DG

5.5

V

T

A

−40

25

+85

10

°C

mA

mF

W

I

SINK

C

R

Decoupling input capacitor

Damping resistor

4.7

2

IN

C

Decoupling Switcher capacitor

Bootstrap capacitor

10

100

2.2

47

2.2

10

mF

nF

mF

mH

mW

AC

C

BOOT

C

CORE

Decoupling core supply capacitor

Decoupling system capacitor

Switcher Inductor

C

, C

OUT1

OUT2

L

X

R

, R

Current sense resistor

RDSON resistance

AC

BC

R

N−channel

MOSFET

DSONQRB, DSONQHS,

DSON QLS, DSONQB

V

= 5 V

GS

C

,C

, C

GQB

Total Gate Charge

10

50

25

nC

°C/W

°C

GQRB GQHS

GQLS

R

Thermal Resistance Junction to Air

Junction Temperature Range

(Notes 4 and 6)

q

JA

J

T

−40

+125

6. The R

is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard.

q

JA

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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4

NCP1871

Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −20°C to +85°C and T up to + 125°C for V

IN

A

J

between 4.5 V to 22 V (Unless otherwise noted). Typical values are referenced to T = + 25°C and V = 12 V (Unless otherwise noted).

A

IN

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

INPUT VOLTAGE

V

Presence input detection threshold

V

rising

3.2

3.5

175

150

50

3.8

V

mV

V

INDET

IN

Hysteresis

Charger mode detection threshold

voltage

V

– V , V rising

BCSP IN

95

10

200

90

INSYS

IN

– V

, V falling

BCSP IN

V

rising

SEL

1.188

25

1.2

50

1.212

75

INLO

Hysteresis

rising

mV

V

Cells detection threshold

V

SEL

0.4

0.45

50

0.5

CELL

Hysteresis

rising, Ratio of V

SYSMIN

mV

%

V

Operating charger valid

threshold

V

IN

103.4

101.4

22

106

104

22.5

125

10

108.6

106.6

23

INMINOK

Hysteresis

rising (Note 7)

%

V

Valid input high threshold

Max Hot Plug Rise time

V

IN

V

INOV

Hysteresis

mV

V/ms

T

ACFET present, from 0 to 30 V,

no overvoltage on ACSP

VINOV

RBFET only, from 0 to 30 V,

no overvoltage on BCSP

10

INPUT CURRENT LIMITING

I

Input current limit

Input Current Limit Range,

Average value.

128

8064

mA

INLIM

Input Current Limit Default. (Note 8)

Input Current Granularity

3328

128

mA

%

Input Current

Accuracy

128 mA to 2048 mA

2048 mA to 4096 mA

−64

−3

+64

+3

T

Current Ramping

128/16

11

mA/ms

A

IIN

I

Short Circuit Detect

Short Circuit Detect Delay

Input Current Limit ILIM

10

12

INSHORT

T

10

ms

INSHORT

BATTERY AND SYSTEM VOLTAGE

V

Output voltage range

Programmable

3328

−0.5

18080

0.5

mV

CHG

Default value, (Note 9)

V

+

SYSMIN

SYSOFF

Voltage regulation accuracy

Programmable granularity

Voltage Ramping

Constant voltage mode, ICHG>=500 mA

%

mV

mV/ms

V

16

64/16

10.8

14.4

21.6

102

V

System OVP

VBCSP

Rising

VCHG ≤ 9V

SYSOV

9 V ≤ VCHG ≤ 13.5 V

VCHG > 13.5 V

V

SYSOV Release Threshold

Buck Out of Regulation

Hysteresis, Ratio of V

Rising Edge

%

CHG

V

VBCSP Rising, Ratio of V

Rising

CHG

104

%

BUCKOV

Edge

BUCKOV Release Threshold

Hysteresis

102

%

7. 19 V and 14.5 V versions are available upon request

8. 2560 mA versions is available upon request

9. 5.6 V, 12.352 V and 16.592 V versions are available upon request

10.512 mA, 1024 mA and 2048 mA versions are available upon request

11. 256 mA, 128 mA and 0 mA versions are available upon request

12.5.6 V, 5.7 V, 5.8 V versions are available upon request

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5

NCP1871

Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −20°C to +85°C and T up to + 125°C for V

IN

A

J

between 4.5 V to 22 V (Unless otherwise noted). Typical values are referenced to T = + 25°C and V = 12 V (Unless otherwise noted).

A

IN

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

BATTERY AND SYSTEM VOLTAGE

V

Minimum System Voltage Range

Minimum System Voltage Default

3328

17792

mV

SYSMIN

RCELL = 0 W (2−3 cells)

RCELL = 220 kW (3−4 cells)

Hysteresis

7936

12032

50

Minimum System Voltage

Granularity

128

V

System Voltage Regulation Offset

SYSOFF_SEL = 0, Default

SYSOFF_SEL = 1

384

256

mV

SYSOFF

CHARGE CURRENT

I

Charge current range

Programmable

128

8064

mA

%

CHG

Default value, (Note 10)

128 mA to 2048 mA

2048 mA to 8064 mA

128

Charge current accuracy

−64

−3

+64

3

2

I C Programmable granularity

128

mA

mA/ms

mA

T

ICHG

Current Ramping

128/16

I

End of Charge Current Range

End of Charge Current Default

End of Charge Current Granularity

End of Charge Current Accuracy

128

−64

1024

+64

EOC

256

128

REVERSE BLOCKING FET

T

RBDRV Rise Time

RBDRV Fall Time

RBDRV Output High

3 nC Load

2

1

ms

V

RBDR

T

10 nC Load

RBDF

R

Referred to ground

Referred to VIN, VIN ≥ 9 V

30

RBDL

4.45

5

0

5.5

V

RBDH

V

RBDRV Output Low

V

< V

, Referred to VIN

ACSP

V

RBDL

RBDH

IN

V

> V

, Referred to ACSP

V

ACSP

VINOK PIN

V

FLAG output low voltage

Off−state leakage

I

= 3 mA

= 5 V

0.4

1

V

OL

INOKLK

VINOK

I

V

mA

VINOK

BATTERY MOSFET FET and PRECHARGE MODE

V

Precharge Current Reduction

Range

SYSOFF_SEL = 0,

BCSP−VSYSMIN, IBAT(DC) = 0 A.

49

0

399

128

mV

PRERED

V

Precharge Current Reduction

Range

BCSP−VSYSMIN, IBAT(AC) = 0 A.

End of Charge, VBAT−BCSP

Supplement, VBAT−BCSP

PRESTOP

V

Battery FET Reconnect Detection

Threshold

256

mV

DRCON

V

Battery FET Re−open Detection

Threshold

−1

+5

DOPEN

7. 19 V and 14.5 V versions are available upon request

8. 2560 mA versions is available upon request

9. 5.6 V, 12.352 V and 16.592 V versions are available upon request

10.512 mA, 1024 mA and 2048 mA versions are available upon request

11. 256 mA, 128 mA and 0 mA versions are available upon request

12.5.6 V, 5.7 V, 5.8 V versions are available upon request

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6

NCP1871

Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −20°C to +85°C and T up to + 125°C for V

IN

A

J

between 4.5 V to 22 V (Unless otherwise noted). Typical values are referenced to T = + 25°C and V = 12 V (Unless otherwise noted).

A

IN

Symbol

Parameter

Conditions

Min

Typ

100

98

Max

Unit

BATTERY MOSFET FET and PRECHARGE MODE

V

PRE

Precharge voltage threshold

V

rising, Ratio of V

SYSMIN

%

BAT

Accuracy

−2

+2

Hysteresis

%

I

Precharge Current Range

Precharge Current Default

Precharge Current Accuracy

BATDRV Output High

BATDRV Output Low

BATDRV Fall Time

128

512

mA

V

PREMAX

Default value (Note 11)

512

−64

4.5

+64

8

V

BFH

VBAT ≥ 3.3 V, Referred to VBAT

5

0

V

BFL

Referred to GND

−0.3

0.3

V

T

From V

to V , 10 nC Load

200

2

ms

FBF

BFH

BFL

BATDRV Rise Time

to V

3 nC Load, From

FBR

BFL

BFH

End of Charge to Supplement mode

From V to V , 3 nC Load.

5

ms

BFL

BFH

2

I C/SMBus

F

Bus operating frequency

Bus Timeout

10

25

400

35

kHz

ms

V

SCL

T

I2CTO

VI

2CINT

Peak voltage at SCL line

SCL, SDA low input voltage

SCL, SDA high input voltage

SDA low output voltage

2.7

−0.5

1.7

0

5.5

0.5

5.5

0.4

V

I2CIL

I2CIH

I2COL

V

Sink 3 mA

V

BUCK CONVERTER

F

Switching Frequency Range

Switching Frequency Default

Switching Frequency Granularity

Switching Frequency Accuracy

600

−10

1200

+10

kHz

%

SWCHG

800

200

F

Spread Spectrum Modulation

Bandwidth

Ratio of FSW

6

%

SWSMB

Spread Spectrum Modulation Rate

Output Current Capability

23

kHz

A

SWSMR

I

8

OUTMAX

I

Maximum peak inductor current

9

A

PKMAX

GENERAL PARAMETERS

I

OFF Mode quiescent current

(Measured on BAT)

PMO_EN = 0, VDROOP_EN = 0,

VIN = 0 V, 2~3 Cells

10

12

80

mA

OFF

QLB

PMO_EN = 0, VDROOP_EN = 0,

VIN = 0 V, 4 Cells

I

Drop Detection Quiescent Current

(Measured on BAT)

OFF mode. PMO_EN = 0,

VDROOP_EN = 1 VIN = 0 V, VBAT>

V , VDRP_SEL ! = 00, 2~3 Cells

LOBAT

OFF mode. PMO_EN = 0,

140

VDROOP_EN = 1 VIN =0V, VBAT>

V ,VDRP_SEL ! = 00, 4 Cells

LOBAT

I

PMO block quiescent current

(Measured on BAT)

OFF mode. PMO_EN = 1, VDROOP_EN

= 0 VIN = 0 V, VBAT> 4 V

1500

mA

STBY

7. 19 V and 14.5 V versions are available upon request

8. 2560 mA versions is available upon request

9. 5.6 V, 12.352 V and 16.592 V versions are available upon request

10.512 mA, 1024 mA and 2048 mA versions are available upon request

11. 256 mA, 128 mA and 0 mA versions are available upon request

12.5.6 V, 5.7 V, 5.8 V versions are available upon request

www.onsemi.com

7

NCP1871

Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T between −20°C to +85°C and T up to + 125°C for V

IN

A

J

between 4.5 V to 22 V (Unless otherwise noted). Typical values are referenced to T = + 25°C and V = 12 V (Unless otherwise noted).

A

IN

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

GENERAL PARAMETERS

E

ECO

NCP1871 Efficiency

With Recommended operating condition,

VIN = 12 V , VBAT = 8.4 V, PMO_EN =

0, VDROOP_EN = 0 ECO_MODE = 1,

20 mA load

80

%

V

Core supply voltage

System UVLO

VIN > 5.5 V

5

V

CORE

V

VIN or VBAT rising, SMBus register

available

4

UVLO

T

SD

Thermal Shutdown

135

°C

CURRENT AND POWER MONITORING

G

Battery Current Sense Gain

GBC_SEL = 0, Default

GBC_SEL = 1

0.2

0.4

2

mA/mV

mA/V

BC

A

BC

Battery Voltage Sense Scaling

Adapter Current Sense Gain

Adapter Voltage Sense Scaling

Mixer Gain

G

0.2

2

mA/mV

mA/V

AC

A

2

K

, K

GAIN_SEL = 0, Default

GAIN_SEL = 1

Full Scale

250

500

100

kA/A

AC

BC

2

kA/A

I

Power Monitor Output Current

mA

%

kHz

%

V

PMO

I

,I

Power Monitor Accuracy

per channel

1.00x Full Scale

0.10x Full Scale

0.03x Full Scale

−5

5

PAC PBC

−8.5

−20

8.5

20

F

PMO

Power Monitor Bandwidth

8

V

VDRP Fast Comparator Reference

Voltage

DRP_SEL = 00, Relative to V

DRP_SEL = 01

97

5.6

5.8

6

DRPREF

SYSMIN

DRP_SEL = 10, Default

DRP_SEL = 11

V

VDRP Fast Comparator Accuracy

VDRP Fast Comparator Debounce

−2.1

+2.1

%

ms

%

2

V

LOBAT

VDRP Slow Comparator

Detection Level

VLOBAT_REG = 00, Ratio of VDRPREF

VLOBAT_REG = 01

OFF

105

107.5

110

VLOBAT_REG = 10, Default

VLOBAT_REG = 11

T

VDRP Slow Comparator Debounce

PRHOTB Sink Capability

128

ms

mA

ms

V

LBDEB

I

Output 0.4 V

40

LBSK

T

Pulse Stretch Duration

10

2.85

1.6

4

LBPS

V

Battery Removal Detection

Threshold

BATRMV_SEL = 0, Default

BATRMV_SEL = 1

2.7

1.5

3

BAT_RMV

1.7

Battery Removal Detection time

TS Input Leakage

ms

I

100

nA

BAT_RMV

7. 19 V and 14.5 V versions are available upon request

8. 2560 mA versions is available upon request

9. 5.6 V, 12.352 V and 16.592 V versions are available upon request

10.512 mA, 1024 mA and 2048 mA versions are available upon request

11. 256 mA, 128 mA and 0 mA versions are available upon request

12.5.6 V, 5.7 V, 5.8 V versions are available upon request

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8

NCP1871

Charging Process

INCHG_OK = (INOK and not VINOK_SEL) or (INMINOK and VINOK_SEL)

SYS RST STATES

(HW_RST & RST_TMR) or (BAT_DIS & INDET)

UVLO

HW_RST

OFF

−Core OFF (10

−DCDC OFF

−SMBus available

−BATFET ON

−RBFET OFF

CONFIG

−Core = OFF (BAT_DIS)

−Core = ON (HW_RST)

−DCDC OFF

−SMBus available

−BATFET OFF

−Core ON

μA

)

INDET or

HW_RST

−DCDC OFF

−SMBus available

−BATFET ON

−RBFET OFF

(not INDET) &

(not BAT _DIS)

(HW_RST and RST_TMR)

or

(BAT_DIS & RST_TMR &

not INDET)

INSYS and

not INSYS or

SYSOV or

IINSHORT or

INOVP

not SYSOV and

not SYSOV_INT and

not IINSHORT_INT and

not INOVP

STBY STATES

CHARGE STATES

HOLD

TSD or

−Core ON

−DCDC OFF

−SMBus available

−BATFET ON

−RBFET ON

TSD or

CHR_DIS or

WD_TMR or

CHR_DIS or

WD_TMR or

not INCHG_OK

10ms timer and

INCHG_OK and

not ldo_mode &

not PRE &

not (SYSOV

TSD or

CHR_DIS or

WD_tmr) and

not LEARN

10 ms timer and

INCHG_OK and

(ldo_mode or

PRE) and

not (SYSOV

TSD or

CHR_DIS or

WD_tmr)

PRE CHARGE

FULL CHARGE

−Core ON

−DCDC ON

−SMBus available

−BATFET ON

−RBFET ON

PRE

−Core ON

−DCDC ON

−SMBus available

−BATFET: PRECHARGE

−RBFET ON

not PRE and not ldo_mode

not EOC

and not IEOC_EN

or LEARN

EOC or

(IEOC and IEOC_EN)

END OF CHARGE

SUPPLEMENT

−Core ON

−DCDC ON

DRCON

−Core ON

−DCDC ON

−SMBus available

−BATFET ON

−RBFET ON

−SMBus available

−BATFET OFF

−RBFET ON

DOPEN and not

LEARN

ACTIVE CHARGE STATES

Figure 3. Charging State Machine

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9

NCP1871

Block Diagram

SW

LSDRV

VIN

RBDRV

ACSP

ACSN

HSDRV

CBOOT

VCORE

HSS

INPUT VOLTAGE

+

INDET

V_IN

V_INDET

−

Drv

LSS

Charge

Pump

Amp

BUCK CONVERTER

+

BCSP

INOVP

V_INOV

−

V_IIN

Drv

V_IINSHOR

INMINOK

T

V_SYSMIN

V_INMINOK

x

V_CHG

V_SYSMIN

V_SYSOFF

,

−

+

V_BCSP

−

VBAT

REVERSE BLOCKING FET

V_BUCKREG

INSYS

CELL

INSHORT

−

+

Amp

V_INSYS

+

INPUT CURRENT LIMIT

+

BUCKOK

+

−

V_CHGx V_BUCKOV

−

V_CELL

HSS

+

SYSOV

VSEL

V_IIN

+

−

+

V_SYSOV

INOK

−

22k

QCELL

V_BUCKREG

V_INLO

QC_DRV

BATTERY AND SYSTEM VOLTAGE

+

−

LSS

V_IBAT

V_REF

−

CHARGE CURRENT

V_IBAT

Amp

+

BCSN

+

−

IEOC

V_{BAT _RMV}

V_IEOC

BUCK CONVERTER

VBAT

Ideal diode

−

+

BAT_RMV

TS

+

−

DOPEN

VIN

V_DOPEN

V_BCSP

VBAT

VCORE

VDRPREF

Charge

Pump

V_PRERED

V_IPREMAX

V_IBAT

−

V_REF

CLOCK

I_REF

Current,

Voltage,

and Clock

Reference

POR

EN

+

VLOBAT

ACSN

VCORE

BATDRV

VBAT

TSD

Drv

ACSP

ON/OFF

VBAT

EN

G_AC

BATTERY MOSFET AND

PRECHARGE MODE

A_AC

SMD Digital

& registers

KAC

+

V_SYSMIN

PRE

−

Enable on POR

IPAC

BCSP

PMO

+

−

DRCON

IPBC

+ V_DRCON

SDA

SCL

CHARGER CONTROL

KBC

EN

G_BC

A_BC

SMB Physical Interface

I@C / SMBUS

BCSN

PRHOTB

BCSP

ACOK_DRV

Pulse Generator

VINOK

POWER MONITORING

VINOK & INT

GND

Figure 4. Detailed Block Diagram

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10

NCP1871

SMBUS Registers Map

SMBUS slave address (binary): b0001001x.

ChargeOption Register − Memory Location : 12h

Bit

0

Type

RW

Reset

Name

CHR_DIS

EOC

RST Value

Function

POR, TR_OFF

0

Charge is suspend when set 1

1

RW

Set 1 will jump to End of Charge state from FULL

charge: signal dictated by the Fuel Gauge

2

3

4

5

6

RW

POR, TR_OFF

IEOC_EN

LEARN

0

Set 1 enable the charger end of charge detection

Set 1 enable the LEARN mode

PMOBAT_EN

PMOAC_EN

GAIN_SEL

Set 1 enable the Battery Power monitoring circuitry

Set 1 enable the Input Power monitoring circuitry

Multiplier Gain selection

0: Full scale 100 W

1: Full scale 50 W

7

8

9

RW

POR, TR_OFF

PMO_IMO_SEL

GBC_SEL

0

1

0 : PMO selected

1: IMO selected

0: Battery Current Sense Gain is 10

1: Battery Current Sense Gain is 20

WDTMR_SET[0]

Watchdog timer [1:0]:

00: Disable

01: 32s

10: 64s

11: 128s

10

11

12

13

14

15

RW

POR, TR_OFF

WDTMR_SET[1]

FREQ_SEL[0]

0

01

DCDC frequency selection[1:0]:

00: 600 kHz

01: 800 kHz

10: 1000 kHz

11: 1200 kHz

FREQ_SEL[1]

VLOBAT_REG[0]

VLOBAT_REG[1]

VDROOP_EN

0

1

0

Ratio of VDRPREF[1:0]:

00: Off

01: 105%

10: 107.5%

11: 110%

0: Critical Voltage Monitoring disable

1: Critical Voltage Monitoring enable

ChargeCurrent Register − Memory Location : 14h

Bit

Type

Reset

Name

RST Value

Function

0

RW

POR, TR_OFF

IPRE_0

11

00: 0 mA

01: 128 mA

10: 256 mA

11: 512 mA

1

RW

POR, TR_OFF

IPRE_1

2

3

R

Not Used

4

R

5

R

6

R

7

RW

R

POR, TR_OFF

ICHG_0

ICHG_1

ICHG_2

ICHG_3

ICHG_4

ICHG_5

000001

000001 : 128 mA (Lower Clamp)

111111: 8064 mA (Higher Clamp)

Step : 128 mA

8

9

10

11

12

13

14

15

Not Used

R

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11

NCP1871

ChargeVoltage Register − Memory Location : 15h

Bit

0

Type

R

Reset

Name

RST Value

Function

Not Used

1

R

2

R

3

R

4

RW

R

POR, TR_OFF

VCHG_0

VCHG_1

VCHG_2

VCHG_3

VCHG_4

VCHG_5

VCHG_6

VCHG_7

VCHG_8

VCHG_9

VCHG_10

VSYSMIN +

VSYSOFF

00000000000 : 3.328 V

00011010000 : 3.328 V (Lower Clamp)

10001101010 : 18.080 V (Higher Clamp)

11111111111 : 18.080 V

5

6

7

Step : 16 mV

8

9

10

11

12

13

14

15

Not Used

ChargeOption2 Register − Memory Location : 3Ch

Bit

0

Type

RW

Reset

Name

RST Value

Function

POR, TR_OFF

HW_RST

BAT_DIS

0

Set 1 will disconnect the battery after RST_TMR

1

RW

Set 1 disconnect the battery when

IN unplug until the next IN plug

2

3

4

RW

R

POR, TR_OFF

FAULT_MSK

STATUS_MSK

STATE[0]

0

Set 1 Mask fault interuption

Set 1 Mask Status interruption

Charge state [2:0]:

000: OFF

001: CONFIG

010: HOLD

5

6

R

STATE[1]

STATE[2]

011: PRECHARGE

100: FULLCHARGE

101: SUPPLEMENT

110: END OF CHARGE

111: HW_RST

7

8

9

RW

POR, TR_OFF

RST_TMR_SET[0]

RST_TMR_SET[1]

FREQ_S_EN

0

1

0

Reset Timer

00: 0 ms

01: 512 ms

10: 1024 ms

11: 2048 ms

Frequency Spread Spectrum enable

0: Disable

1: Enable

10

11

RW

POR, TR_OFF

CPEXIT_EN

IEOC[0]

0

1

0: CP exit disable

1: CP exit Enable

000: 128 mA

001: 256 mA

010: 384 mA

011: 512 mA

100: 640 mA

101: 768 mA

110: 896 mA

111: 1024 mA

12

13

RW

POR, TR_OFF

IEOC[1]

IEOC[2]

0

14

15

RW

POR, TR_OFF

LDO_MODE

ECO_MODE

0

1

Set 1 select LDO mode

0: No Eco Mode

1: Eco Mode

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12

NCP1871

Interrupt Register − Memory Location : 3Dh

Bit

0

Type

RC

R

Reset

Name

RST Value

Function

Flag End of Charge State is reached

Flag Precharge state is reached

Flag entering/exiting Learn mode

Flag a WatchDog Timer expired

Flag IPEAK MAX is reached

Flag VIN> VINOV

POR, OFF

POR

EOC_INT

0

1

PRE_INT

2

LEARNB_INT

WDOG_INT

IPEAK_INT

3

4

5

INOVP_INT

BUCK_OVP_INT

IINSHORT_INT

HW_RST_INT

BAT_DIS_INT

SYSOV_INT

BAT_RMV_INT

6

Flag BUCK OV

7

Flag IIN> IINSHORT

8

RC

W1C

RC

R

Flag HW_RST state and HW_RST=1

Flag HW_RST state and BAT_DIS=1

Flag System Overvoltage

Flag battery is removed

Not Used

9

POR

10

11

12

13

14

15

POR, OFF

R

Not Used

R

Not Used

R

Not Used

MinSysVoltage Register − Memory Location : 3Eh

Bit

Type

Reset

Name

RST Value

Function

0

RW

POR, TR_OFF

VDYNPRE_EN

1

0: Dynamic precharge disable

1: Dynamic precharge enable

1

RW

POR, TR_OFF

VINOK_SEL

0

Control VINOK signal

0: INOK is set by VSEL

1 INOK is set by VSYSMIN

2

3

R

Not Used

R

4

R

5

R

6

R

7

RW

POR, TR_OFF

VSYSMIN_0

VSYSMIN_1

VSYSMIN_2

VSYSMIN_3

VSYSMIN_4

VSYSMIN_5

VSYSMIN_6

VSYSMIN_7

N_CELL_EN

See electrical

characteristics

00000000 : 3.328 V

00011010 : 3.328 V (Lower Clamp)

10001011 : 17.792 V (Higher Clamp)

11111111 : 17.792 V

8

9

10

11

12

13

14

15

Step : 128 mV

1

0: VSYSMIN default value detection disable

1: VSYSMIN default value detection enable

Reset Legend:

• OFF: Set bit to RST VALUE when the charging state machine is in OFF state.

• TR_OFF: Set bit to RST VALUE when the charging state machine transits to OFF state.

• POR: Set bit to RST VALUE on power on reset.

• W1C : Need to write 1 to reset this bit to 0

• RC : Read this bit to reset to 0

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13

NCP1871

InputCurrent Register − Memory Location : 3Fh

Bit

0

Type

R

Reset

Name

RST Value

Function

Not Used

000000: 128 mA

1

R

2

R

3

R

4

R

5

R

6

R

7

RW

R

POR, TR_OFF

IINLIM_0

IINLIM_1

IINLIM_2

IINLIM_3

IINLIM_4

IINLIM_5

011010

000001 : 128 mA (Lower Clamp)

111111 : 8064 mA

8

9

Step : 128 mA

10

11

12

13

14

15

Not Used

R

ChargeOption3 Register − Memory Location : 40h

Bit

Type

Reset

Name

RST Value

Function

VSYS offset selection:

0

RW

POR, TR_OFF

SYSOFF_SEL

0

0 : 384 mV

1 : 256 mV

1

2

3

RW

POR, TR_OFF

DRP_SEL[0]

DRP_SEL[1]

BATRMV_SEL

10

0

VDROOP threshold selection:

00 : 97% Relative to V

01 : 5.6 V

SYSMIN

10 : 5.8 V

11 : 6 V

Battery removal threshold selection:

0 : 2.85 V

1 : 1.6 V

4

5

R

Not Used

6

7

8

9

10

11

12

13

14

15

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14

NCP1871

ManufacturerID Register − Memory Location : FEh

Bit

0

Type

R

Reset

Name

MAN_ID[15:0]

RST Value

Function

0

1

R

2

R

3

R

4

R

5

R

6

R

7

R

8

R

9

R

10

11

12

13

14

15

R

DeviceID Register − Memory Location : FFh

RST Value

Bit

0

Type

R

Reset

Name

DEV_ID[15:0]

Function

0

1

R

2

R

3

R

4

R

5

R

6

R

7

R

8

R

9

R

10

11

12

13

14

15

R

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15

NCP1871

FUNCTIONAL DESCRIPTION

Overview

The NCP1871 is part of On Semiconductor’s growing

switching battery charger family for wireless and mobile

computing. The NCP1871 is a NVDC switching battery

charger with characteristics that makes it perfectly suited for

2−stacked battery cell applications such as ultrabooks or

tablets.

The NCP1871 is designed around a full NMOS DC to DC

controller that brings down the high voltage charger adapter

voltage to a regulated system supply that is in the same range

as the battery pack voltage. This limits the variation on the

system supply voltage, hence the name Narrow Voltage DC

(NVDC), and improves efficiency of the core converters.

The device includes a voltage droop monitor, charger

adapter validation and blocking as well as an intelligent

battery connection control. The adapter current, charge

current and system current are closely monitored and an

image is provided to the host. The NCP1871 is fully

programmable through an I C compatible SMBus interface.

In below figure, the block diagram of the NCP1871 in its

typical application is shown.

2

ACFET

RBFET

HSS

RAC

AC/DC

2.2uH

10uF

47uF

100nF

VIN

RBDRV

ACSP

ACSN

HSDRV

SW

CBOOT

LSDRV

Input FET

Control

Output

Stage

Drivers

Adapter Current

& Power Sense

LSS

VSEL

Adapter

Detection &

Cell Select

VINOK

SDA

DC−DC

Controller

BCSP

BCSN

SMBus

SCL

Host

Battery Current

& Power Sense

RBC

P_AC

P_BC

Charger

Control

Application

PRHOTB

PMO

Precharge

Control

Power and

Droop Monitor

BATDRV

BATFET

Battery FET

Control

VIN VBAT

VBAT

TS

VCORE

GND

NCP1871 NVDC

Battery Charger

Core Supply

2.2uF

10uF

Figure 5. Functional Block Diagram

The charger adapter is connected to the application

through a reverse blocking FET that avoids the leakage from

the battery to input. The FET is made conducting when a

valid charger is detected. At the same time a signal is

generated to inform the host. Overvoltage detection will

reject high voltage charge sources while protecting the

application by blocking the high side FET of the DC to DC

converter.

The adapter current is measured by means of a low

impedance sense resistor. This information is used by the

DC to DC converter to limit the average input current.

Optionally, a second FET can be placed back−to−back in

series with the reverse blocking FET to provide additional

isolation towards the application.

input current as well as the battery charge current. The latter

is measured by means of a low impedance sense resistor.

The battery pack is connected to the system through a low

impedance NMOS. This battery FET is opened in case the

battery is depleted while the DC to DC directly supplies the

application using the system voltage as its feedback.

When charging, the battery FET is closed and the charge

current is monitored. The battery voltage is used as the

feedback voltage for the DC to DC.

When the battery is fully charged to End of Charge state,

the battery FET is opened to preserve its charge but will

assist the system in case it draws more peak power than the

charge adapter can deliver.

The DC to DC converter runs in fixed frequency PWM

mode with pulse skipping capabilities. To reduce EMI

issues, the switching frequency is selectable and a frequency

The DC to DC converter supplies both the application and

charges the battery pack. It regulates its output voltage, the

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16

NCP1871

CORE

spreading feature can be enabled which can reduce peak

The IC core is supplied from a locally generated VCORE.

amplitude of the EMI energy by 10 dB. Soft start of both

output voltage and output current moderate the inrush

current.

The DC to DC converter uses external NMOS switches to

handle the high currents involved. the NCP1871 has the

capability to deliver up to 8 A. Though optimized for

2−stacked cell battery packs the NCP1871 also supports 3

and 4−stacked cell batteries.

Additional features include a voltage drop monitor that

can supervise critical system voltage, a learn mode that

allows to cycle a battery pack to re−initiate the battery pack’s

fuel gauge, and a system power monitor providing a true

analog image of the system power to the host.

The VCORE is a regulated supply that automatically takes

the highest of the AC adapter input VIN and the battery

connection VBAT as its input. The core includes a bandgap

and generates all necessary references for the circuit.

VCORE requires a bypass capacitor.

The core operates in two distinct modes: Off and Active.

In Off mode only imprecise detectors are active monitoring

the VIN pin and SMBus activity while keeping the battery

pack connected to the system. All other circuitries are

disabled. When a VIN or SMBus activity is detected, the

core transitions to the active mode where the entire core is

active including the precise bandgap and clocking. In active

mode the different functions of the IC can be enabled such

as the DCDC converter or power monitors.

The NCP1871 is controllable through a SMBus interface

2

that is also compatible with a 400 kHz I C control. A

The core does not operate for voltages below the under

sideband interrupt signal informs the system of any event

occurring. The bus allows reading out the device status as

well as programming the different voltage and current levels

and operating modes. The NCP1871 comes in a small

3.5 x 3.5 mm QFN−20 package at 0.5 mm pitch.

voltage lockout threshold (V

) and all internal circuitry,

UVLO

both analog and digital, is held in reset.

Charge Profile

VIN

VBAT

VSYS

ISYS

IBAT

IIN

Figure 6. Typical Charge Profile

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17

NCP1871

Pre Charge

the battery will supplement the remainder of the current to

avoid further drop. Once the system current is reduced

below the adapter current, the system voltage will again rise

above the battery voltage and the FET is opened. The battery

will not get recharged in the process as long as the charger

is not re−enabled through SMBus.

In case of a depleted battery, attaching a valid charger will

enable the DC to DC and the output voltage will be raised to

VCHG. The feedback of the DC to DC converter is taken

from BCSP. The battery FET will be used in a linear mode

to precharge the battery pack at a current IPRE. Once the

battery voltage reaches the minimum system operating

voltage VSYSMIN, the battery FET is slowly turned on and

the feedback is now taken from VBAT. Note that VSYSMIN

is to be programmed to a value lower than VCHG.

When precharging the battery, the voltage at BCSP is

permanently monitored. When the output drops towards the

VSYSMIN level, the precharge current is reduced to zero in

an analog fashion starting with BCSP being VPRERED

above the VSYSMIN level. The precharge current will drop

to zero immediately if BCSP drops across VPRESTOP

above the VSYSMIN level. The above described precharge

behavior is the default. By opting for a LDO_MODE option,

the precharge phase will be skipped. This should only be

done if the battery pack can handle a safe precharge on its

own.

DCDC Converter

The DC to DC converter uses external NMOS pass

devices for both the low side and the high side switches. To

drive the gate of the high side switch at HSDRV, a bootstrap

capacitor is used that is connected between SW and CBOOT.

This capacitor is precharged from the VCORE reference.

The gate of the low side switch is directly driven at LSDRV.

Not the drain of the high side switch, but the hot side of the

sense resistor should be considered as the input of the

converter and therefore a capacitor has to be placed at ACSP.

To avoid too high ripple in the application, the capacitor is

to be grounded to the source of the low side switch before

connecting to the system ground.

The output voltage of the DC to DC converter is regulated

to the level VCHG as set in the ChargeVoltage register.

Depending on the state of the battery FET the voltage at pin

BCSP (FET open) or the voltage at pin VBAT (FET closed)

is taken as the feedback voltage. The latter is done to avoid

any early charge current reduction due to the IR drop

between BCSP and VBAT.

Apart from the output voltage regulation, the DC to DC

converter control loop will also limit the amount of input

power from the AC adapter and the amount of current

provided to the battery. In other words, the DC to DC

converter will only be at the set output voltage if the current

limits are not hit. The input current limit is set in the

InputCurrent register, the charge current in the

ChargeCurrent register. Note that when the input current

limit is reached, the output voltage will drop automatically

thus reducing the amount of current provided to the battery.

In other words, priority is given to the system current over

the battery charge current.

When enabled, the reference for the DC to DC output

voltage is smoothly ramped. Once the output voltage ramp

has finished, the charge current is ramped up. When

reprogramming an established output voltage to a higher or

lower value, the voltage ramp is also applied. The

combination of these mechanisms limits the peak inrush

current at startup and during the transitions after SMBus

programming.

Full Charge

In case of an already connected battery, attaching a valid

charger will enable the DC to DC with VBAT as the

feedback voltage. If at the end of the voltage ramp the VBAT

is greater than VSYSMIN, the battery FET remains closed

and full charging is engaged. For VBAT below the

VSYSMIN however, the battery FET is automatically made

non−conducting, the pin BCSP taken as the feedback, and

the battery pack pre−charged as described above. By this

overlapped approach the system will remain correctly

supplied when opening the battery FET.

End of Charge

Once the battery is fully charged the battery FET is made

non−conducting. This avoids wear and tear of the battery

cells and enhances the battery pack’s lifetime. The fully

charged state is determined by the battery pack’s fuel gauge.

Through SMBus the battery charger is then disabled. This

does not mean that the DC to DC converter is disabled, just

that the battery is no longer charged. Normally, it was still

being charged with a small current before disabling charging

for a full battery, so after the battery FET is opened, the

system voltage is slightly above the battery voltage.

The end of charge detection by the charger is not the

preferred method; termination by the fuel gauge is preferred

at large due to the correlation between end of charge and

100% battery capacity. However, the end of charge detection

may be helpful as an additional means of protection. The end

of charge detection should therefore be set low. Upon an end

of charge detection an interrupt is generated.

Once enabled, the converter operates in a fixed frequency

PWM mode and will pulse skip automatically when needed.

The switching frequency is selectable over a small range, it

is however not advised to apply ‘on the fly’ changes but to

use a device instance with a different default value.

During specific mode, the power consumption of the

whole system is intended to be very low. An Eco mode can

Supplement Mode

With the FET non−conducting, the system current may

exceed the power rating of the wall charger. As a result the

system voltage will drop. When a significant BCSP drop of

VDRCON is detected, the battery FET will be turned on and

2

be enabled through I C, (bit ECO_MODE, register

ChargeOption2) which increases the efficiency at very light

load (10−20 mA).

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NCP1871

This particular skip mode is active when the input current

is lower than 100 mA. If so, the T is extended to

reduce switching activity and frequency as a consequence.

The buck also regulates in asynchronous mode. As soon as

ECO_MODE is set to ‘0’ whatever the input current is, the

eco mode is disabled.

The DC to DC converter switches at fairly significant

current levels which could cause conducted and radiated

EMI issues. A frequency spreading option can be enabled to

reduce the side−effects of this. By varying the switching

frequency at a constant low rate (i.e. a modulation with a

triangular waveform), the peak amplitude of the EMI energy

in the output spectrum can be reduced by about 10 dB. Note

that the amount of power itself is not reduced, just its

allocation over the frequency band.

When pulse skipping, the current in the inductor will fall

to zero for each cycle (discontinuous operation). At that

point both the low side and high side switches are

non−conducting, and the SW node will be ringing caused by

the LC resonance created on the switch node. In absence of

prolonged switching activity, the bootstrap capacitor will

discharge. In order to maintain the capacitor charge, the low

side FET will be turned on periodically so that the bootstrap

capacitor can be recharged again to VCORE level.

To protect the DC to DC converter output transistors as

well as the inductor, a peak current limiter will limit the

cycle to cycle peak current. It uses the voltage drop over the

input current sense resistor to monitor the peak current. A

flag bit is set to inform the host about the event but the DC

to DC converter is not automatically disabled.

ONMIN

Current and Power Monitoring

The current and power monitoring block consists of an

analog output signal reflecting the amount of power taken by

the system and an open drain output signaling the host that

excessive power is drawn by the system.

The below diagram depicts the power monitoring

functionality.

IPAC = KAC ( AAC*VAC * GAC*VIAC )

IPBC = KBC ( ABC*VBC * GBC*VIBC )

ACSP

A_AC

BCSN

A_BC

VBC

VAC

KBC

KAC

IPAC

IPBC

G_AC

G_BC

VIBC

VIAC

ACSN

BCSP

IPMO = IPAC + IPBC

RPMO

Figure 7. Power Monitoring Diagram

In order to inform the Host about the amount of power

used by the system, an image of the power taken from the

charger input and the battery pack is provided at the power

monitor output PMO. PMO does take into account the power

that is sourced to the battery during the charge cycle. Based

on this information, the host can determine if it is reaching

the maximum power level it is allowed to take from either

source.

to the PMO output. The current measurement signal is also

used by the DC to DC converter to limit the input currents

and by the adapter over current protection circuitry.

The current flowing out of and into the battery is sensed

through the sense resistor R connected between the pins

BC

BCSP and BCSN. The measurement is low pass filtered to

remove any current spikes due to the transient load response

of the system. The resulting signal is multiplied with the

battery voltage at BCSN and amplified to the PMO output.

The current measurement signal is also used by the DC to

DC converter to control the charge current. The battery

power sense circuitry can be enabled in both charging and

non charging modes.

The adapter current is sensed through the sense resistor

R

AC

connected between the pins ACSP and ACSN. The

measurement is low pass filtered to remove the current

ripple due to the DC to DC activity. The resulting signal is

multiplied with the adapter voltage at ACSP and amplified

www.onsemi.com

19

NCP1871

VOLTAGE DROOP MONITOR

The below diagram depicts the voltage monitoring functionality.

BCSP

BAT_RMV

VDRPREF

VLOBAT

INSYS

PRHOTB

PRHOTB_DRV

IINLIM_DISABLE

&

1 shot Pulse

Stretcher (TPS ms )

CPEXIT_EN

Figure 8. Critical Voltage Monitor Diagram

Input Current Limitation

The critical system voltage node, is connected to BCSP

and is monitored for a sudden drop due to high loading

conditions. A comparator with a programmable threshold is

used for this. This comparator is enable when bit

VDROOP_EN is set to 1 (register ChargeOption). For

additional adjustment, the detection level can be adjusted

with VDRP_SEL bit of ChargeOption3 register. This

comparator can be disabled under low battery conditions to

avoid false triggering (bits VLOBAT_REG, register

ChargeOption). The overall system can be enabled in both

charging and non charging modes. Note that under low

battery conditions the processor peak current will be

automatically reduced by the system so that critical voltage

droops are avoided.

The output of the drop monitor is fed into a pulse stretcher

that will ensure the PRHOTB pin will be pulled low for a

guaranteed minimum period TPS which will reduce the

processor speed (PROCHOT# pin) and thus the power

consumed. BAT_RMV and INSYS signal leads to a

PRHOTB generation as well.

Apart from the output voltage regulation, the DC to DC

converter control loop will also limit the amount of input

power from the AC adapter and the amount of current

provided to the battery. In other words, the DC to DC

converter will only be at the set output voltage if the current

limits are not hit. The input current limit is set in the

InputCurrent register. Note that when the input current limit

is reached, the output voltage will drop thus automatically

reducing the amount of current provided to the battery.

Battery FET

The battery pack is connected to the system voltage rail

through the NMOS battery FET (BATFET), driven from

BATDRV. In order to support all operating modes of the

application, the battery FET can be operated in three states;

fully conducting, non−conducting and linear mode.

When the application is in off mode and no charger is

attached, the system voltage is maintained by the battery.

The BATFET is fully conducting by BATDRV being driven

high through a charge pump to VBAT plus VPUMP. The

charge pump features a very low bias current when

maintaining BATDRV high. This current is accounted for in

the core quiescent current. When the application is operating

without any charger attached, the battery FET is by default

fully conducting when the VBAT is greater than the

undervoltage threshold UVLO while non−conducting for

lower voltages (fully depleted battery).

Watchdog Timer Description

The battery charging cycle is under control of the host. It

may happen that the host is too busy to survey the charger or

that the system is stuck. As a safety measure therefore a

2

watchdog timer is started after each I C write in charge

current or/and voltage setting registers during active charge

states. When the watchdog timer is enabled, the charge will

be suspended if IC does not receive any write charge voltage

or write charge current command within the watchdog time

period. This timer can be set or disabled through SMBus

registers.

www.onsemi.com

20

NCP1871

Adapter Detection and Removal

VINOK Output

The AC adapter is connected to the input VIN which is

permanently monitored by a set of comparators. A first

imprecise low current comparator will detect the presence of

an input voltage greater than VINDET. This comparator is

always enabled even when the core of the circuit is in off

mode. Once detected, the more precise input voltage

detectors are enabled.

The precise voltage detectors will validate if the applied

charger is in the proper input range bounded by VINLO (on

VSEL pin) and VINOV(on VIN pin) or VINMINOK

depending on VINOK_SEL (see SMBUS Registers Map).

To guarantee a robust detection, debounce timers are added

to the VINLO detection. The VINOV acts as an overvoltage

protection that rejects too high voltage chargers in order to

avoid damage to the application.

When the input voltage is valid (VSEL > VINLO and VIN

< VINOV) or (VINMINOK < VIN < VINOV) depending on

VINOK_SEL bit (register MinSysVoltage), the open drain

VINOK pin is released and pulled high by the external pull

up resistor thus signaling the host that a valid supply is

attached. When becoming invalid the opposite applies.

The SMBus doesn’t has a slave interrupt feature. To

inform the host about an event a sideband signal is to be used.

On the NCP1871 the VINOK pin flags to the host when a

valid charger is attached. Given the non critical timing of the

VINOK signal for this use case, an interrupt is signaled as

a short ‘not VINOK’ pulse. The short period of the pulse

allows distinguishing an interrupt from a charger removal.

An interrupt can only be generated when a valid charger is

attached. The interrupt feature can be enabled and disabled

through the control bus (Bit FAULT_MSK and

STATUS_MSK, Register ChargeOption2). Register

Interrupt inform the system about the nature of interruption.

Flagged on

VINOK

Associated

Mask Bit

2

I C Signal

Nature

Description

EOC_INT

RC Dual Edge

Yes

STATUS_MSK

0: Not in End of Charge state

1: End of charge state

PRE_INT

RC Dual Edge

Yes

STATUS_MSK

0: Not in Precharge State

1: Precharge state

LEARNB_INT

WDOG_INT

IPEAK_INT

INOVP_INT

RC Dual Edge

RC Single Edge

RC Dual Edge

Yes

STATUS_MSK

FAULT_MSK

1: Enter/Exit Learn Mode

1: Wd timer expired

1: IPKMAX reached.

0: INOVP = 0

1: INOVP = 1

BUCK_OVP_INT

RC Dual Edge

Yes

FAULT_MSK

0: BUCKOV = 0

1: BUCKOV = 1

SYSOV_INT

HW_RST_INT

BAT_DIS_INT

INSHORT_INT

BAT_RMV_INT

Write 1 to Clear

RC Single Edge

No Clear

Yes

No

FAULT_MSK

NA

1: SYSOV

1: HW_RST state and HW_RST=1

1: HW_RST state and BAT_DIS=1

1: INSHORT = 1

No

NA

Yes

FAULT_MSK

STATUS_MSK

RC Single Edge

0: Battery is present

1: Battery is removed

Battery Removal

Event occurs

A battery removal pin TS can be used to monitor battery

presence. This allows the charger to anticipate a potential

voltage drop of the system rail in case of battery removal. If

a battery is suddenly removed, a PRHOTB is immediately

generated, informing the system that the battery is no longer

available for supplement. If this event appears during learn

mode, the buck is immediately forced to VCHG. The

PRHOTB length is 10 ms allowing enough time for the

system to take into account this event, and adapt its power

management accordingly.

200us

VINOK

Valid Adapter Attached

Figure 9. Interrupt Signaling

www.onsemi.com

21

NCP1871

VSYSMIN Default Value Detection

limited to the capacitor at ACSP. It is therefore thought that

a back to back configuration of a reverse blocking FET

RBFET with an input FET ACFET is not necessarily

required, By using a back to back FET configuration

however, the charger can be isolated from the application

thus providing additional protection against system short

circuits and overvoltages. A back to back FET combination

also allows connecting some additional charging related

circuitry just right after the input FETs while taking

advantage of the overvoltage protection.

When a system short circuit occurs that exceeds the input

and peak to peak current limits, the RBDRV pin will be made

low and the charger will have to be removed to unlatch this

condition. When exceeding the system overvoltage

threshold VSYSOV, SYSOV_INT bit will be triggered as

system over voltage, need to Write 1 to Clear this bit and

release this protection.

User can select the VSYSMIN default value thanks to an

external resistor RCELL. The resistance should be put in

series with VSEL pin as follows:

2 /3 Cells

configuration

3 /4 Cells

configuration

V_IN

R 2

V_IN

R 2

V_SEL

RCELL

R 1

For effective isolation the ACFET will have to be added

to create a back to back configuration with the RBFET. Both

mechanisms add additional safety in case the DC to DC

converter does not manage to limit the voltage or current due

to for instance a shorted high side switch or other

malfunctioning.

Figure 10. Resistor Network for CELL Detection

RCELL must be 220 kW if 3/4 cells config selected. R1 is

also fixed to 22 kW, and R2 is used to select VINOK

threshold. The following table illustrates VINOK versus R2.

Learn Mode

The NCP1871 provides a special battery learning cycle

that helps to calibrate the battery fuel gauge. This cycle is

performed while an adapter is attached. Upon the SMBus

LEARN command the DC to DC converter is immediately

forced to VSYSMIN+VSYSOFF, so the application would

be supplied from the battery therefore discharging the latter.

When LEARN is finished (normally by fuel gauge) or

battery is removed, the charge can resume normally.

Constant Power Exit

In case a PRHOTB generation is not sufficient to stop the

voltage drop during a very strong load transient, some AC

adapters are designed to provide more power than their

nominal value. In that case, the charger must disable the

input current limit to allow full power to flow through it.

This mode is enabled thanks to CPEXIT_EN bit in register

ChargeOption2. If this bit is set to 1, the input current limit

will immediately be disabled during PRHOTB generation.

As soon as PRHOTB disappears, the input current limit is

enabled again.

Figure 11. VINOK versus R2 Table

2

This function can be defeated through I C (bit

N_CELL_EN, register MinSysVoltage).

Upfront Protection

To avoid the battery voltage supplying the AC adapter

input pin, a reverse blocking element is required. One could

use a Schottky diode but given the high current levels in play,

the dissipation would be excessively high and overall

efficiency degraded. This is resolved by using a reverse

blocking FET (RBFET) function that simulates an ideal

diode. The RBFET is an NMOS type and its gate driven from

RBDRV. An internal charge pump will provide a RBDRV

drive voltage of VIN plus VCORE.

When attaching a charger, the DC to DC converter is not

yet operational and the system is isolated from the charger

by the DC to DC converter high side switch. Therefore, upon

attachment the capacitive loading seen from the battery

charger through the body diode of the RBFET remains

AC Adapter Overvoltage Protection

In case of an overvoltage, the DC to DC converter is

immediately disabled and the RBDRV pin made low, so

a−synchronously with the core logic. The converter and

RBDRV are enabled again when the overvoltage condition

disappears. The converter is definitely disabled by the core

logic and the charger rejected when the overvoltage

condition persists. When connecting an AC adapter,

transient voltages greater than the maximum ratings of the

IC can occur. Appropriate filtering will have to be placed

upfront to stay below these levels.

www.onsemi.com

22

NCP1871

Hard System Reset

For SMBus the SDA and SCL logic low and high levels

are defined as absolute voltages, where they are relative to

the supply for I C. Although specification wise this may

lead to conflicting situations, in practice this does not cause

an issue when operating from 3 V and 5 V supply rails. The

interface of the NCP1871 uses absolute levels and is

supplied by the bus lines itself.

A hard system reset is initiated after the user has pressed

the power button for a long period, usually 8 seconds. The

keyboard controller can then through SMBus program the

system reset bit after which the BATDRV pin is temporarily

made low to GND and the system reset bit cleared. To totally

isolate the battery pack from application, back to back

configuration of BATFET will be needed. Upon HW_RST

bit is set to 1, a RST_TMR timer is launched and BATFETs

are made non conducting when this timer is expired. This

RST_TMR timer ensures the system can turn off correctly

after HW_RST bit is set 1. The Timer also determines the

BATFET OFF duration.

2

For SMBus the clock frequency is within 10 kHz and

2

100 kHz where I C allows for 0 Hz while in the widespread

fast mode it can run up to 400 kHz.

The minimum clock frequency for SMBus allows for

implementing a bus timeout mechanism. When the master

keeps the bus clock low the slave will release the data lines

2

and the transaction is aborted (equivalent to an I C STOP

Battery Disconnect

command).

In web tablets and ultrabooks, the battery pack is

embedded and is shipped while being partially charged. To

avoid the battery getting slowly discharged by the

application while being on the shelf, the battery pack is

totally isolated from the application by adding a second

MOS in a back to back configuration. By setting the battery

disconnect bit through SMBus, after a delay of RST_TMR,

the BATDRV pin will be made low to GND when the adapter

is removed and will be kept low as long as the battery power

remains available. To exit this state a valid charger will have

to be inserted which will reconnect the battery pack and reset

the disconnect bit.

Limiting the clock frequency of the interface to the

SMBus standard could lead to conflicts on an I C bus. The

2

NCP1871 therefore supports up to 400 kHz. This has no side

effects on the SMBus operation itself. Note that the bus

clocking is independent from the core logic clocking.

For SMBus a slave should always ACK its device address

2

but is allowed to NACK after any of the data bytes. On I C

one is allowed to NACK the address. The NCP1871 will

actually never respond with a NACK and therefore always

provide an ACK.

A smart battery charger on a SMBus has an imposed bus

address of 0001001b. Optionally, the NCP1871 includes a

2

different I C address (available upon request).

Serial Interface (SMBUS)

The smart battery charger protocol imposes a word (low

byte, high byte) write/read protocol with one address per 2

The device is widely programmable through the SMBus

2

interface. The SMBus is based on the I C interface with

2

bytes. In I C, the single byte write/read is more common

some exceptions. These exceptions are documented in the

SMBus specification 2.0 that is available at smbus.org. The

where each byte of data has its own individual address.

2

However, most I C masters can perform an auto increment

I C specification is available from the NXP website or

to perform a 2 bytes consecutive write/read starting with the

low byte, also see the appendix. The diagram below

summarizes this.

through i2c−bus.org.

The SMBus implementation on the NVDC charger is I C

2

friendly allowing it to be used on non SMBus applications.

The most noticeable differences between the two standards

to the NVDC charger are listed below.

www.onsemi.com

23

NCP1871

Application Information

Typical Application

Negative Protection

circuitry

QNP

R1

R2

Damping

Network

QAC

QRB

RIN

AC

ADAPTOR

L_X

QLS

RAC

SYSTEM

LOAD

QHS

C2

C1

CBOOT

COUT1

COUT2

DF

CIN

CAC

RI1

R3

D1

RCELL

RBDRV

ACSP ACSN

CBOOT LSDRV BCSP

SW

VIN

HSDRV

VDD

10k

VSEL

RBC

RI2

BCSN

BATDRV

VINOK

SDA

HOST

NCP1871

QBAT

SCL

VBAT

RTS

PRHOTB

PMO

CBAT

TS

BATTERY

PACK

VCORE

RPMO

GND

CCORE

+5V

Figure 12. Additional Circuitry for Negative Protection

Table 5. BILL OF MATERIAL

Reference

Description

Decoupling input capacitor

Damping Resistor

Manufacturer / Part Number

Value

C

R

4.7 mF / 50 V

2 W / 0.5 W

10 mF / 50 V

100 nF / 25 V

2.2 mF / 6.3 V

47 mF / 25 V

10 mF / 50 V

20 V / 1 A

IN

C

Decoupling Switcher capacitor

Bootstrap capacitor

AC

C

BOOT

C

CORE

Decoupling core supply capacitor

Decoupling system capacitor

Decoupling battery capacitor

Clamping Schottky Diode

Switcher Inductor

C

OUT1, OUT2

C

BAT

D

MBRM120E / ONSEMI

F

X

L

IHLP−2525CZ−01 / VISHAY

2.2 mH / 8 A

10 mW / 1 W

10 mW / 30 V

1 kW / 0.1 W

R

, R

Current sense resistor

AC

BC

Q

, Q , Q , Q , Q

BAT

Power MOSFET N−channel

Battery Hotplug Current Limit Resistor

Battery Removal Pull Up resistor

NTTFS4C10N / ONSEMI

AC

RB

HS

LS

R

TS

UP

R

100 kW / 0.1 W

3.01 MW / 0.25 W

1 MW / 0.25 W

4 kW / 0.5 W

33 kW / 0.1 W

2.2 nF / 50 V

0.1 mF / 50 V

7.5 W / 60 V

R

Q

Reverse protection biasing resistor

1

2

3

RB

R

RB

R

Reverse protection resistor

BDRV

R

Power Monitor Resistor

PMO

C

Reverse protection capacitor

Reverse protection NMOS

Schottky Barrier Rectifier

1

2

Q

2N7002L / ONSEMI

NP

D

MBRA340T3G / ONSEMI

3 A / 40 V

1

R , R

Minimum input voltage valid resistor

Number of cell selection resistor

See VSYSMIN Default

Value Detection

I1

I2

R

CELL

www.onsemi.com

24

NCP1871

Input Damping Network

charger circuitry by blocking the negative voltage and R3

limits the current flowing into the ESD protection circuitry

A Damping network is recommended in order to avoid

voltage ringing on the input. On the following example (see

Figure 13) with a 1 mH / 0.1 W cable, the maximum input

voltage is higher than 30 V and can damage the application.

In Figure 14, a damping network 1 mF / 2 W is added so the

input voltage is smoothed to 22−24 V maximum.

thus avoiding damage. C1 and C2 ensure the V of Q

GS

RB

and Q remains 0 V during negative hot plug.

AC

Components Selection

Inductor Selection

Inductor electrical selection depends on maximum

current, frequency and duty cycle. The saturation and DC

current are defined by:

I_SAT+ I_CHG) 0.5 I_RIPPLE

The inductor ripple current depends on input voltage

(V ), duty cycle (D = V

/V ), switching frequency

IN

OUT

IN

(F

) and inductance (L ):

X

SWCHG

ǒ

Ǔ

V_IN D (1 * D)

I_RIPPLE

+

ǒ_F

Ǔ

L_X

SWCHG

The maximum inductor ripple current happens for

D = 0.5

Figure 13. Hot Plug Behavior without Damping

Network

I

= V / (4 x F

x L ) So maximum current

RIPPLE

IN

SWCHG X

is given by I

= I

+ 0.5 x V / (4 x F x L )

SWCHG X

SAT

CHG

IN

Please note that the NCP1871 switching frequency is

selectable.

Power MOSFETs Selection

NCP1871 is designed to drive N−Chanel MOSFET with

5 V gate drive voltage and an operating voltage up to 24 V.

Due to voltage transient, a 30 V N−MOSFET is preferred.

Q

, Q , Q , Q and Q

are all N−Chanel MOSFET

AC RB HS LS

BAT

and can be identical. It is also recommended to select a very

low RDSON MOSFET (10 mW typically for V = 4.5 V)

GS

with a total gate charge around 10 nC typically. NTTFS4C10N

from ON SEMICONDUCTOR is the perfect fit with

NCP1871.

For Q , one more thing needs mention: since BATDRV

BAT

Figure 14. Hot Plug Behavior with Damping Network

would be pulled low to GND during shipping mode or hard

system reset action, which means VGS at this time would be

(–VBAT), the NFET needs to be selected with enough VGS

rating especially for 3 or 4 cells application.

Input Negative Protection

A negative voltage protection on input is defined by the

negative protection circuitry (see Figure 12). In normal

operation, Q is off (VGS < 0 V). D1 is conducting and R1,

NP

PCB Layout Recommendation

C1 and C2 have no continuous effect. When adapter voltage

Proper layout of the components is recommended in order

to minimize high frequency current path loop and to prevent

high frequency resonant problems and electrical magnetic

field radiation.

is reversed, Q

V

is positive causing Q to turn on. As

NP GS NP

a consequence, the source and gate node of Q is shorted

RB

so Q is off and the battery side circuitry is protected by the

RB

body diode of Q . At the same time, D1 is protecting input

RB

www.onsemi.com

25

NCP1871

GND PLANE

CIN

RIN

COUT

CAC

QLS

L_X

AC

ADAPTOR

RAC

RBC

QAC

VIN

QRB

CBOOT

QBAT

QHS

SYSTEM

LOAD

BATTERY

PACK

LSDRV

RBDRV

ACSP ACSN HSDRV CBOOT SW

BCSP

SENSE

BCSN

BATDRV

VBAT

DC POWER

AC POWER

NCP1871

TS

VCORE

SUPPLY

& DRIVER

CCORE

GND

Figure 15. Typical Layout Recommendation

It is crucial to take the following rules into account.

• C

Capacitor must be placed as close as possible to

the IC and routed on the same PCB layer as the IC. The

connection to GND (expose pad) should be short and

CORE

• The switching loop (AC power track) composed by

C

, R , Q , Q , L , C

must be as short as

AC AC

HS

LS

X

OUT

possible and placed on the same layer of PCB. This

connected to C

cold node with a unique track.

OUT

track must be isolated from GND plane, only C

OUT

• Use Kelvin connection for RAC and RBC sensing and

do not route these sense leads through a high di/dt or

dv/dt path.

cold node is connected to the GND plane. This track

must be large enough to reduce impedance of track

(8 A typ).

• Supply and driver track must be large enough (1 A

max). LSDRV and HSDRV are switching nodes; track

must be shortened to reduce parasitic inductance.

• The impedance of DC power track composed by Q

,

AC

Q

, R and Q

must be as low as possible and

RB BC

BAT

placed on the same PCB layer as the AC power track.

This track also must be large enough (8 A typ).

www.onsemi.com

26

NCP1871

PACKAGE DIMENSIONS

QFN20 3.5x3.5, 0.5P

CASE 485CP

ISSUE O

NOTES:

B

E

A

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.30 MM

FROM TERMINAL TIP.

D

L

PIN ONE

REFERENCE

L1

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

MILLIMETERS

DIM MIN

MAX

1.00

0.05

A

A1

A3

b

0.80

−−−

0.20 REF

0.10

C

0.20

0.30

A3

D

D2

E

3.50 BSC

0.10

C

2.10

2.30

EXPOSED Cu

MOLD CMPD

TOP VIEW

3.50 BSC

E2

e

K

L

L1

2.10

0.50 BSC

0.30 REF

0.25

0.00

2.30

A

0.05

C

A1

0.45

0.15

A3

DETAIL B

ALTERNATE

CONSTRUCTIONS

0.05

DETAIL B

NOTE 4

A1

SEATING

PLANE

C

SIDE VIEW

RECOMMENDED

MOUNTING FOOTPRINT

0.10 C A B

DETAIL A

3.80

2.36

D2

K

20X

0.57

6

0.10 C A B

11

20X

L

1

E2

2.36

3.80

1

16

20X

b

PACKAGE

OUTLINE

e

20X

0.10

C A

B

0.35

0.50

PITCH

0.05

C

NOTE 3

BOTTOM VIEW

DIMENSIONS: MILLIMETERS

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

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For additional information, please contact your local

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NCP1871/D

www.onsemi.com

27


型号：	NCP1871
厂家：	ONSEMI
描述：	Narrow Voltage DC Battery Charger 电池
文件：	总27页 (文件大小：386K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP1871 [ONSEMI]

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