NCP1655ADR2G [ONSEMI]
Multi-Mode (CrM-CCM) Power Factor Correction Controller, Brown Out Protection;
| 型号： | NCP1655ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Multi-Mode (CrM-CCM) Power Factor Correction Controller, Brown Out Protection |
| 文件： | 总24页 (文件大小：796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Power Factor Controller for
Compact and Robust
Multimode Pre-Converters
NCP1655
The NCP1655 is an innovative multimode power factor controller.
The circuit naturally transitions from one operation mode to another
depending the switching period duration so that the efficiency is
optimized over the line/load range. In very−light−load conditions, the
circuit can enter the soft−SKIP mode for minimized losses.
Housed in a SO−9 package, the circuit further incorporates the
features necessary for robust and compact PFC stages, with few
external components.
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10
1
SOIC−9 NB
CASE 751BP
MARKING DIAGRAM
Multimode Operation
• Multimode Operation for Optimized Operation over the Line/Load
10
Range:
NCP1655X
ALYW
♦ Continuous Conduction Mode (CCM) in Heavy−Load Conditions
♦ Frequency−Clamped Critical Conduction Mode (FCCrM) in
Medium− and Light−Load Conditions
G
♦ FCCrM: Critical Conduction Mode (CrM) when the CrM
Switching Frequency is Lower than 130 kHz, Discontinuous
Conduction Mode (DCM) at 130 kHz Otherwise
♦ DCM Frequency Reduction in Light Load Conditions
♦ Minimum DCM Frequency Forced above 25 kHz
♦ Valley Turn−On in FCCrM
1
NCP1655X = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
♦ Soft−SKIP Mode in Very Light Load Conditions
• Near−Unity Power Factor in All Modes (Except Soft−SKIP Mode)
• Firm Control of the Switching Frequency between 25 kHz and
130 kHz
PIN CONNECTIONS
V
FB
1
2
3
4
5
10
S
General Features
• V High−Voltage Line Sensing Pin: Reduced External Compoments
S
pfcOK
Vm
Count and Minimized Leakage Current Compatible to Most Severe
Standby Specifications (< 30 mA @ 400 V)
8
7
6
Vcc
• Internal Compensation of the Regulation Loop
• Fast Line / Load Transient Compensation (Dynamic Response
CS
Driver
Ground
Enhancer)
• Large V Operating Range (9.5 V to 35 V)
CC
ZCD
• Line Range Detection
• pfcOK Signal For Enabling/Disabling the Downstream Converter
• Jittering for Easing EMI Filtering
ORDERING INFORMATION
See detailed ordering and shipping information on page 22 of
this data sheet.
Safety Features
• Soft− and Fast−Overvoltage Protection
• Brown−Out Detection
• 2−Level Over Current Detection
• Bulk Under−Voltage Detection
• Thermal Shutdown
Typical Applications
• PC Power Supplies
• All Off−Line Appliances Requiring Power
Factor Correction
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
November, 2020 − Rev. 0
NCP1655/D
NCP1655
Table 1.
CCM Switching Frequency
FCCrM Frequency Clamp
NCP1655ADR2G
65 kHz
130 kHz
TYPICAL APPLICATION SCHEMATICS
V
out
V
in
Bypass Diode
Ac line
L
1
.
.
D
1
D
VS
V
out
R
pfcOK
VS
C
pfcOK
R
R
FB2
R
ZCD
V
FB
S
EMI
Filter
10
1
2
V
BIAS
pfcOK
C
FB
FB1
V
M
R
Vcc
pfcOK
8
7
6
3
4
5
CS
DRV
GND
Q
1
ZCD
R
OCP
R
PD
C
bulk
R
M
C
Protecting
Diode
(optional)
M
R
sense
C
ZCD
Figure 1. Typical Application Schematic
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2
NCP1655
PIN FUNCTION DESCRIPTION
Pin No. Pin Name
Function
Description
1
FB
Feedback Pin This pin receives a portion of the PFC output voltage for regulation and the Dynamic Response
Enhancer (DRE) function which drastically speeds−up the loop response when the output voltage
drops below 95.5% of the desired output level. V is also the input signal for the soft− and
FB
fast−overvoltage (OVP) and under−voltage (UVP) comparators. A 250 nA sink current is built−in
to trigger the UVP protection and disable the part if the feedback pin is accidently open.
2
3
pfcOK
PFC OK Pin This pin is grounded until the PFC output has reached its nominal level. It is also grounded if the
NCP1655 detects a major fault like a brown−out situation. A resistor is to be placed between the
pfcOK pin and ground to form a voltage representative of the output voltage which can be used
to enable the downstream converter and provide it with a feedforward signal.
Multiplier
Output
This pin provides a voltage V for duty cycle modulation when the circuit operates in continuous
M
V
M
conduction mode. The external resistor R applied to the V pin, adjusts the maximum power
M
M
which can be delivered by the PFC stage. The device operates in average−current mode if an
external capacitor C is further connected to the pin. Otherwise, it operates in peak−current mode
M
4
5
CS
Current
This pin sources a current I which is proportional to the inductor current. The NCP1655 uses
CS
CS CS
detection, abnormal current detection and overcurrent protection (OCP).
Sense Pin
I
to adjust the PFC duty ratio in CCM operation. I is also used for protection: inrush current
ZCD
Zero Current This pin is designed to monitor a signal from an auxiliary winding and to detect the core reset
Detection
when this voltage drops to zero. This function ensures valley turn−on in discontinuous and critical
conduction modes (DCM and CrM).
6
7
GND
DRV
Ground Pin Connect this pin to the PFC stage ground.
Driver Output The high−current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to
effectively drive high gate charge power MOSFETs.
8
V
CC
IC Supply
Pin
This pin is the positive supply of the IC. The circuit starts to operate when V exceeds 10.5 V
CC
and turns off when V goes below 9.0 V (typical values). After start−up, the operating range is
CC
9.5 V up to 35 V.
9
−
−
Removed for creepage distance.
10
V
S
High Voltage The circuit senses the V pin voltage for line range detection and brownout protections.
S
Pin
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3
NCP1655
INTERNAL CIRCUIT ARCHITECTURE
V
VS
VS
BONOK
OFF
BUV
FB
OFF
BUV
Major Faults
TSD
SKIP2
Management
pfcOK
UVLO
pfcOK and
Skip control
soft−stop
pfcOK_H
UVP
idle_phase
VCC
End_skip_burst
VCC
VDD
pfcOK−H
HL
CCM
Management
SKIP1
fastOVP
idle_phase
SKIP2
reset
UVLO
SoftOVP
soft−SKIP
control
CCM
End_skip_burst
End_idle_phase
pfcOK−H
Regulation, UVP,
softOVP,
fastOVP, DRE,
Soft−Start,
FB
UVP
StaticOVP,
SKIPout and BUV
staticOVP
DRV
clamp
V
REGUL
pfcOK−H
HL
idle_phase
OFF
BUV
Output
Buffer
OUTon
SoftOVP
DRE1
DRV
GND
fastOVP
OCP
DRE
soft−stop
OVS
DT
Internal Ramp
and
multimode
management
Ics
(CCM, CrM, DCM
and soft−SKIP)
V
VS
V
DMG
In−rush
SKIP
BONOK
HL
DRE1
DRE
staticOVP
Line Range Control
ZCDfault
CSfault
CCM
OVP
V
REGUL
Ics
V
M
In−rush
In−rush
OUTon
Current Sense
Block
OCP
OVS
Zero
V
DMG
ZCD
current
detection
and OVP2
CS
DT
CSfault
SKIP1
ZCDfault
Figure 2. Internal Circuit Architecture
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NCP1655
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
V
High Voltage Input Voltage
*0.3 to 700
V
VS(MAX)
V
Maximum Power Supply voltage, V pin, continuous voltage
−0.3 to 35
Internally limited
V
mA
CC(MAX)
CC(MAX)
CC
I
Maximum current for V pin
CC
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
mA
DRV(MAX)
DRV(MAX)
DRV
I
−500, +800
V
Maximum voltage on low voltage pins (except DRV and V pins)
−0.3, 5.5 (Note 2)
−2, +5
V
mA
MAX
MAX
CC
I
Current range for low voltage pins (except DRV and V pins)
CC
R
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
180
°C/W
°C
°C
°C
−
q
J−A
T
150
J(MAX)
T
−40 to +125
J
T
−60 to +150
S
MSL
Moisture Sensitivity Level
1
3.5
1
ESD Capability, HBM model (Notes 3 and 4)
ESD Capability, CDM model (Note 4)
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V otherwise.
DRV
DRV(high)
CC
DRV(high) DRV CC
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages
can be applied if the pin current stays within the −2 mA / 5 mA range.
3. Except V pin
S
4. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22*A114F,
Charged Device Model 1000 V per JEDEC Standard JESD22*C101F
5. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78E.
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max
J
CC
VS
values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted)
J
CC
VS
Symbol
Description
Test Condition
Min
Typ
Max
Unit
SUPPLY CIRCUITS
V
V
Startup Threshold
Minimum Operating Voltage
Hysteresis V – V
CC(off)
V
CC
V
CC
V
CC
V
CC
rising
9.75
8.5
0.5
3.5
10.50
9.0
11.25
9.5
−
V
CC(on)
CC(off)
decreasing
decreasing
decreasing
V
1.5
CC(HYS)
CC(reset)
CC(on)
V
V
level below which the circuit resets
5.0
6.0
CC
Supply Current
V
CC
= 9.6 V, F = 65 kHz
mA
sw
I
I
I
Device Disabled / Fault (no switching)
Device Enabled (switching) / No output load on pin 5
Soft−SKIP Idle Phase
0.80
−
−
1.20
2.20
0.25
1.40
4.00
0.50
CC1
CC2
CC3
GATE DRIVE
T
Output voltage rise−time
Output voltage fall−time
C = 1 nF
−
−
45
30
−
−
ns
ns
R
L
10 − 90% of output signal
T
C = 1 nF
F
L
10 − 90% of output signal
R
Source resistance
−
−
−
−
8
11
7
−
−
−
−
−
W
W
OH
R
Sink resistance
OL
SOURCE
I
Peak source current (Note 6)
Peak sink current (Note 6)
V
V
V
= 0 V
500
800
−
mA
mA
V
DRV
I
= 12 V
SINK
DRV
V
DRV pin level at V close to V
= V
+ 200 mV
DRVlow
CC
CC(off)
CC
CC(off)
10 kW resistor to GND
V
DRV pin level at V = 35 V
R = 33 kW, C = 220 pF
10
12
14
V
DRVhigh
CC
L
L
RAMP
f
CCM switching frequency
60
65
70
kHz
%
CCM
R
Ratio f
over Switching Frequency for CCM
−
112
−
CCM
CCM
detection
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NCP1655
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max
J
CC
VS
values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted) (continued)
J
CC
VS
Symbol
Description
Test Condition
Min
315
−
Typ
360
130
2.00
Max
415
−
Unit
ms
kHz
−
T
Blanking Time for CCM mode end detection
Clamp Frequency (DCM Frequency)
CCMend
f
No frequency foldback
No frequency foldback
clamp
clamp_ratio
f
f
over f
ratio
1.90
2.05
clamp
CCM
(t
)
On−Time below which Frequency Foldback is Engaged Low line
−
−
3.75
1.87
−
−
ms
on,FF LL
(t
)
High line
on,FF HL
F
Minimum DCM Frequency
Maximum On−Time (CCM)
Ramp Frequency Jittering
Jittering Frequency
25.0
13
−
30.5
15
36.0
17
−
kHz
ms
min
T
on,max
R
10
%
jit
F
−
119
−
Hz
jit
REGULATION BLOCK
Feedback Voltage Reference
V
REF
T = 25°C
J
2.46
2.44
2.50
2.50
2.54
2.56
V
%
%
J
T = −40°C to +125°C
V
L /
REF
Ratio (V
Low Detect Lower Threshold / V )
REF
95.0
97.5
2
95.5
98.0
−
96.0
98.5
−
DRE
OUT
V
V
H /
REF
Ratio (V
Low Detect Higher Threshold / V
)
DRE
OUT
REF
V
H
/ V
REF
Ratio (V
Low Detect Hysteresis / V )
REF
%
DRE
OUT
K
DRE1
K
DRE0
Loop Gain Increase due to Dynamic Response
Enhancer
pfcOK high
pfcOK low
−
−
10
5
−
−
−
T
Soft−Stop Duration for Gradual Discharge of the
Control Voltage from Max to Min
−
140
−
ms
SSTOP,max
StaticOVP
D
Duty Ratio
V
FB
= 3 V
−
−
0
%
MIN
SOFT SKIP CYCLE MODE BLOCK
CrM/DCM V pin Current Capability
I
400
1.2
0.4
24
−
−
mA
V
VM
M
V
V
M
Pin SKIP Threshold
1.5
0.5
29
1.8
0.6
33
SKIP(th)
V
SKIP2
pfcOK SKIP Threshold
V
T
SKIP2
pfcOK Minimum Negative Pulse Duration for SKIP
Detection
ms
V
/V
V
Upper Value (V ) During a Soft−SKIP Burst
REFX
102.5
96.5
103.0
98.0
103.5
99.5
%
%
REFX REF
FB
Cycle (defined as a V
percentage)
REF
(R
)
V
FB
Lower Value During a Soft Skip Cycle Burst
FB recover
(defined as a percentage of V
)
REF
CURRENT SENSE BLOCK
V
Current Sense Voltage Offset
Current Sense Voltage Offset
I
I
= −100 mA
−10
−10
185
−
−
−
15
10
mV
mV
mA
ns
CSoff100
CS
V
= −10 mA
CSoff10
CS
I
Low−Line Range Current Sense Protection Threshold
200
40
215
100
ILIMIT1(LL)
T
Over−current Protection Delay from (I > I
DRV low
) to
OCP(LL)
CS
ILIMIT1
I
Minimum I current for CCM detection
44
26
270
−
50
30
56
35
mA
mA
mA
ns
CCM−H
CS
I
Minimum I current for CCM confirmation
CS
CCM−L
I
Low−Line Threshold for Abnormal Current Detection
300
40
330
100
ILIMIT2(LL)
T
Over−current Protection Delay from (I > I
) to
OCP(HL)
CS
ILIMIT2
DRV low
T
Leading Edge Blanking Time for the Over−Current and
Abnormal Current Detection Comparators (Note 6)
150
260
350
ns
LEB,CS
I
Threshold for In−rush Current Detection
7.5
10.0
250
12.5
320
mA
in−rush
V
CS Fault Threshold
180
mV
CS(fault)
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NCP1655
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max
J
CC
VS
values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted) (continued)
J
CC
VS
Symbol
Description
Test Condition
Min
Typ
Max
Unit
CURRENT SENSE BLOCK
T
CS Fault Blanking Time
1
−
−
2
235
−
3
−
ms
mA
kW
CS(fault)
CS(test)
I
Source Current for CS pin testing
R
Minimum Impedance to apply to the CS pin not to Trig
the CS Short−to−Ground Protection (Note 6)
1.5
OCP,min
ZERO VOLTAGE DETECTION CIRCUIT
T
V
ZCD Leading Edge Blanking Time
70
0.90
0.40
0.35
0.5
0.5
−
100
1.00
0.50
0.50
−
130
1.10
0.60
−
ns
V
LEB,ZCD
ZCD(th)H
Zero Current Detection, V
rising
falling
ZCD
V
Zero Current Detection, V
V
ZCD(th)L
ZCD
V
Hysteresis of the Zero Current Detection Comparator
ZCD Pin Bias Current, V = V
V
ZCD(hyst)
I
2.0
2.0
85
mA
mA
ns
ns
ms
mA
kW
ZCD(bias)H
ZCD
ZCD(th)H
I
ZCD Pin Bias Current, V
= V
ZCD(th)L
−
ZCD(bias)L
ZCD
T
ZCD
(V
ZCD
< V ) to (DRV high)
ZCD(th)L
50
T
Minimum ZCD Pulse Width
−
50
−
SYNC
T
Watch Dog Timer in “Overstress” Situation
Source Current for ZCD pin testing
710
−
815
230
−
950
−
WDG(OS)
ZCD(test)
I
R
Minimum Impedance to apply to the ZCD pin not to
Trig the ZCD Short−to−Ground Protection (Note 6)
−
7.5
ZCD,min
UNDER− AND OVER−VOLTAGE PROTECTION
V
R
UVP Threshold
Ratio (UVP Threshold) over V
V
FB
V
FB
V
FB
V
FB
V
FB
falling
−
8
0.3
12
−
16
4
V
%
%
V
UVP
UVP
(V
/ V )
REF
falling
rising
rising
rising
REF
UVP
R
Ratio (UVP Hysteresis) over V
2
3
UVP(HYST)
REF
V
Soft OVP Threshold
Ratio (Soft OVP Threshold) over V
−
2.625
105
−
softOVP
R
(V
softOVP
/
104
106
%
softOVP
REF
V
REF
)
R
Ratio (Soft OVP Hysteresis) over V
V
FB
V
FB
V
FB
falling
rising
rising
1.5
−
2.0
2.7
2.5
−
%
V
softOVP(H)
REF
V
Fast OVP Threshold
fastOVP
R
Ratio (Fast OVP Threshold) over (Soft OVP Upper
102
103
104
%
fastOVP1
Threshold) (V / V
)
fastOVP
softOVP
R
Ratio (Fast OVP Threshold) over V
REF
(V
/
V
FB
V
FB
rising
falling
107.0
108.3
109.5
%
fastOVP2
REF
fastOVP
V
)
V
FB Threshold for Recovery from a Soft or Fast OVP
−
2.575
210
−
V
OVPrecover
(I )
FB bias Current @ V = V
50
50
450
450
nA
nA
B FB1
FB
softOVP
UVP
(I )
FB bias Current @ V = V
210
B FB2
FB
V
M
PIN
V
V
Pin Voltage in FCCrM (CrM or DCM)
2.0
2.5
3.0
V
V
M,FCCrM
M
(V
)
PWM Comparator Reference Voltage for CCM
Operation
V
V
rising
3.50
3.75
4.00
ramp pk
M
I
V
M
Pin Source Current
= 2 V, I = −100 mA
31
8.4
66
39
10.4
82
46
12.4
96
mA
mS
mA
mS
mA
M1(LL)
FB
CS
low line
I
(V
/
I
over (V
)
ratio
V
= 2 V, I = −100 mA
M1(LL)
M1(LL)
ramp pk
FB CS
)
low line
V = 2 V, I = −200 mA
FB
ramp pk
I
V
M
Pin Source Current
M2(LL)
CS
low line
I
(V
/
I
over (V
)
ratio
V
FB
= 2 V, I = −200 mA
17
22
26
M2(LL)
M2(LL)
ramp pk
CS
)
low line
ramp pk
I
V
M
Pin Source Current
V
FB
= 2 V, I = −100 mA
131
163
194
M1(HL)
CS
high line
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NCP1655
ELECTRICAL CHARACTERISTICS (For typical values T = 25°C, V = 12 V, V = 130 V unless otherwise noted. For min/max
J
CC
VS
values T = −40°C to +125°C, V = 12 V, V = 130 V unless otherwise noted) (continued)
J
CC
VS
Description
ratio
Symbol
Test Condition
= 2 V, I = −100 mA
Min
Typ
Max
Unit
I
/
I
over (V
)
V
35
43
52
mS
M1(HL)
M1(HL)
ramp pk
FB
CS
(V
)
high line
ramp pk
BROWN−OUT AND LINE RANGE DETECTION
Leakage Current
I
VS
V
S
V
V
V
V
V
V
V
V
V
= 400 V
−
−
95
30
102
94
mA
V
S
V
V
Upper Threshold for Brown−Out Detection
Lower Threshold for Brown−Out Detection
Hysteresis
increasing
decreasing
increasing
decreasing
increasing
decreasing
increasing
decreasing
88
BO(start)
BO(stop)
BO(HYS)
BO(blank)
VS
VS
VS
VS
VS
VS
VS
VS
80
87
V
V
3.5
550
220
207
9
8
−
V
t
Brown−out Detection Blanking Time
High−Line Level Detection Threshold
Low−Line Level Detection Threshold
Line Range Select Hysteresis
650
236
222
−
750
252
237
−
ms
V
V
HL
V
V
LL
LR(HYST)
V
V
T
High− to Low−Line Mode Selector Timer
Low− to High−Line Mode Selector Timer Filter
Lockout Timer for Low− to High−Line Mode Transition
22.8
300
450
26.0
360
515
30.2
420
600
ms
ms
ms
blank(LL)
T
filter(VS)
t
V
VS
increasing
line(lockout)
pfcOK AND BUV PROTECTION
V
pfcOK Voltage in OFF Mode
1 mA being sunk by the
pfcOK pin
−
−
100
mV
pfcOK−L
I
pfcOK Current
V
FB
V
FB
= 2.5 V, V
= 1 V
pfcOK
23.5
1.14
450
25.0
1.20
515
26.5
1.26
600
mA
V
pfcOK
V
Bulk Under−Voltage Protection (BUV) Threshold
BUV Delay Before Operation Recovery
falling
BUV
T
ms
BUV
THERMAL SHUTDOWN
T
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
−
−
150
50
−
−
°C
°C
LIMIT
TEMP
H
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by Design
www.onsemi.com
8
NCP1655
Powering the Circuit
The auxiliary source (V
of Figure 3) is often applied
AUX
The NCP1655 is ideal in applications where an external
power source (provided by an auxiliary power supply or
from the downstream converter) feeds the circuit. The
through a switch which can abruptly turn on and off. Note
that in this case, it is recommended to limit the V pin
CC
dV/dt by adding a small resistor (R ) particularly if the V
1
CC
maximum V
start−up level (11.25 V) is set low enough
capacitor (C ) is small. As an example, R can be 22 ohm and
CC
1
1
so that the circuit can be powered from typical 12−V voltage
rails.
C , 220 nF.
1
Figure 3. Powering the NCP1655
THREE MODES OF OPERATION
T
= 1 / f
) as it can easily be the case near the line
clamp
clamp
Depending on the current cycle duration, the NCP1655
operates in either FCCrM or CCM. In FCCrM (or frequency
clamped critical conduction mode), the circuit operates in
critical conduction mode until the switching frequency
zero crossing and in light−load conditions. Conversely, if the
current cycle exceeds T , the system naturally enters the
CrM operation mode. These transitions cause no
discontinuity in the operation and power factor remains
properly controlled.
clamp
exceeds the f
clamp threshold (130 kHz typically). At
clamp
that moment, as detailed in the next paragraph, the circuit
operates in discontinuous conduction mode with valley
turn−on.
Note that the circuit can transition from CrM to DCM and
vice versa within half−line cycles. Typically DCM is
obtained near the line zero crossing where current cycles
tend to be shorter and CrM, at the top of the line sinusoid
where the current cycles are longer. This is because the
circuit enters DCM operation when the current cycle is
CCM operation is obtained in heavy load conditions when
the current cycle is longer than 112% of the CCM switching
period. At that moment, the circuit operates as a CCM
controller in all parts of the line sinusoid (no transitions to
FCCrM) and remains in CCM for at least the CCM blanking
time (T
of 360 ms typically). This is because the
CCMend
circuit recovers the FCCrM mode only if it cannot detect 8
consecutive current cycles longer than the CCM switching
period for T
.
CCMend
shorter than T
(clamp period corresponding to f
:
clamp
clamp
www.onsemi.com
9
NCP1655
(t)
(t)
(t)
iL
iL
iL
VDS
VDS
VDS
V
ramp,pk
V
Internal
Ramp
Internal
Ramp
V
Internal
Ramp
clamp
clamp
T
T
TCCM
clamp
clamp
T
cycle
< T
→ DCM
T
clamp
< T
< T
→ CrM
T
> 112% * T
→ CCM
clamp
cycle
CCM
cycle
CCM
(FCCrM operation is recovered if
T
< T
for T
)
cycle
CCM
CCMend
Figure 4. Three Operation Modes (MOSFET Drain−source Voltage is in Red, the Internal Ramp is in Green)
Finally, depending on the conditions, the circuit operates
in CrM, DCM (with valley turn−on) or CCM.
Practically, the circuit compares the current cycle duration
delays the next cycle until the T
the circuit enters DCM operation. In DCM, the switching
period is actually a bit longer than T . This is because of
time has elapsed. Thus,
clamp
clamp
to two periods T
and T
:
the below discussed modulation method but mainly because
the next cycle is further delayed until the next valley is
detected (left plot of Figure 4). Doing so, valley turn−on is
obtained for minimized losses.
clamp
CCM
• If the current cycle duration is shorter than T
, T
clamp clamp
forces the switching frequency and the system operates in
DCM
Frequency−Clamped operation is controlled by a
proprietary circuitry which modulates the duty−ratio
cycle−by−cycle to prevent any discontinuity in operation
and ensure proper current shaping. Also, as shown by
Figure 5, it automatically varies the valley at which the
MOSFET turns on within the line sinusoid as necessary to
maintain valley switching and clamp the frequency over the
instantaneous input voltage range. For instance, DCM is
more likely to occur near the line zero crossing and CrM at
the top of the sinusoid. As the load further decays, current
cycles become shorter and DCM operation is obtained over
the entire line sinusoid. Furthermore, as detailed in the next
section and illustrated by Figure 5c and Figure 5d, the DCM
period clamp is increased below a certain load level for
frequency foldback (a longer minimum switching period is
forced causing frequency foldback). Anyway, in all cases,
the NCP1655 scheme ensures a clean control preventing that
repeated spurious changes in the turn−on valley possibly
cause current distortion and audible noise.
• If the current cycle duration is longer than T
but
clamp
shorter than 112% of T
, the system operates in CrM.
CCM
• If 8 consecutive current cycles happen to be longer than
112% of T , the system enters CCM mode with a
CCM
switching frequency set to f
= 1 / T
. The system
CCM
CCM
remains in this mode until the circuit cannot detect 8
consecutive current cycles longer than T
(360 ms typically).
for T
CCM
CCMend
Figure 4 provides a simplified description of the manner
the conduction mode is selected.
FREQUENCY−CLAMPED CRITICAL CONDUCTION
MODE
As aforementioned, the NCP1655 tends to operate in
critical conduction mode as long as the current switching
cycle is short enough not to enter the CCM mode. However,
if the current cycle happens to be shorter than the
frequency−clamp period (T
which is about 7.7 ms
clamp
typically leading to a 130 kHz DCM frequency), the circuit
www.onsemi.com
10
NCP1655
V
V
out
out
ILINE
ILINE
VDS
VDS
a) 40% load, top of the sinusoid
b) 40% load, near the line zero crossing
V
out
ILINE
V
out
ILINE
V
DS
VDS
c) 20% load, top of the sinusoid
d) 20% load,near the line zero crossing
Figure 5. Operation of the 500 W NCP1655 Evaluation Board @ 115 Vrms
FREQUENCY FOLDBACK IN DCM OPERATION
The frequency clamp (or DCM period) is gradually
decreased when the power demand drops below a certain
threshold. The expression of this power threshold depends
on the line range (see the “Line Range Detection” section):
DCM MINIMUM FREQUENCY (FOR DCM ONLY)
As aforementioned, the DCM frequency is gradually
lowered in very light load conditions as a function of the
load, to optimize the efficiency. This frequency foldback
function can reduce the frequency to nearly 10 kHz.
However, a specific ramp ensures that the switching
frequency remains above audible frequencies.
This ramp generates a clock which overrides the clock
provided by the DCM ramp (it forces next DRV pulse even
if the DCM ramp clock is not generated yet). However, the
minimum−frequency ramp remains synchronized to the
drain source voltage for valley turn−on. Practically, as
shown by Figure 6, the minimum−frequency ramp typically
sets the clock signal when the switching period reaches
33 ms. The DRV output will then turn on back when the next
valley is detected. If no valley can be detected within a 3 ms
interval, DRV is forced high whatever the drain−source
voltage is. As a result, the minimum frequency is typically
between 30 kHz (33 ms switching period) if a valley is
immediately detected and 28 kHz (36 ms switching period)
if no valley can be detected.
• Low−line power threshold:
2
12% @ Vin,rms
(PFF,th LL +
)
(eq. 1)
L @ fCCM
• High−line power threshold:
2
6% @ Vin,rms
(PFF,th HL +
)
(eq. 2)
L @ fCCM
The frequency clamp level linearly reduces as the power
further decays to nearly reach (f / 10) when the power
clamp
is close to zero. The circuit however forces a minimum
25 kHz operation to prevent audible noise. See next section.
Note that the frequency clamp can force a new DRV pulse
only if the system is in dead−time. The minimum frequency
clamp cannot cause CCM operation.
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11
NCP1655
V
V
ZCD
ZCD
time
time
DCM Fmin
Ramp
DCM Fmin
Ramp
DRV
DRV
time
33 ms (30 kHz)
36 ms (28 kHz)
Restart on the lowest ramp threshold
Restart on the highest ramp threshold
(synchronization to V case)
(no possibility to synchronize to V
)
DS
DS
Figure 6. DCM Minimum Switching Frequency Ramp
JITTERING
Where L is the value of the PFC inductor, V
is the line
is the CCM
in,rms
In CCM operation, the NCP1655 features the jittering
function which is an effective method to improve the EMI
signature. An internal low−frequency signal modulates the
oscillator swing which helps by spreading out energy in
conducted noise analysis.
rms voltage, V is the output voltage and f
out
CCM
switching frequency (65 kHz typically).
NOTES:
• The 8 current cycles longer than 112% of T
necessary
CCM
to detect CCM are not validated unless the inductor
current happens to exceed a minimum level within each
cycle. Practically, the second criterion consists of
Practically, the CCM switching frequency is typically
varied as follows:
• Jittering frequency: 119 Hz
• Pk to pk frequency variation: 10%
comparing the internal current sense current (I ) to the
following internal current references:
CS
Jittering is not implemented in frequency clamped critical
conduction mode (FCCrM including CrM and/or DCM
sequences) where valley turn−on operation naturally leads
to frequency variations.
♦ I
♦ I
(50 mA typically) when CCM is low.
(30 mA typically) when CCM is high.
CCM−H
CCM−L
CURRENT SENSE BLOCK
The NCP1655 is designed to monitor a negative voltage
CCM DETECTION
proportional to inductor current (I ). As portrayed by
L
As aforementioned, the NCP1655 measures the duration
of each current cycle (the current cycle is the total duration
of the on−time + the demagnetization time) and compares it
Figure 7, a current sense resistor (R
) is inserted in the
sense
return path to generate a negative voltage (V
)
Rsense
proportional to I . The circuit uses V
to detect when I
L
Rsense
L
to T
, which is the CCM switching period. The circuit
CCM
exceeds its maximum permissible level. To do so, the circuit
incorporates an operational amplifier that sources the
current necessary to maintain the CS pin at 0 V (refer to
enters CCM mode if it consecutively detects 8 current cycles
longer than 112% of T . Conversely, the circuit leaves the
CCM
CCM mode if the circuit does not detect 8 consecutive cycles
exceeding T for the CCM blanking time (T of
Figure 8). By inserting a resistor R
between the CS pin
OCP
CCM
CCMend
and R
, we adjust the current that is sourced by the CS pin
sense
360 ms typically).
The following expressions provide the typical power
thresholds for:
• CCM entering:
(I ) as follows:
CS
* (Rsense @ IL) ) (ROCP @ ICS) + 0
(eq. 5)
(eq. 6)
Which leads to:
Ǹ
0.56 @ Vin,rms 2 @ (Vout * 2 @ Vin,rms
)
Rsense
ICS
+
IL
(Pin,avg CCM +
)
ROCP
(eq. 3)
(eq. 4)
in
L @ fCCM @ Vout
In other words, the CS pin current (I ) is proportional to
CS
• FCCrM recovery:
the inductor current. Three protection functions use I : the
CS
Ǹ
0.50 @ Vin,rms 2 @ (Vout * 2 @ Vin,rms
)
over−current protection, the in−rush current detection and
the overstress detection. It is also used in CCM to control the
power−switch duty−ratio.
(Pin,avg CCM
)
+
out
L @ fCCM @ Vout
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12
NCP1655
In−rush Current Detection
IMPORTANT NOTES:
The NCP1655 permanently monitors the input current
and when in FCCrM, can delay the MOSFET turn on until
• As detailed below, two external resistors adjust the
current thresholds (R
and R
), thus offering some
sense
OCP
(I ) has vanished. This is one function of the I comparison
L
CS
flexibility on the R
selection which can be chosen for
sense
to the I
threshold (10 mA typical). This feature helps
in−rush
an optimal trade−off between noise immunity and losses.
maintain proper FCCrM operation when the ZCD signal is
too distorted for accurate demagnetization detection like it
can happen at very high line. The inrush comparator also
serves to detect that the inductor current remains at a low
value, as necessary for some functions like the CS pin
short−to−ground accidental protection. Re−using above
• However the R
resistance must be selected higher or
OCP
equal to 1.5 kW. If not, the protection against accidental
short−to−ground failures of the CS pin may trip and thus,
prevent operation of the circuit.
Over−Current Protection (OCP)
example (R
= 30 mW, R
= 2 kW), the inrush level of
sense
OCP
If I exceeds the OCP threshold (I
which is
CS
ILIMIT1
the input current is typically set to:
200 mA typically) an over−current situation is detected and
the MOSFET is immediately turned off (cycle−by−cycle
current limitation). The maximum inductor current can
hence be limited as follows:
2 @ 103
30 @ 10*3
I(L(inrush)
+
@ 10 @ 10*6 ^ 0.67 A
(eq. 9)
Abnormal Current Detection (Overstress)
ROCP
When the PFC stage is plugged to the mains, the bulk
capacitor is abruptly charged to the line voltage. The charge
current (named in−rush current) can be very huge even if an
in−rush limiting circuitry is implemented. Also, if the
inductor saturates, the input current can go far above the
current limitation due to the reaction time of the overcurrent
protection. If one of these cases leads the internal CS pin
IL(max)
+
ILIMIT1
(eq. 7)
Rsense
As an example, if R
maximum inductor current is typically set to:
= 30 mW and R
= 2 kW, the
sense
OCP
2 @ 103
30 @ 10*3
I(L(max)
+
@ 200 @ 10*6 ^ 13.3 A
(eq. 8)
current (I ) to exceed I
(set to 150% of I
), an
CS
ILIMIT2
ILIMIT1
abnormal current situation is detected, causing the DRV
output to be kept low for 800 ms after the circuit has dropped
below the in−rush level.
I CS
Over Current Limit
CIN
I ILIMIT1
To PWM
reset
Overstress
input
I CS
iin (t)
S
I CS
Q
I ILIMIT2
S
R
Q
Q
Q
R
CS
Negative clamp
800 ms
ICS
overstress delay
I CS
Inrush
I inrush
ROCP
Rsense
iin (t)
Figure 7. Current Protections
Re−using above example (R
= 30 mW, R
= 2 kW),
controllers. In other words, it directly computes the power
sense
OCP
the overstress level of the input current is typically set to:
switch on−time as a function of the inductor current.
Practically, the I current is modulated by the control signal
2 @ 103
30 @ 10*3
CS
Iin(OVS)
+
@ 300 @ 10*6 + 20 A
and sourced by the V pin to build the CCM current
(eq. 10)
M
information. The V pin signal is:
M
Duty Ratio Control in CCM Mode
The NCP1655 re−uses the proven “predictive method”
scheme implemented in NCP1653 and NCP1654 CCM PFC
VRAMP,pk
VM + 0.4 @ RM
@
@ ICS
(eq. 11)
VREGUL
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13
NCP1655
VRAMP,pk
Where V
, V
and R respectively are the
REGUL
RAMP,pk M
Rsence
ROCP
VM + 0.4 @ RM
@
@
@ 〈IL〉TSW
regulation voltage (derived from V
oscillator peak value and the V pin resistor. Actually, a
), the CCM
CONTROL
(eq. 12)
VREGUL
M
Now, 〈I 〉 , the inductor current averaged over the
switching frequency is the input current. Thus, Equation 12
can be changed into:
L Tsw
capacitor C is to be added across R to filter and remove
M
M
the switching frequency component of the V pin voltage.
Hence, replacing I by its function of the inductor current
given by Equation 6, it comes:
M
CS
VRAMP,pk
RM @ Rsense
VM + 0.4 @
@
@ iin (t)
(eq. 13)
ROCP
VREGUL
CCM Oscillator Ramp
Generation
V
of the V pin
M
RAMP,pk
current
RAMP
CLOCK
Clock
S
R
DRV
Q
Q
VRAMP,pk
vRAMP
(t)
IM + 0.4 @ ICS
@
VREGUL
+
+
RM
CM
v
(t)
−
M
VRAMP,pk
Figure 8. Duty Ratio Control in CCM Mode
Figure 8 sketches the manner the duty ratio is controlled
in CCM.
Like in the NCP1653/4 controllers, when the power
switch on−time starts, an oscillator ramp is added to the V
Hence, the CCM input power expression is:
• Low−line conditions:
2
2.5 @ ROCP @ Vin,rms
VCONTROL
M
Pin,avg
+
@
(eq. 17)
(eq. 18)
R
M @ Rsence
Vout
pin voltage and the power switch opens when the sum
reaches the oscillator upper threshold. Doing so, if V
• High−line conditions:
RAMP,pk
designates the peak value of the oscillator ramp, the V
M
2
0.625 @ ROCP @ Vin,rms
VCONTROL
voltage and the on−time (t ) are linked as follows:
Pin,avg
+
@
on
R
M @ Rsence
Vout
ton
@ ǒ1 * Ǔ
VM + VRAMP,pk
NOTE: The R resistance must be selected higher than
M
(eq. 14)
TSW
4.5 kW. If not, the circuit may not be able to
Now, the off−duty−ratio of a boost converter operated in
charge the V pin to SKIP threshold (V
).
M
SKIP(th)
CCM is:
ZERO CROSSING DETECTION BLOCK
vin (t)
Vout
ton
doff + 1 *
+
The NCP1655 optimizes the efficiency by turning on the
MOSFET at the very valley when operating in critical and
discontinuous conduction modes. For this purpose, the
circuit is designed to monitor the voltage of a small winding
taken off of the boost inductor. This auxiliary winding
(called the “zero current detector” or ZCD winding) gives a
scaled version of the inductor voltage which is easily usable
by the controller. The PFC stage being a boost converter, this
auxiliary winding voltage provides:
(eq. 15)
TSW
Combining Equations 13, 14 and 15, the following
expression of the input current is obtained:
R
OCP @ VREGUL
RM @ Rsence
vin (t)
Vout
iin (t) + 2.5 @
@
(eq. 16)
The input current is as targeted proportional to the input
voltage.
The CCM regulation voltage (V
the regulation control signal provided by the
“transconductance error amplifier and compensation”
) is proportional to
REGUL
NAUX
• ǒ*
(t)Ǔ
@ vin
NP
internal block (V
) as follows:
CONTROL
during the MOSFET conduction time
• (V
) in low−line conditions (see the “Line Range
Detection” section)
/ 4) in high−line conditions (see the “Line
Range Detection” section)
CONTROL
NAUX
• ǒ
(t))Ǔ
(Vout * vin
NP
• (V
CONTROL
www.onsemi.com
14
NCP1655
during the demagnetization time. This voltage used to
detect the zero current detection can be small when the
input voltage is nearly the output voltage.
• A voltage oscillating around zero during dead−times
ZCD
R1
+
−
DT
S
R
C3
I
< I
inrush
CS
Q
Q
S
R
Q
Q
V
/V
ZCD(th)H
ZCD(th)L
f
SW,min
ramp
reset
DRV
Figure 9. Zero Current Detection Block
Figure 9 shows how the NCP1655 detects the valley.
An internal comparator detects when ZCD pin voltage
exceeds an upper threshold V (1 V typically). When
ZCDH
this is the case, the inductor core is resetting and the ZCD
latch is set. This latch will be reset when the next driver pulse
occurs. Hence the output of the latch remains high during the
whole off−time (demagnetization time + any possible dead
time). The output of the comparator is also inverted to form
a signal that is low when the ZCD pin voltage is higher than
the V
upper voltage reference of the ZCD comparator.
ZCDH
As a result, V
that is the AND combination of both
DMG
signals is high when the ZCD pin voltage drops below the
lower threshold of the ZCD comparator, that is, at the
auxiliary winding falling edge. It is worth noting that as
portrayed by Figure 10, V
is also representative of the
AUX
MOSFET drain−source voltage (“V ”). More specifically,
DS
when V
is below zero, V is minimal (below the input
AUX
DS
voltagev (t)). That is why V
is used to enable the driver
in
DMG
so that the MOSFET turns on when its drain−source voltage
is low. Valley switching reduces the losses and interference.
Figure 10. Zero Current Detection Timing Diagram
(VAUX is the Voltage Provided by the ZCD Winding)
IMPORTANT NOTE:
• The ZCD pin impedance (for instance R of Figure 9),
3
Note that the circuit can detect faulty conditions of the
ZCD pin:
• A permanent 1 mA current source pulls up the pin if it
happens to be floating. The circuit is hence maintained off
• If the pin is grounded, no falling edge of the auxiliary
winding can be detected. The DRV remains off until the
DCM minimum frequency ramp initiates a new cycle.
must be higher than 7.5 kW not to trigger the ZCD pin
short−to ground protection.
If no ZCD can be detected when the circuit operates in
FCCrM mode, the circuit cannot use the valley detection to
start a new current cycle. In this case, the next DRV pulse is
forced by the DCM minimum frequency ramp (f
of Figure 9) which acts as a watchdog.
ramp
sw,min
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15
NCP1655
Before the new pulse is generated, the circuit senses the
less than V
(300 mV typically), the UVP protection trips
UVP
and thus, protects the circuit if the FB pin is floating.
The fast OVP comparator is analogue and directly
monitors the feedback pin voltage. The rest of the block
which is digital, receives a digitized feedback value. The
sampling rate is 10 kHz.
pin impedance by sourcing 250 mA. No DRV pulses are
generated until the pin voltage exceeds V
. Hence,
ZCDH
the part is inhibited when the pin is grounded. Not to
trigger this protection, the pin impedance (for instance R
3
of Figure 9. must be higher than 7.5 kW).
The digital “transconductance error amplifier and
The ZCD pin is shortly grounded when the MOSFET
turns off (ZCD leading edge blanking − LEB). The LEB of
100 ns typical, is implemented to prevent the ZCD
comparator from tripping due to turn−off noise.
compensation” block provides the control signal V
CONTROL
(which is devoid of the PFC stage 120 or 100 Hz ripple) to
control the duty ratio.
Practically, the signal V
does dictate the on−time.
REGUL
OUTPUT VOLTAGE CONTROL (REGULATION
BLOCK)
The general structure is sketched by Figure 11.
A small 250 nA sink current is built−in to pull down the
V
differs from V
only in the case of a
REGUL
CONTROL
soft−OVP event (see “soft−OVP” paragraph) and in CCM
when in high line where (V
= V
/ 4). In all
REGUL
CONTROL
other cases, (V
= V
).
REGUL
CONTROL
pin if the FB pin is accidentally open. In this case, V being
FB
V
out
PWM latch
Fast OVP
Detection
SoftOVP
Soft OVP
Detection
R
FB1
Soft−Stop
HL
FB
Transconductance
Error Amplifier and
compensation
Regulation
Signal
Generation
VCONTROL
staticOVP
VREGUL
S/H
I
STBY
DRE
B(FB)
CCM
HL
R
FB2
Dynamic
Response
Enhancer
Bulk Under−
Voltage
BUV
Detection
OFF
UVP
To soft−SKIP block
Detection
To pfcOK block
Figure 11. Regulation Circuitry
Output Voltage Levels
The regulation block and the soft−OVP, UVP and DRE
comparators monitor the FB pin voltage. Based on the
typical value of their parameters and if (V
output voltage nominal value (e.g., 390 V), we can deduce
the following typical levels:
• Output Regulation Level: V
• Output Lower Soft−SKIP Level:
(V ) = 98% · V
out,softSKIP L
out,nom
Where:
)is the
out,nom
• V
is the regulation reference voltage (2.5 V typically)
REF
• R
and R
are the feedback resistors (see Figure 1).
FB1
FB2
• k is the scale down factor of the feedback resistors
= V
/ k
REF FB
FB
out,nom
RFB2
• Output Soft−OVP Level: V
• Output Fast−OVP Level: V
• Output UVP Level: V
= 105% · V
out,nom
out,SOVP
out,FOVP
ǒk
Ǔ
+
FB
R
FB1 ) RFB2
= 107% · V
.
out,nom
= 12% · V
out,UVP
out,nom
• V
and V
are the levels between
out,softSKIP−H
out,softSKIP−L
• Output DRE Level: V
• Output BUV Level: V
= 95.5% · V
out,nom
out,DRE
which the output voltage swings when in soft−SKIP mode
(see the “Soft−SKIP Mode” section)
= 48% · V
out,nom
out,BUV
• Output Upper Soft−SKIP Level:
(V ) = 103% · V
out,softSKIP H
out,nom
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16
NCP1655
StaticOVP
Soft−OVP
The circuit stops providing DRV pulses when V
reaches its bottom level.
As sketched by Figure 12, the soft−OVP trips when the
feedback voltage exceeds 105% of V and remains in this
CONTROL
REF
mode until V drops below 103% of V . When the
soft−OVP trips, it reduces the power delivery down to zero
in 4 steps:
FB
REF
fastOVP Comparator
+
−
• Step 1: V
400 ms
• Step 2: V
400 ms
• Step 3: V
400 ms
drops to 75% of the V
drops to 50% of the V
drops to 25% of the V
value for
value for
value for
107% Vref
REGUL
REGUL
REGUL
CONTROL
CONTROL
CONTROL
fastOVP
S
Q
Q
OVPout Comparator
R
−
+
FB
103% Vref
OVPout
• Step 4: V
drops and remains to 0 until the
soft−OVP fault is over, that is, when the output voltage
REGUL
drops below 103% of its regulation level.
softOVP Comparator
+
FastOVP
As sketched by Figure 12, the fast−OVP trips when the
feedback voltage exceeds 107% of V and remains in this
−
105% Vref
S
softOVP
Q
REF
mode until V drops below 103% of V . The drive is
Q
FB
REF
immediately stopped when the fast OVP is triggered.
250 nA
R
OVPout
Figure 12. Fast and Soft OVP Protections
105% · V
OUT,NOM
V
OUT
103% · V
V
OUT,NOM
OUT,NOM
time
time
Soft−OVP
V
CONTROL
(V
)
CONTROL 0
The regulation loop decreases V
CONTROL
(V
)
(quantization steps are not shown)
CONTROL 1
time
75% · V
CONTROL
V
REGUL
50% · V
CONTROL
25% · V
CONTROL
V
= (V
)
REGUL
CONTROL 0
0% · V
CONTROL
400 ms
V
= (V
)
REGUL
CONTROL 1
400 ms
400 ms
time
Figure 13. Soft−OVP
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17
NCP1655
Dynamic Response Enhancer
• A line−sag or a brownout fault is detected
• A BUV fault is detected
• When in soft−SKIP mode, the output voltage reaches its
upper threshold, the active phase of the burst ends. At that
moment, soft−stop leads to a gradual stop of the power
delivery and a smooth idle phase start for a minimized risk
of audible noise.
The NCP1655 embeds a “dynamic response enhancer”
circuitry (DRE) which firmly contains under−shoots. An
internal comparator monitors the feed−back voltage on pin 1
(V ) and when V is lower than 95.5% of the regulation
FB
FB
reference voltage (V ), it speeds−up the charge of the
REF
compensation network. Practically a 10x increase in the loop
gain is forced until the output voltage has reached 98% of its
nominal value.
A soft−skip sequence is terminated when V
CONTROL
reaches its bottom level. In the soft−SKIP case, the soft−stop
sequence is also immediately ended when the output voltage
drops below the restart level, so that the restart of operation
Soft−Stop Sequences
A soft−stop sequence is forced when the circuit must stop
operating in a smooth manner to prevent bouncing effects
possibly resulting from an abrupt interruption. Soft−stop
is not delayed until the total V
discharge.
CONTROL
gradually reduces V
to zero, in the following cases:
CONTROL
SOFT−SKIP MODE
As detailed in application note AND90011
(http://www.onsemi.com/pub_link/Collateral/AND90011−
D.PDF), the circuit is designed to be externally forced to
enter the soft−SKIP mode by applying negative pulses on
either the pfcOK pin or the V pin. In CCM mode, the V
pin provides the current information necessary to modulate
The soft−SKIP mode can also be triggered by generating
a negative pulse on the pfcOK pin. To do so, the pfcOK pin
must be pulled down below V
(0.4 V min) for T
SKIP2
SKIP2
(33 ms max) or more. Note that in this case, the pfcOK signal
may have to be filtered before being applied to the
downstream converter so that the negative pulses do not stop
its operation. Figure 14 illustrates a possible implementation
with ON Semiconductor LLC controller NCP13992.
M
M
the duty−ratio. In CrM and DCM modes of operation, this
pin is pulled−up to V
(2.5 V typically). If the pin is
M,DCM
externally forced below V
(1.5 V typically) for 100 ms
SKIP(th)
or more, the circuit enters the soft−SKIP mode.
NCP13992
BO
Pin
R2
C3
NCP13992
Pmode
Pin
NCP1655
pfcOK
Pin
D2
C1
D1
4.7 V
C2
R1
Grounding pulses
generation
Figure 14. Circuitry to Control the Soft−SKIP Mode
When the V or pfcOK pins receive a grounding pulse, the
circuit detects a soft−SKIP condition. As a result, as
illustrated by Figure 15, the NCP1655:
turned off so that the circuit consumption is reduced to a
minimum (I = I which is 250 mA typically). Since
no energy is provided to the bulk capacitor, the output
voltage decays.
M
CC
CC3
• First charges up the output voltage to 103% of its nominal
voltage (103% V
).
• When the output voltage drops below 98% of its nominal
out,nom
voltage (98% * V
), the circuit exits the deep idle
• Then, enters a soft−stop sequence to gradually reduce the
line current and thus minimize the risk of audible noise.
If the output voltage reaches the soft−OVP level (105%
out,nom
mode. Operation resumes and the output voltage charges
up to 103% of its nominal voltage again.
V
), the protection trips and the 4−step stop
• When the output voltage reaches 103% of its nominal
out,nom
illustrated by Figure 13 takes place.
voltage, there are two possibilities:
♦ The V or the pfcOK pins have received a grounding
• When the soft−stop sequence (or the 4−step stop) is
finished, the circuit enters the deep idle mode: the part
stops switching and all the non−necessary circuitries are
M
pulse during this latest charge to 103% V
. In this
out,nom
case, the circuit remains in soft−SKIP mode, i.e., the
www.onsemi.com
18
NCP1655
circuit enters a new deep idle mode phase at the end of
the soft−stop (or the 4−step stop) sequence.
V
. In this case, the circuit recovers the normal
out,nom
operation until the V or pfcOK pins receive a
M
♦ The V or the pfcOK pins have not received a
grounding pulse
M
grounding pulse during this latest charge to 103%
103% Vout,nom
Vout
98% * Vout,nom
ILINE
5 s
Figure 15. Soft−SKIP Operation
NOTES:
is in nominal operation and grounded when the PFC stage is
in start−up phase or in a fault condition. Using the pfcOK
signal to enable/disable it, the downstream converter can be
optimally designed for the narrow voltage range nominally
provided by the PFC stage in normal operation.
Practically, the pfcOK pin is grounded when the PFC stage
enters operation and remains in low state until the output
voltage has nearly reached its nominal level (practically
• The circuit cannot enter the soft−SKIP mode when it
operates in CCM.
• The soft−stop sequence is interrupted if not finished when
the output voltage reaches the soft−SKIP bottom
threshold (V
operation.
) so that the circuit can resume normal
out,nom
• When in soft−SKIP mode, the NCP1655 is prevented
from entering CCM during the active burst. This is to
minimize the risk of audible noise by limiting burst
energy. However, if during the soft−SKIP active burst, a
sudden load increase causes the output voltage to drop
when V reaches 98%V ). At that moment, the pfcOK
FB
REF
pin sources a current proportional to the feedback voltage
(k · V ). See Figure 16. Placing an external resistor
FB
between the pfcOK and GND pins, we obtain a voltage
V
pfcOK
which is proportional to the bulk voltage and can
below the DRE level (95.5% of V
) while V pin is
out,nom
M
serve as a feedforward signal for the downstream converter.
k typical value is 10 mA/V so that the pfcOK pin typically
sources 25 mA when the FB voltage is 2.5 V (regulation
level).
Conversely, when a major fault is detected (brown−out,
UVLO, Thermal shutdown, OVP2 latch off, UVP and
BUV), the internal OFF signal turns high and the pfcOK pin
is grounded to prevent the downstream converter from
operating in the abnormal conditions causing these faults.
above 1.5 V, the circuit can enter CCM if necessary to
deliver the power. Such a situation normally occurring
when the application gets loaded, the circuit will leave the
soft−SKIP mode at the end of this burst when the output
voltage is charged to 103% V
.
out,nom
pfcOK SIGNAL
The pfcOK pin is designed to control the operation of the
downstream converter. It is in high state when the PFC stage
www.onsemi.com
19
NCP1655
FB
VDD
k*V
−
FB
+
V
BUV
BUV
S
R
Q
Q
pfcOK
R1
LLC BO pin
C1
+
V
STBY
STBY_init1
−
BUV Delay
pfcOK_int
pfcOK_int
V
FB
> 98% V
REF
S
Q
Q
R
OFF
Figure 16. pfcOK Block
In particular, when the feedback voltage drops below the
internal reference (1.2 V typically), a BUV fault is
detected (BUV stands for Bulk Under−voltage).
• When the soft−stop sequence ends, the PFC stops
operating until the T delay has elapsed (515 ms
V
BUV
BUV
typically). However, if the BUV protection trips during a
line sag condition, the T delay is bypassed and
Corresponding output voltage BUV threshold is:
BUV
VBUV
operation immediately resumes when the line recovers.
The wakeup information is provided by signal
“Line_Recovery” generated by the line−sag block. This
enables a rapid operation recovery when the line fault is
over.
Vout,BUV
+
@ Vout,nom
(eq. 19)
VREF
When a BUV fault is detected:
• The pfcOK pin is grounded
• A soft−stop sequence is started during which the power
delivery gradually drops to zero
INPUT VOLTAGE SENSING
The V pin provides access to the brownout and line range
or the V pin can be simply connected to the rectified voltage
S
S
detectors. The brownout detector detects too low line levels
and the line range detector determines the presence of either
110 V or 220 V ac mains. Depending on the detected input
voltage range device parameters are internally adjusted to
optimize the system performance.
(Figure 17b case) still through a diode. The diodes prevent
the pin voltage from going below ground. A resistor in series
with the diodes can be used for protection. It should be less
than 20 k not to alter the accuracy of the input voltage
measurement.
As shown by Figure 17, line and neutral can be diode
“ORed” before connecting to the V pin (Figure 17a case)
S
www.onsemi.com
20
NCP1655
Ac line
Ac line
FB
V
S
FB
V
S
1
2
3
4
5
10
1
2
3
4
5
10
EMI
Filter
EMI
Filter
Vcc
pfcOK
Vm
Vcc
pfcOK
Vm
8
7
6
8
7
6
DRV
GND
CS
DRV
GND
CS
ZCD
ZCD
a) The line terminals are sensed
b) The input voltage is sensed
Figure 17. High−Voltage Input Connection
+
V
HS
BO_NOK
−
+
T
BO(blank)
V
if BONOK is high
if BONOK is low
BO(start)
V
reset
BO(stop)
Figure 18. Brown−Out Detection
BROWN−OUT PROTECTION
The controller is enabled once the V pin voltage is above
t
(typically 500 ms), expires. The timer and logic
line(lockout)
is included to prevent unwanted noise from toggling the
operating line level.
S
the upper brownout threshold, V
, typically 95 V, and
BO(start)
V
reaches V
. The brownout timer (t of
The line range detection circuit optimizes the operation
for universal (wide input mains) applications. Practically, in
“high−line”:
CC
CC(on)
BO(blank)
typically 650 ms) is enabled once the V pin voltage drops
below the lower brownout threshold, V
S
, which is
BO(stop)
87 V typically and a brown−out fault is detected if V
• The regulation bandwidth and the CCM gain are divided
VS
doesn’t exceed V
before the brownout timer expires.
BO(stop)
by 4
The timer is set long enough to pass line−dropout tests. The
timer ramp starts charging once the V pin voltage drops
• The V
below which frequency foldback starts is
CONTROL
S
reduced by 2.
below V
.
BO(stop)
When the line recovers, the circuit does not resume
operation until V is above the startup threshold (V
of 10.5 V typically) so that a clean restart is obtained
OFF MODE
The circuit turns off when the circuit detects one of the
following major faults:
CC
CC(on)
• BONOK: a brown−out fault is detected (too low a line
voltage for proper operation).
• BUV: too low a bulk voltage is detected for proper
operation of the downstream converter.
LINE RANGE DETECTION
The input voltage range is detected based on the peak
voltage measured at the V pin.
S
The controller compares V to the high−line select
VS
• TSD: The thermal shutdown protection stops the circuit
threshold, V
, typically 236 V. A blanking time
lineselect(HL)
operation when the junction temperature (T ) exceeds
T
of 300 ms typically, prevents erroneous detection
J
filter(VS)
150°C typically. The controller remains off until T goes
due to noise. Once V exceeds V
operates in “high−line” (Europe/Asia).
The controller switches back to “low−line” mode if V
, the PFC stage
J
VS
lineselect(HL)
below nearly 100°C.
• UVLO: Incorrect feeding of the circuit
VS
remains below V
(which is 222 V typically, i.e.,
lineselect(LL)
• UVP: an Output Under−Voltage situation is detected
14 V less than V
, thus offering an hysteresis) for
lineselect(HL)
when V is less than V
(12% of V , typically)
REF
FB
UVP
the t timer delay (25 ms typically).
line
If the controller transitions to “low−line”, it is prevented
from switching back to “high−line” until the lockout timer
www.onsemi.com
21
NCP1655
OFF
TSD
UVP
UVLO
staticOVP
BONOK
BUV
S
R
Soft−Stop
Q
Q
SKIP
StaticOVP
Figure 19. Faults Leading to the OFF Mode
When one of the TSD, UVP, UVLO faults is detected, the
part immediately turns off:
output regulation and OVP levels remain negligible with
the resistor dividers typically used to sense the bulk
voltage.
• The DRV pin is disabled.
• Improper connection of the ZCD pin
• The pfcOK pin is grounded
The ZCD pin sources a 1 mA current to pull up the pin
voltage and hence disable the part if the pin is floating. If
the ZCD pin is grounded before operation, the circuit
cannot monitor the ZCD signal and no DRV pulse can be
generated until the DCM minimum frequency ramp has
elapsed. At that moment, the circuit sources a 250 mA
current source to pull−up the ZCD pin voltage. No drive
pulse is initiated until the ZCD pin voltage exceeds the
ZCD 1 V threshold. Hence, if the pin is grounded, the
circuit stops operating. Circuit operation requires the pin
impedance to be 7.5 kW or more, the tolerance of the
NCP1655 impedance testing function being considered
over the −405C to 1255C temperature range.
• The circuit consumption drops to I
CC1
When a BUV fault is detected, pfcOK immediately turns
low to disable the downstream converter but the part does
not stop operating. Instead, a soft−stop sequence is forced to
gradually decay the power delivery until the staticOVP level
is reached. At that moment, the circuit turns off.
When a BONOK fault is detected, pfcOK keeps high and
the part enters a soft−stop sequence to gradually decay the
power delivery until the staticOVP level is reached. At that
moment, the circuit turns off leading the drive pin to be
disabled, the pfcOK output to be grounded and the circuit
consumption to be reduced.
When the fault having caused the off mode is removed, the
• Improper connection of the CS pin
circuit does not recover until V exceeds V
.
CC
CC(on)
A comparator to 250 mV senses the CS pin. If the CS pin
exceeds this level for 1 or 2 ms, the part is off for the 800 ms
delay time. In addition, the CS pin sources a 1 mA current
to pull up the pin voltage and hence disable the part if the
pin is floating. The CS short−to−ground is also detected
as follows: whenever the input voltage is higher than the
FAILURE DETECTION
When manufacturing a power supply, elements can be
accidentally shorted or improperly soldered. Such failures
can also happen to occur later on because of the components
fatigue or excessive stress, soldering defaults or external
interactions. In particular, adjacent pins of controllers can be
shorted, a pin can be grounded or badly connected. Such
open/short situations are generally required not to cause fire,
smoke nor big noise. The NCP1655 integrates functions that
ease meeting this requirement. Among them, we can list:
brown−out threshold and no I current higher than
CS
I
is detected at the end of a MOSFET conduction
in−rush
phase (DRV high), the circuit sources a 250 mA current
source to pull−up the CS pin voltage. No drive pulse is
initiated until the CS pin voltage exceeds the 250 mV fault
threshold. Hence, if the pin is grounded, the circuit stops
operating. Circuit operation requires the pin impedance
to be 1.5 kW or more, the tolerance of the NCP1655
impedance testing function being considered over the
−405C to 1255C temperature range.
• Floating feedback pin
A 250 nA sink current source pulls down the FB voltage
so that the UVP protection trips and prevents the circuit
from operating if this pin is floating. This current source
is small (450 nA maximum) so that its impact on the
ORDERING INFORMATION
†
Device Order Number
NCP1655ADR2G
Specific Device Marking
Package Type
Shipping
NCP1655A
SOIC−9 NB
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
22
NCP1655
PACKAGE DIMENSIONS
SOIC−9 NB
CASE 751BP
ISSUE A
2X
NOTES:
0.10
C A-B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DE-
TERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERM-
INED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
D
H
A
2X
0.20
C
4 TIPS
0.10 C A-B
F
10
6
E
1
5
L2
A3
SEATING
PLANE
L
C
0.20
C
9X b
DETAIL A
B
5 TIPS
M
MILLIMETERS
0.25
C A-B D
DIM MIN
MAX
1.75
0.25
0.25
0.51
5.00
4.00
TOP VIEW
A
A1
A3
b
D
E
1.25
0.10
0.17
0.31
4.80
3.80
9X
h
X 45
_
0.10
C
0.10
C
M
e
1.00 BSC
H
h
5.80
0.37 REF
6.20
A
L
L2
M
0.40
0
1.27
0.25 BSC
DETAIL A
e
SIDE VIEW
A1
SEATING
PLANE
C
8
_
_
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
1.00
PITCH
9X
0.58
6.50
1
9X
1.18
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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