NCP1632ADR2G [ONSEMI]
Critical Conduction Mode (CrM) Power Factor Controller, Interleaved;
| 型号： | NCP1632ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Critical Conduction Mode (CrM) Power Factor Controller, Interleaved |
| 文件： | 总26页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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2-Phase Power Factor
Controller, Interleaved
SOIC−16
D SUFFIX
CASE 751B
NCP1632A
The NCP1632A integrates a dual MOSFET driver for interleaved
PFC applications. Interleaving consists of paralleling two small stages
in lieu of a bigger one, more difficult to design. This approach has
several merits like the ease of implementation, the use of smaller
components or a better distribution of the heating.
MARKING DIAGRAM
NCP1632AG
AWLYWW
Also, Interleaving extends the power range of Critical Conduction
Mode that is an efficient and cost−effective technique (no need for low
t diodes). In addition, the NCP1632A drivers are 180° phase shifted
rr
NCP1632AG = Device Code
for a significantly reduced current ripple.
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
Housed in a SOIC16 package, the circuit incorporates all the
features necessary for building robust and compact interleaved PFC
stages, with a minimum of external components.
WW
G
= Work Week
= Pb−Free Package
General Features
• Near−Unity Power Factor
• Substantial 180° Phase Shift in All Conditions Including Transient
Phases
PIN ASSIGNMENT
ZCD2
FB
ZCD1
• Frequency Clamped Critical Conduction Mode (FCCrM) i.e., Fixed
Frequency, Discontinuous Conduction Mode Operation with Critical
Conduction Achievable in Most Stressful Conditions
• FCCrM Operation Optimizes the PFC Stage Efficiency Over the
Load Range
• Out−of−phase Control for Low EMI and a Reduced rms Current in
the Bulk Capacitor
• Frequency Fold−back at Low Power to Further Improve the Light
Load Efficiency
1
REF5V/pfcOK
DRV1
Rt
OSC
GND
Vcc
Vcontrol
FFOLD
DRV2
BO
Latch
CS
OVP / UVP
(Top View)
• Accurate Zero Current Detection by Auxiliary Winding for Valley
Turn On
• Fast Line / Load Transient Compensation
ORDERING INFORMATION
• High Drive Capability: −500 mA / +800 mA
†
Device
NCP1632ADR2G
Package
Shipping
• Signal to Indicate that the PFC is Ready for Operation (“pfcOK” Pin)
SOIC−16
(Pb−Free)
2500 / Tape &
Reel
• V Range: from 10 V to 20 V
CC
Safety Features
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Output Over and Under Voltage Protection
• Brown−Out Detection with a 50−ms Delay to Help Meet Hold−up
Time Specifications
• Soft−Start for Smooth Start−up Operation
• Programmable Adjustment of the Maximum Power
• Over Current Limitation
Typical Applications
• Computer Power Supplies
• LCD / Plasma Flat Panels
• Detection of Inrush Currents
• All Off Line Appliances Requiring Power
Factor Correction
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
June, 2022 − Rev. 1
NCP1632A/D
NCP1632A
VIN
VOUT
Dbypass
L2
RBO1
VOUT
V
AUX2
pfcOK
ROUT1
ROUT2
RBO2
ROVP1
L1
V
AUX2
RZCD2
ZCD2
RZCD1
CpfcOK
ZCD1
pfcOK
DRV1
D1
1
16
15
14
13
12
11
10
9
ROUT3
FB
ROVP2
2
RT
Rt
3
D2
M1
ROSC
CFF
OSC
GND
VCC
OVP
4
in
COSC
CVCC
Vcontrol
M2
5
CCOMP2
RCOMP1
RFOLD
Ac line
DRV2
FFOLD
RBO3 ROVP3
6
Latch
CS
BO
CFOLD
7
OVP/UVP
EMI
Filter
CCOMP1
8
CBO2
CBULK
CIN
ROCP
OVPin
RCS
Figure 1. Typical Application Schematic
Table 1. MAXIMUM RATINGS
Symbol
Rating
Pin
Value
Unit
V
Maximum Power Supply Voltage Continuous
12
−0.3, +20
−0.3, +9.0
V
V
CC(MAX)
V
MAX
Maximum Input Voltage on Low Power Pins (Note 1)
1, 2, 3, 4, 6, 7, 8,
9, 10, 15, and 16
V
V
Control
Pin Maximum Input Voltage
5
−0.3, V
(Note 2)
V
Control(MAX)
Control(clamp)
Power Dissipation and Thermal Characteristics
P
Maximum Power Dissipation @ T = 70°C
550
145
mW
°C/W
D
A
R
Thermal Resistance Junction−to−Air
Operating Junction Temperature Range
Maximum Junction Temperature
q
J−A
T
−40 to +150
°C
°C
°C
°C
kV
V
J
T
150
−65 to +150
300
J(MAX)
S(MAX)
T
Storage Temperature Range
T
Lead Temperature (Soldering, 10 s)
ESD Capability, HBM model (Note 3)
ESD Capability, Machine Model (Note 3)
ESD Capability, Charged Device Model (Note 3)
L(MAX)
3
200
1000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. These maximum ratings (−0.3 V / 9.0 V) guarantee that the internal ESD Zener diode is not turned on. More positive and negative voltages
can be applied to the ZCD1 pin if the ESD Zener diode current is limited to 5 mA maximum. Typically, as detailed in the Zero Current Detection
section, an external resistor is to be placed between the ZCD1 pin and its driving voltage to limit the ZCD1 source and sink currents to 5 mA
or less. See Figure 2 and application note AND9654 for more details. The same is valid for the ZCD2 pin.
2. “V ” is the pin5 clamp voltage.
Control(clamp)
3. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
Charged Device Model Method 1000 V per JEDEC Standard JESD22−C101E
4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78F.
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2
NCP1632A
ZCD1 pin
RZCD1
IZCD1
ESD
Zener
Diode
V
ZCD1
Circuitry
AUX1
GND
NCP1632A
Figure 2. Limit the ZCD1 Pin Current (IZCD1) between – 5 mA and 5 mA (the Same is Valid for the ZCD2 Pin)
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE
(Conditions: V = 15 V, V
= 2 V, V = 0 V, T from −40°C, to +125°C, unless otherwise specified)
pin10 J
CC
pin7
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
V
Startup Threshold
Minimum Operating Voltage
V
V
increasing
decreasing
V
V
11
12
10
2.0
6.0
13
10.4
−
CC
CC(on)
9.4
1.5
4.0
CC
CC(off)
Hysteresis V
– V
V
V
CC(on)
CC(off)
CC(hyst)
CC(reset)
Internal Logic Reset
V
V
decreasing
= 9.4 V
7.5
CC
Startup Current
I
−
50
100
mA
CC
CC(start)
Supply Current
mA
Device Enabled/No Output Load on Pin6
Current that Discharges V in Latch Mode
F
= 130 kHz (Note 5)
I
−
–
−
−
3.5
0.4
0.4
−
7.0
0.8
0.8
2.6
sw
CC1
V
V
V
= 15 V, V
= 5 V
I
CC(latch)
I
CC(off)
CC
CC
CC
FB
pin10
Current that Discharges V in OFF Mode
= 15 V, pin 7 grounded
= 3 V
CC
SKIP Mode Consumption
I
CC(SKIP)
OSCILLATOR AND FREQUENCY FOLDBACK
Charge Current
Pin 6 open
Pin 6 open
I
120
90
−
140
105
1
154
115
−
mA
mA
-
CH
Maximum Discharge Current
I
DISCH
I
over I Ratio
I
I
= 30 mA
= 30 mA
R
FFOLD
CS
CS
CS
FFOLD30
FFOLD30
Pin 6 Source Current
I
28
−
30
5
32
−
mA
V
Oscillator Upper Threshold
Oscillator Lower Threshold
V
OSC(high)
V
FFOLD
V
FFOLD
V
FFOLD
V
FFOLD
V
FFOLD
= 4.2 V, V
falling
falling
rising
falling
falling
V
OSC(low)
3.6
3.6
2.7
1.8
0.8
4.0
4.0
3.0
2.0
1.0
4.4
4.4
3.3
2.2
1.1
V
FFOLD
FFOLD
FFOLD
FFOLD
FFOLD
= 3.8 V, V
= 3.8 V, V
= 2.0 V, V
= 0.8 V, V
Oscillator Swing (Note 6)
V
FFOLD
V
FFOLD
V
FFOLD
V
FFOLD
V
FFOLD
= 4.2 V, V
= 3.8 V, V
= 3.8 V, V
= 2.0 V, V
= 0.8 V, V
falling
falling
rising
falling
falling
V
OSC(swing)
0.90
0.90
1.90
2.85
3.80
1.00
1.00
2.00
3.00
4.00
1.05
1.05
2.10
3.15
4.20
V
FFOLD
FFOLD
FFOLD
FFOLD
FFOLD
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3
NCP1632A
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (continued)
(Conditions: V = 15 V, V
= 2 V, V = 0 V, T from −40°C, to +125°C, unless otherwise specified)
pin10 J
CC
pin7
Characteristics
CURRENT SENSE
Test Conditions
Symbol
Min
Typ
Max
Unit
Current Sense Voltage Offset
I
I
= 100 mA
= 10 mA
V
V
−20
−10
0
0
20
10
mV
mA
mA
pin9
CS(TH100)
CS(TH10)
pin9
Current Sense Protection Threshold
T = 25°C
T = −40°C to 125°C
I
I
199
190
210
210
228
228
J
ILIM1
J
ILIM2
Threshold for In−rush Current Detection
GATE DRIVE (Note 8)
I
11
14
17
in−rush
Drive Resistance
DRV1 Sink
DRV1 Source
DRV2 Sink
W
I
I
I
I
= 100 mA
= −100 mA
= 100 mA
= −100 mA
R
SNK1
R
SRC1
R
SNK2
R
SRC2
–
–
–
–
7
15
7
15
25
15
25
pin14
pin14
pin11
pin11
DRV2 Source
15
Drive Current Capability (Note 6)
DRV1 Sink
DRV1 Source
DRV2 Sink
DRV2 Source
mA
V
DRV1
V
DRV1
V
DRV2
V
DRV2
= 10 V
= 0 V
= 10 V
= 0 V
I
−
−
−
−
800
500
800
500
−
−
−
−
SNK1
I
SRC1
I
I
SNK2
SRC2
Rise Time
DRV1
DRV2
ns
ns
C
C
= 1 nF, V
= 1 nF, V
= 1 to 10 V
= 1 to 10 V
t
t
−
−
40
40
−
−
DRV1
DRV1
r1
DRV2
DRV2
r2
Fall Time
DRV1
DRV2
C
C
= 1 nF, V
= 1 nF, V
= 10 to 1 V
= 10 to 1 V
t
t
–
–
20
20
–
–
DRV1
DRV1
f1
DRV2
DRV2
f2
REGULATION BLOCK
Feedback Voltage Reference
Error Amplifier Source Current Capability
Error Amplifier Sink Current Capability
Error Amplifier Gain
V
2.44
−
2.50
−20
+20
200
2.56
−
V
REF
@ V
@ V
= 2.4 V
= 2.6 V
I
mA
pin2
EA(SRC)
I
−
−
pin2
EA(SNK)
G
115
285
mS
mA
EA
Control(boost)
Pin 5 Source Current when (V
Activated
Detect) is
pfcOK high
pfcOK low
I
175
55
220
70
265
85
out(low)
Pin2 Bias Current
Pin 5 Voltage
V
= 2.5 V
I
−500
500
nA
V
pin2
FB(bias)
@ V
@ V
= 2.4 V
V
V
−
−
2.8
3.6
0.6
3.0
−
−
3.5
pin2
Control(clamp)
= 2.6 V
V
pin2
Control(MIN)
Control(range)
Ratio (V
Ratio (V
Detect Threshold / V
) (Note 6) FB falling
V /V
out(low) REF
95.0
95.5
96.0
0.5
%
%
out(low)
REF
Detect Hysteresis / V
) (Note 6) FB rising
REF
H
/V
−
−
out(low)
out(low) REF
SKIP MODE
Duty Cycle
V
FB
= 3 V
D
MIN
−
−
0
%
RAMP CONTROL (VALID FOR THE TWO PHASES)
Maximum DRV1 and DRV2 On−Time
(FB Pin Grounded)
V
= 1.1 V, I
= 1.1 V, I
= 2.2 V, I
= 2.2 V, I
= 50 mA (Note 6)
= 200 mA
= 100 mA
t
t
t
t
14.5
1.00
3.80
0.34
19.5
1.35
5.00
0.41
22.5
1.60
6.00
0.50
ms
pin7
pin7
pin7
pin7
pin3
pin3
pin3
pin3
on1
on2
on3
on4
V
V
V
= 400 mA
Pin 3 Voltage
V
BO
V
BO
V
BO
V
BO
= V
= V
= V
= V
= 1.1 V, I
= 1.1 V, I
= 2.2 V, I
= 2.2 V, I
= 50 mA
= 200 mA
= 50 mA
= 200 mA
V
Rt1
V
Rt2
V
Rt3
V
Rt4
1.068 1.096 1.126
1.068 1.096 1.126
2.165 2.196 2.228
2.165 2.196 2.228
V
pin7
pin7
pin7
pin7
pin3
pin3
pin3
pin3
Maximum V Voltage
Not tested
V
5
V
ton
ton(MAX)
Rt(MAX)
Pin 3 Current Capability
I
1
−
−
mA
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4
NCP1632A
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (continued)
(Conditions: V = 15 V, V
= 2 V, V = 0 V, T from −40°C, to +125°C, unless otherwise specified)
pin10 J
CC
pin7
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
RAMP CONTROL (VALID FOR THE TWO PHASES)
Pin 3 Sourced Current Below which the
Controller is OFF
I
−
7
−
mA
mA
Rt(off)
Pin 3 Current Range
(Note 6)
I
20
1000
Rt(range)
ZERO VOLTAGE DETECTION CIRCUIT (VALID FOR ZCD1 AND ZCD2)
ZCD Threshold Voltage
ZCD Hysteresis
V
V
increasing
falling
V
V
0.40
0.20
0.50
0.25
0.60
0.30
V
ZCD
ZCD(TH),H
ZCD
ZCD(TH),L
V
ZCD
decreasing
V
−
0.25
−
V
V
ZCD(HYS)
Input Clamp Voltage
High State
Low State
I
I
= 5.0 mA
= −5.0 mA
V
V
9.0
11
13
pin1
ZCD(high)
−1.10 −0.65 −0.10
pin1
ZCD(low)
Internal Input Capacitance (Note 6)
ZCD Watchdog Delay
C
−
10
−
pF
ZCD
t
80
200
320
ms
ZCD
BROWN−OUT DETECTION
Brown−Out Comparator Threshold
Brown−Out Current Source
V
0.97
6
1.00
7
1.03
8
V
BO(TH)
I
mA
ms
ms
mV
BO
Brown−Out Blanking Time (Note 6)
Brown−Out Monitoring Window (Note 6)
t
38
38
−
50
62
62
−
BO(BLANK)
BO(window)
t
50
Pin 7 Clamped Voltage if V < V
BO(BLANK)
During
I
I
I
= −100 mA
= − 100 mA
= − 100 mA
V
965
BO
BO(TH)
pin7
pin7
pin7
BO(clamp)
t
Current Capability of the BO Clamp
Hysteresis V – V
I
100
10
−
35
−
−
60
−
mA
mV
mA
BO(clamp)
V
BO(TH)
BO(clamp)
BO(HYS)
Current Capability of the BO pin Clamp PNP
Transistor
I
100
BO(PNP)
Pin BO Voltage when Clamped by the PNP
OVER AND UNDER VOLTAGE PROTECTIONS
Over−Voltage Protection Threshold
V
0.35
0.70
0.90
V
BO(PNP)
V
2.425 2.500 2.575
V
%
OVP
Ratio (V
/ V ) (Note 6)
REF
V
/V
OVP REF
99.2
8
99.7
12
−
100.2
16
OVP
Ratio UVP Threshold over V
Pin 8 Bias Current
V
/V
UVP REF
%
REF
V
V
= 2.5 V, V
= 0.3 V
I
OVP(bias)
−500
500
nA
pin8
pin8
LATCH INPUT
Pin Latch Threshold for Shutdown
Pin Latch Bias Current
V
2.3
2.5
2.7
V
Latch
= 2.5 V
I
−500
−
500
nA
pin10
Latch(bias)
pfcOK / REF5V
Pin 15 Voltage Low State
Pin 15 Voltage High State
Current Capability
V
V
= 0 V, I
= 0 V, I
= 250 mA
V
−
4.7
5
60
5.0
10
120
5.3
−
mV
V
pin7
pin15
REF5V(low)
= 5 mA
V
pin7
pin15
REF5V(high)
I
mA
REF5V
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
(Note 6)
T
130
140
50
150
°C
°C
SHDN
T
−
−
SHDN(HYS)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
6. Not tested. Guaranteed by design.
7. Not tested. Guaranteed by design and characterization.
8. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically.
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5
NCP1632A
Table 3. DETAILED PIN DESCRIPTION
Pin number
Name
Function
1
ZCD2
This is the zero current detection pin for phase 2 of the interleaved PFC stage. It is designed to
monitor the voltage of an auxiliary winding to detect the inductor core reset and the valley of the
MOSFET drain source voltage
2
FB
This pin receives the portion of the PFC stage output voltage for regulation. V is also monitored by
FB
the dynamic response enhancer (DRE) which drastically speeds−up the loop response when the
output voltage drops below 95.5 % of the wished level.
3
4
5
R
The resistor placed between pin 3 and ground adjusts the maximum on−time in both phases, and
T
hence the maximum power that can be delivered by the PFC stage.
OSC
Oscillator pin. The oscillator sets the maximum switching frequency, particularly in medium− and
light−load conditions when frequency foldback is engaged.
V
The error amplifier output is available on this pin for loop compensation. The capacitors and resistor
connected between this pin and ground adjusts the regulation loop bandwidth that is typically set
below 20 Hz to achieve high Power Factor ratios. Pin5 is grounded when the circuit is off so that
when it starts operation, the power increases gradually (soft−start).
CONTROL
6
7
FFOLD
This pin sources a current proportional to the input current. Placing a resistor and a capacitor
(Freq. Foldback) between the FFOLD pin and GND, we obtain the voltage representative of the line current
magnitude necessary to control the frequency foldback characteristics.
BO
(Brown−out
Protection)
Apply an averaged portion of the input voltage to detect brown−out conditions when V drops
BO
below 1 V. A 50−ms internal delay blanks short mains interruptions to help meet hold−up time
requirements. When it detects a brown−out condition, the circuit stops pulsing and grounds the
“pfcOK” pin to disable the downstream converter. Also an internal 7−mA current source is activated
to offer a programmable hysteresis.
The pin2 voltage is internally re−used for feed−forward.
Ground pin 2 to disable the part.
8
9
OVP / UVP
CS
The circuit turns off when V
goes below V
(300 mV typically – UVP protection) and disables
pin8
UVP
the drive when the pin voltage exceeds V
(2.5 V typically − OVP protection).
OVP
The CS pin monitors a negative voltage proportional to the input current to limit the maximum
(Current Sense) current flowing in the phases. The NCP1632A also uses the CS information to prevent the PFC
stage from starting operation in presence of large in−rush currents.
10
Latch
DRV2
Apply a voltage higher than V
(2.5 V typically) to latch−off the circuit. The device is reset by
STDWN
unplugging the PFC stage (practically when the circuit detects a brown−out detection) or by forcing
the circuit V below V RST (4 V typically). Operation can then resume when the line is applied
CC
CC
back.
11
12
This is the gate drive pin for phase 2 of the interleaved PFC stage. The high−current capability of
the totem pole gate drive (+0.5/−0.8A) makes it suitable to effectively drive high gate charge power
MOSFETs.
V
CC
This pin is the positive supply of the IC. The circuit starts to operate when V exceeds 12 V and
CC
turns off when V goes below 10 V (typical values). After start−up, the operating range is 10.5 V
CC
up to 20 V.
13
14
GND
Connect this pin to the pre−converter ground.
DRV1
This is the gate drive pin for phase 1 of the interleaved PFC stage. The high−current capability of
the totem pole gate drive (+0.5/−0.8A) makes it suitable to effectively drive high gate charge power
MOSFETs.
15
16
REF5V / pfcOK
ZCD1
The pin15 voltage is high (5 V typically) when the PFC stage is in a normal, steady state situation
and low otherwise. This signal serves to “inform” the downstream converter that the PFC stage is
ready and that hence, it can start operation.
This is the zero current detection pin for phase 1 of the interleaved PFC stage. It is designed to
monitor the voltage of an auxiliary winding to detect the inductor core reset and the valley of the
MOSFET drain source voltage.
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6
NCP1632A
DRE
pfcOK
150 mA
COMP
Vref
VDD
Iref
Internal
Thermal
Shutdown
0.955*V
ref
+
Vcc
50 mA
Regul
−
TSD
VDD
Stdwn
UVP
FB
Error Amplifier
−
Vcc_OK
+/−20 mA
BO_NOK
+
V
ref
V
CC(on)
/ V
Vcontrol
CC(off)
UVLO
OFF
Fault
management
SKIP
OVLflag1
BO_NOK
V
OPAMP
OFF
4R
BO
OCP
V
Brown−out detection
with 50−ms delay
REGUL
STOP
V
3V
5R
BO
OVP
OFF
V
OSC(low)
SKIP
CLK2
Vcc
Output
Buffer 2
DRV2
S
Oscillator low
threshold
control
Vpwm2
Freq foldback
DT
Vton
Q
L
R
processing
circuitry
pwm2
V
OPAMP
STOP
V
Vton
BO
DRV1
DRV2
CLK1
Vcc
Output
Buffer 1
DRV1
Generation of the
charge current for the
Internal timing
S
Rt
Vpwm1
I
Q
Vpwm1
Vpwm2
ch
On−time control
for the two phases
L
R
pwm1
capacitors
(max on−time setting for
the twophases)
STOP
In−rush
CLK1
V
Oscillator block
with interleaving and
frequency foldback
In−rush
DMG2
OSC
CLK2
V
ZCD1
Zero
current
ZCD2
V
V
V
ZCD2
All the RS latches are
RESET dominant
OSC(low)
detection
for phase 2
ZCD1
OUTon2
REF5V
V
DMG1
V
pfcOK
ZCD1
pfcOK / REF5V
OFF
Stup
Zero
current
ZCD1
DT
OFF
S
R
detection
for phase 1
Q
OUTon1
Lstup
OVLflag1
Current Sense Block
−
OVP
UVP
(Building of I
CS
proportional to I
)
in
+
V
UVP
OCP
Ics > I
ILIM1
Ics
+
OVP
CS
−
−
V
In−rush
OVP
+
Ics > I
in−rush
Vcc < VccRST
Q
R
zcd1
stdwn
Q
Q
−
V
zcd2
DRV
GND
STDWN
Lstdwn
S
latch−off
1
+
DRV
2
Figure 3. Block Diagram
www.onsemi.com
7
NCP1632A
DETAILED OPERATING DESCRIPTION
Introduction
• Output Stage Totem Pole: the NCP1632A incorporates
a −0.5 A / +0.8 A gate driver to efficiently drive most
TO220 or TO247 power MOSFETs.
• Safety Protections: the NCP1632A permanently
monitors the input and output voltages, the inductor
current and the die temperature to protect the system from
possible over−stresses and make the PFC stage extremely
robust and reliable. In addition to the aforementioned
OVP protection, one can list:
The NCP1632A is an interleaving, 2−phase PFC
controller. It is designed to operate in critical conduction
mode (CrM) in heavy load conditions and in discontinuous
conduction mode (DCM) with frequency foldback in light
load for an optimized efficiency over the whole power
range. In addition, the circuit incorporates protection
features for a rugged operation. More generally, the
NCP1632A functions make it the ideal candidate in systems
where cost−effectiveness, reliability, low stand−by power,
high−level efficiency over the load range and near−unity
power factor are the key parameters:
• Accurate and robust interleaving management:
The NCP1632A modulates the oscillator swing as a
function of the current cycle duration to control the delay
between the two branches drive pulses. This ON
proprietary method is a simple but robust and stable
solution to interleave the two branches. The 180−degree
phase shift is ensured in all situations (including transient
phases) and whatever the operation mode is (CrM or
DCM).
♦ Maximum Current Limit: the circuit permanently
senses the input current for over current protection and
in−rush currents detection, for preventing the
excessive stress suffered by the MOSFETs if they
turned on when large in−rush currents take place.
♦ Zero Current Detection: the NCP1632A prevents the
MOSFET from closing until the inductor current is
zero, to ensure discontinuous conduction mode
operation in each branch.
♦ Under−Voltage Protection: the circuit turns off when
it detects that the output voltage goes below 12% of the
OVP level (typically). This feature protects the PFC
stage from starting operation in case of too low ac line
conditions or in case of a failure in the OVP monitoring
network (e.g., bad connection).
♦ Brown−Out Detection: the circuit detects too low ac
line conditions and stop operating in this case. This
protection protects the PFC stage from the excessive
stress that could damage it in such conditions.
♦ Thermal Shutdown: an internal thermal circuitry
disables the circuit gate drive and then keeps the power
switch off when the junction temperature exceeds
150°C typically. The circuit resumes operation once
the temperature drops below about 100°C (50°C
hysteresis).
• Frequency fold−back and skip−cycle capability for
low power stand−by:
The NCP1632A optimizes the efficiency of your PFC
stage over the whole load range. In medium− and
light−load conditions, the switching frequency can
linearly decay as a function of the line current magnitude
(FFOLD mode) down to about 30 kHz at very low power
(depending on the OSC pin capacitor). To prevent any risk
of regulation loss at no load and to further minimize the
consumed power, the circuit skips cycles when the error
amplifier output reaches its low clamp level.
• Fast Line / Load Transient Compensation:
by essence, PFC stages are slow systems. Thus, the output
voltage of PFC stages may exhibit excessive over− and
under−shoots because of abrupt load or input voltage
variations (e.g. at start−up). The NCP1632A incorporates
a fast line / load compensation to avoid such large output
voltage variations. Practically, the circuit monitors the
output voltage and:
Interleaving
An interleaved PFC converter consists of two paralleled
PFC stages operated out−of−phase. Each individual stage is
generally termed phase, channel or branch.
If the input current is well balanced, each phase processes
half the total power. The size and cost of each individual
branch is hence accordingly minimized and losses are
spitted between the two channels. Hence, hot spots are less
likely to be encountered. Also, if the interleaving solution
requires more components, they are smaller and often more
standard. In addition, they can more easily fit applications
with specific form−factors as required in thin flat panel TVs
for instance.
Furthermore, if the two channels are properly operated
out−of−phase, a large part of the switching−frequency ripple
currents generated by each individual branch cancel when
they add within the EMI filter and the bulk capacitors. As a
result, EMI filtering is significantly eased and the bulk
capacitor rms current is drastically reduced. Interleaving
♦ Disables the drive to stop delivering power as long as
the output voltage exceeds the over voltage protection
(OVP) level.
♦ Drastically speeds−up the regulation loop (Dynamic
Response Enhancer) when the output voltage is below
95.5 % of its regulation level. This function is partly
disabled during the startup phase to ensure a gradual
increase of the power delivery (soft−start).
• PFC OK: the circuit detects when the circuit is in normal
situation or if on the contrary, it is in a start−up or fault
condition. In the first case, the pfcOK pin is in high state
and low otherwise. The pfcOK pin serves to control the
downstream converter operation in response to the PFC
state.
www.onsemi.com
8
NCP1632A
therefore extends the CrM power range by sharing the task
actually be extremely cost−effective and efficient for
powers above 300 watts. And even less for applications like
LCD and Plasma TV applications where the need for smaller
components, although more numerous, helps meet the
required low−profile form−factors.
between the two phases and by allowing for a reduced input
current ripple and a minimized bulk capacitor rms current.
This is why this approach which at first glance, may
appear more costly than the traditional 1−phase solution can
Branch 1
IL1
I
D 1
Vin
Iin
Acline
Branch 2
IL 2
I
D 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I
line
I
D(tot)
V
cc
Vout
EMI
Filter
Cbulk
Cin
LOAD
Rsense
Figure 4. Interleaved PFC Stage
The NCP1632A manages the 180−degree phase shift
between the two branches by modulating the oscillator
swing as a function of the current cycle duration in the
inductor of each individual phase. This onsemi proprietary
technique ensures an accurate, stable and robust control of
the delay between the two branches in all situations
(including transient phases) and whatever the operation
mode is (CrM or DCM).
The ac line current is the averaged inductor current as the
result of the EMI filter “polishing” action. Hence, the line
current produced by one of the phase is:
t1(t1 ) t2)
2T L
I
in + Vin
(eq. 2)
Where (T = t + t + t ) is the switching period and V is
1
2
3
in
the ac line rectified voltage.
The NCP1632A is a voltage mode controller. As a result,
the input current is optimally shared between the two
branches if they have an inductor of same value. If the
inductances differ, out−of−phase operation will not be
affected. Simply, the branch embedding the lowest−value
inductor, will process more power as:
Pbranch1 Lbranch2
+
Pbranch2 Lbranch1
(eq. 1)
Figure 5. Current Cycle Within a Branch
Inductor typical deviation being below 5%, the power
between 2 branches should not differ from more than 10%.
Provided its interleaving capability, the protections it
features and the medium− to light−load efficiency
enhancements it provides compared to traditional CrM
circuits, the NCP1632A is more than recommendable for
powers up to 600 W with universal mains and up to 1 kW in
narrow mains applications.
Equation 2 shows that the input current is proportional to
t1ꢀ(t1 ) t2
the input voltage if ǒ Ǔis a constant.
T
This is what the NCP1632A does. Using the “Vton
processing block” of Figure 5, the NCP1632A modulates t1
t1ꢀ(t1 ) t2
so that ǒ Ǔremains a constant:
T
NCP1632A On−time Modulation
The NCP1632A incorporates an on−time modulation
circuitry to support both the critical and discontinuous
conduction modes. Figure 5 portrays the inductor current
absorbed in one phase of the interleaved PFC stage. The
initial inductor current of each switching cycle is always
zero. The inductor current ramps up when the MOSFET is
Ct @ VREGUL
t1(t1 ) t2)
+
T
It
(eq. 3)
Where C and I respectively, are the capacitor and charge
t
t
current of the internal ramp used to control the on−time and
is the signal derived from the regulation block
V
REGUL
which adjusts the on−time. This onsemi proprietary
technique makes the NCP1632A able to support the
Frequency Clamped Critical conduction mode of operation,
that is, to operate in discontinuous− or in critical−conduction
mode according to the conditions, without degradation of
on. The slope is (V /L) where L is the inductor value. At the
IN
end of the on−time (t ), the coil demagnetization phase
1
starts. The current ramps down until it reaches zero. The
duration of this phase is (t ). The system enters then the
2
dead−time (t ) that lasts until the next clock is generated.
3
www.onsemi.com
9
NCP1632A
the power factor. Critical conduction mode is naturally
Feedforward:
obtained when the inductor current cycle is longer than the
minimum period controlled by the oscillator. Discontinuous
conduction mode is obtained in the opposite situation. In this
case, the switching frequency is clamped.
The C timing capacitors (one per phase) are internal and
are well matched for an optimal current balancing between
the two branches of the interleaved converter.
t
As detailed in the brown−out section, the I current is
t
Hence, the averaged current absorbed by one of the phase
of the PFC converter:
internally processed to be proportional to the square of the
voltage applied to the BO pin (pin 7). Since the BO pin is
designed to receive a portion of the average input voltage,
Ct @ VREGUL
Vin
2L
I
in(phase1) + Iin(phase2)
+
@
the I current is proportional to the square of the line
t
It
(eq. 4)
magnitude which provides feedforward.
In a typical application, the BO pin voltage is hence:
Given the regulation low bandwidth of PFC systems,
(V ) and then (V ) are slow varying signals.
CONTROL
REGUL
Ǹ
2 2 Vin(rms)
Rbo2
bo1 ) Rbo2
Hence, the line current absorbed by each phase is:
Vpin7
+
p
R
I
in(phase1) + Iin(phase2) + k @ Vin
(eq. 9)
(eq. 5)
where R and R are the scaling down resistors for BO
bo1
bo2
VREGULAR
ƪ
ƫ
Where k is a constant k + Ct @
@ L @ It .
sensing (see brown−out section)
In addition, I is programmed by the pin 3 resistor so that
2
t
Hence, the input current is then proportional to the input
voltage and the ac line current is properly shaped.
This analysis is valid for DCM but also CrM which is just
the maximum on−time obtained when V
is max
REGUL
(1.66 V) is given by:
Rt2
a particular case of this functioning where (t = 0). As a
3
Ton,max (ms) ^ 50 @ 10*9
@
2
result, the NCP1632A automatically adapts to the
conditions and jumps from DCM and CrM (and vice versa)
without power factor degradation and without discontinuity
in the power delivery.
Vpin7
(eq. 10)
From this, we can deduce the input current and power
expressions:
2
62 @ 10*14 @ Rt2
L @ Vin(rms)
The total current absorbed by the two phases is then:
Rbo1
@ ǒ1 ) Ǔ @
Rbo2
VREGUL
VREGUL(max)
Iin(rms)
^
Ct @ V
Iin(total)
+
REGUL @ Vin
L @ It
(eq. 11)
(eq. 6)
2
Rbo1
This leads to the following line rms current and average
input power:
62 @ 10*14 @ Rt2
VREGUL
VREGUL(max)
@ ǒ1 ) Ǔ @
Rbo2
Pin(avg)
^
L
Ct @ V
Iin(rms)
+
REGUL @ Vin(rms)
(eq. 12)
L @ It
(eq. 7)
(eq. 8)
Ct @ V
2
Pin(avg)
+
REGUL @ Vin(rms)
L @ It
PWM
comparator
timing capacitor
saw−tooth
+
to PWM latch
−
Vton
OA1
V
REGUL
+
SKIP
R1
−
OVP
OFF
S3
C1
OCP
0.5*
V
BOcomp
(from BO block)
(Isense
− 210 m)
IN1
S1
pfcOK
S2
−> Vton during (t1+t2)
In−rush
DT
(high during dead−time)
−> 0 V during t3 (dead−time)
−> Vton*(t1+t2)/T in average
Figure 6. Vton Processing Circuit
www.onsemi.com
10
NCP1632A
Regulation Block and Low Output Voltage Detection
The swing of the error amplifier output is limited within
an accurate range:
A trans−conductance error amplifier with access to the
inverting input and output is provided. It features a typical
trans−conductance gain of 200 mS and a typical capability of
20 mA. The output voltage of the PFC stage is typically
scaled down by a resistors divider and monitored by the
inverting input (feed−back pin – pin2). The bias current is
minimized (less than 500 nA) to allow the use of a high
impedance feed−back network. The output of the error
amplifier is pinned out for external loop compensation
(pin5). A type−2 compensator is generally applied between
pin5 and ground, to set the regulation bandwidth in the range
of 20 Hz, as need in PFC applications (refer to application
note AND8407).
• It is maintained above a lower value (V – 0.6 V typically)
F
by the “low clamp” circuitry. When this circuitry is
activated, the power demand is minimum and the
NCP1632A enters skip mode (the controller stops
pulsating) until the clamp is no more active.
• It is clamped not to exceed 3.0 V + the same V voltage
F
drop.
Hence, V
features a 3 V voltage swing. V
is then
pin5
pin5
offset down by (V ) and divided by three before it connects
F
to the “V
processing block” and the PWM section.
ton
Finally, the output of the regulation is a signal (“V
”
REGUL
of the block diagram) that varies between 0 and 1.66 V.
Dynamic Response Enhancer
pfcOK
Vout low
150 mA
detect
−
50 mA
VREGUL
+
0.955*Vref
1.66 V
Error Amplifier
FB
−
20 mA
+
Vref
OFF
Vcontrol
+
V
F
+
4R
VCONTROL
V
F
V
REGUL
3 V
5R
VF
3 V +VF
Figure 7. Regulation Block
Figure 8. VREGUL versus VCONTROL
Zero Current Detection
Provided the low bandwidth of the regulation loop, sharp
variations of the load, may result in excessive over and
under−shoots. Over−shoots are limited by the Over−Voltage
Protection (see OVP section). A dynamic Response
Enhancer circuitry (DRE) is embedded to contain the
under−shoots. Practically, an internal comparator monitors
While the on time is constant, the core reset time varies
with the instantaneous input voltage. The NCP1632A
detects the demagnetization completion by sensing the
inductor voltage. Sensing the voltage across the inductor
allows an accurate zero current detection, more specifically,
by detecting when the inductor voltage drops to zero.
Monitoring the inductor voltage is not an economical
solution. Instead, a smaller winding is taken off of the boost
inductor. This winding (called the “zero current detection”
or ZCD winding) gives a scaled version of the inductor
voltage that is easily usable by the controller. Furthermore,
this ZCD winding is coupled so that it exhibits a negative
voltage during the MOSFET conduction time (flyback
configuration) as portrayed by Figure 9.
the feed−back signal (V ) and connects a 200 mA current
FB
source to speed−up the charge of the compensation network
when VFB is lower than 95.5% of its nominal value. Finally,
it is like if the comparator multiplied the error amplifier gain
by about 10.
One must note that a large part of the DRE current source
(150mA out of 200 mA) cannot be enabled until the converter
output voltage has reached its target level (that is when the
“pfcOK” signal of the block diagram, is high). This is
because, at the beginning of operation, it is generally
welcome that the compensation network charges slowly and
gradually for a soft start−up.
In that way, the ZCD voltage (“V
”) falls and starts to
AUX
ring around zero volts when the inductor current drops to
zero. The NCP1632A detects this falling edge and prevents
any new current cycle until it is detected.
www.onsemi.com
11
NCP1632A
Figure 9 shows how it is implemented.
below zero (below the 0.25 V lower threshold of the ZCD
comparator to be more specific). As a result, the ZCD
For each phase, a ZCD comparator detects when the
voltage of the ZCD winding exceeds its upper threshold (0.5
V typically). When this is the case, the coil is in
circuitry detects the V
falling edge.
AUX
It is worth noting that as portrayed by Figure 10, V
is
AUX
demagnetization phase and the latch L
is set. This latch
also representative of the MOSFET drain−source voltage
ZCD
is reset when the next driver pulse occurs. Hence the output
of this latch (Q ) is high during the whole off−time
(“V ”). More specifically, when V
is minimal (below the input voltage V ). That is why V
is below zero, V
DS
AUX DS
ZCD
IN
ZCD
(demagnetization time + any possible dead time). The
output of the comparator is also inverted to form a signal
is used to enable the driver so that the MOSFET turns on
when its drain−source voltage is low. Valley switching
reduces the losses and interference.
which is AND’d with the Q
output so that the AND gate
ZCD
output (V
) turns high when the V
voltage goes
ZCD
AUX
Rzcd2
Rzcd1
D1
1
ZCD1
16
ZCD2
Vin
L1
AND1
V
DMG1
PWM
latch
PH1
Vzcd1
SET1
+
Vcc
Qzcd1
S
−
Negative
and
positive
clamp
Negative
and
positive
clamp
DRV1
Q
S
L
ZCD
Q
Q
ZCD
0.5 V
CLK1
(from phase
management
block)
M1
14
R
R
output
buffe r 1
In−rush
200−ms
delay
reset signal
(from PH1 PWM
comparator)
DT
S
R
Q
Vout
D2
OFF
L2
Vin
(from Fault
management
block)
V
DMG2
output
PWM
latch PH2
Vzcd2
SET2
buffe r 2
Vcc
+
−
DRV2
M2
Qzcd2
CLK2
(from phase
management
block)
S
S
R
Cbulk
Q
Q
Cbulk
11
R
0.5 V
In−rush
reset signal
(from PH2 PWM comparator)
Figure 9. Zero Current Detection
At startup or after an inactive period (because of a
protection that has tripped for instance), there is no energy
in the ZCD winding and therefore no voltage signal to
activate the ZCD comparator. This means that the driver will
never turn on. To avoid this, an internal watchdog timer is
integrated into the controller. If the driver remains low for
To prevent negative voltages on the ZCD pins (ZCD1 for
phase 1 and ZCD2 for phase 2), these pins are internally
clamped to about 0 V when the voltage applied by the
corresponding ZCD winding is negative. Similarly, the ZCD
pins are clamped to V
(10 V typical), when the
ZCD(high)
ZCD voltage rises too high. Because of these clamps, a
resistor (R and R of Figure 9) is necessary to limit
more than 200 ms (typical), the timer sets the L
latch as
ZCD
ZCD1
ZCD2
the current from the ZCD winding to the ZCD pin. The
clamps are designed to respectively source and sink 5 mA.
the ZCD winding signal would do. Obviously, this 200 ms
delay acts as a minimum off−time if there is no
demagnetization winding voltage is detected.
It is hence recommended to dimension R
and R
to
ZCD1
ZCD2
limit the ZCD1 and ZCD2 pins current below 5 mA.
www.onsemi.com
12
NCP1632A
DRV
time
V
IN
V
DS
time
time
V
AUX
CLOCK
time
Q
ZDC
time
time
V
ZCD
DT
time
Figure 10. Zero Current Detection Timing Diagram
(VAUX is the Voltage Provided by the ZCD Winding)
Current Sense
The NCP1632A is designed to monitor a negative voltage
proportional to the input current, i.e., the current drawn by
Figure 11, a current sense resistor (R ) is practically
inserted in the return path to generate a negative voltage
CS
the two interleaved branches (I ). As portrayed by
(V ) proportional to I .
CS in
in
VAUX2
V
Iin
in
VOUT
VAUX1
L2
D2
EMI
filter
ICS
OCP
C
IN
L1
D1
IILIM1
Current
Mirror
M2
DRV
2
ICS
In−rush
ICS
M1
DRV
1
Iin−rush
CBULK
CS
(QZCD1 and
ZCD2 are
from the
QZCD 2
QZCD 1
9
Q
Negative clamp
ICS
DRV2
ZCD block)
DRV1
ROCP
RCS
Iin
Figure 11. Current Sense Block
www.onsemi.com
13
NCP1632A
The NCP1632A uses V to detect when I exceeds its
particularly if no in−rush limiting circuitry is implemented.
CS
in
maximum permissible level. To do so, as sketched by
Figure 11, the circuit incorporates an operational amplifier
that sources the current necessary to maintain the CS pin
The power switches should not turn on during this severe
transient. If not, they may be over−stressed and finally
damaged. That is why, the NCP1632A permanently
monitors the input current and delays the MOSFET start of
voltage near zero. By inserting a resistor R
between the
OCP
CS pin and R , we adjust the current that is sourced by the
switching until (I ) has vanished. This is the function of the
CS
in
CS pin (I ) as follows:
I
comparison to the I
threshold (14 mA typical).
CS
CS
in−rush
When I
exceeds I
, the comparator output
CS
in−rush
ǒ
Ǔ
ǒ
Ǔ
* RCS @ Iin ) ROCP @ ICS ^ 0
(eq. 13)
(“In−rush”) is high and prevents the PWM latches from
setting (see block diagram). Hence, the two drivers (DRV1
and DRV2) cannot turn high and the MOSFETs stay off.
This is to guarantee that the MOSFETs remain open as long
as if the input current exceeds 10% of the maximum current
limit. Again, this feature protects the MOSFETs from the
possible excessive stress it could suffer from if it was
allowed to turn on while a huge current flowed through the
coil as it can be the case at start−up or during an over−load
transient.
Which leads to:
RCS
ROCP
ICS
+
Iin
(eq. 14)
In other words, the CS pin sources a current (I ) which
is proportional to the input current.
Two functions use I : the over current protection and the
in−rush current detection.
CS
CS
Over−Current Protection (OCP)
The propagation delay (I < I
) to (drive outputs
CS
in−rush
If I exceeds I
(210 mA typical), an over−current is
CS
ILIM1
high) is in the range of few ms.
detected and the on−time is decreased proportionally to the
difference between the sensed current I and the 210 mA
OCP threshold.
The on−time reduction is done by injecting a current I
in the negative input of the “V
OPAMP. (See Figure 6)
However when the circuit starts to operate, the
NCP1632A disables this protection to avoid that the current
produced by one phase and sensed by the circuit prevents the
other branch from operating. Practically, some logic
grounds the In−rush protection output when it detects the
presence of “normal current cycles”. This logic simply
consists of the OR combination of the Drive and
demagnetization signals as sketched by Figure 11.
in
neg
processing circuit”
TON
I
CS * IILIM1
Ineg
+
(eq. 15)
2
This current is injected each time the OCP signal is high.
Over−Voltage Protection
The maximum coil current is:
While PFC circuits often use one single pin for both the
Over−Voltage Protection (OVP) and the feed−back, the
NCP1632A dedicates one specific pin for the under−voltage
and over−voltage protections. The NCP1632A
configuration allows the implementation of two separate
feed−back networks (see Figure 13):
ROCP
RCS
Iin(max)
+
IILIM1
(eq. 16)
In−rush Current Detection
When the PFC stage is plugged to the mains, the bulk
capacitor is abruptly charged to the line voltage. The charge
current (named in−rush current) can be extremely huge
1. One for regulation applied to pin 2.
2. Another one for the OVP function (pin 8).
Vout (bulk voltage)
Vout (bulk voltage)
Rout1
Rout1
16
15
14
13
12
11
10
9
1
2
16
15
14
13
12
11
10
9
1
FB
FB
2
3
4
5
6
7
3
4
5
6
7
Rout3
Rout2
Rovp1
Rovp2
Rout2
OVP
OVP
8
8
Figure 12. Configuration with One Feed−back
Figure 13. Configuration with Two
Network for Both OVP and Regulation
Separate Feed−back Networks
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14
NCP1632A
Oscillator Section – Phase Management
The oscillator generates the clock signal that dictates the
The double feed−back configuration (Figure 13) offers
some up−graded safety level as it protects the PFC stage
even if there is a failure of one of the two feed−back
arrangements. In this case:
maximum switching frequency (f ) of the interleaved PFC
osc
stage. In other words, each of the two interleaved branches
cannot operate above half the oscillator frequency (f /2).
osc
The bulk regulation voltage (“V
”) is:
out(nom)
The oscillator frequency (f ) is adjusted by the capacitor
osc
R
out1 ) R
Rout2
Vout(nom)
+
out2 @ Vref
applied to OSC pin (pin 4). Typically, a 220 pF capacitor
approximately leads to a 260 kHz oscillator operating
frequency, i.e., to a 130 kHz clamp frequency for each
branch.
As shown by Figure 14, a current source I (140 mA
typically) charges the OSC pin capacitor until its voltage
(eq. 17)
The OVP level (“V ”) is:
out(ovp)
R
ovp1 ) Rovp2
CH
Vout(ovp)
+
@ Vref
Rovp2
(eq. 18)
exceeds V
(5 V typically). At that moment, the
OSC(high)
Where V is the internal reference voltage (2.5 V typically)
Now, if wished, one single feed−back arrangement is
possible as portrayed by Figure 12. The regulation and OVP
ref
oscillator enters a discharge phase for which I
(105 mA
DISCH
typ.) discharges the OSC pin capacitor. This sequence lasts
until V goes below the oscillator low threshold V
OSC
OSCL
blocks having the same reference voltage (V ), the
ref
and a new charging phase starts*. An internal signal
(“SYNC” of Figure 14) is high during the discharge phase.
A divider by two uses the SYNC information to manage the
phases of the interleaved PFC: the first SYNC pulse sets
“phase 1”, the second one, “phase 2”, the third one phase 1
again… etc.
According to the selected phase, SYNC sets the relevant
“Clock generator latch” that will generate the clock signal
(“CLK1” for phase 1, “CLK2” for phase 2) when SYNC
drops to zero.
resistance ratio R
over R
adjusts the OVP threshold.
out2
out3
More specifically,
The bulk regulation voltage (“V
”) is:
out(nom)
R
out1 ) Rout2 ) R
Vout(nom)
+
out3 @ Vref
R
out2 ) Rout3
(eq. 19)
(eq. 20)
The OVP level (“V
”) is:
out(ovp)
R
out1 ) Rout2 ) R
Vout(ovp)
+
out3 @ Vref
Rout2
Actually, the drivers cannot turn on at this very moment
if the inductor demagnetization is not complete. In this case,
the clock signal is maintained high and the discharge time is
The ratio OVP level over regulation level is:
Vout(ovp)
Rout3
Rout2
+ 1 )
prolonged although V
is below V
, until when the
OSC
OSCL
Vout(nom)
(eq. 21)
core being reset, the drive pin turns high. The prolonged
OSC discharge ensures a substantial 180−degree phase shift
in CrM, out−of−phase operation being in essence,
guaranteed in DCM. In the two conditions (CrM or DCM),
the interleaved operation is stable and robust.
For instance, (V
= 105% ⋅ V ) leads to:
out(nom)
out(nom)
(R
out3
= 5% ⋅ R ).
out2
When the circuit detects that the output voltage exceeds
the OVP level, it maintains the power switch open to stop the
power delivery.
*As detailed in the following sections, V
is V
−
OSCL
OSC(low)
4 V typically − by default to set the frequency clamp level
used in heavy−load conditions. V is varied between 1
OSCL
and 3 V in FFOLD mode (frequency foldback mode) in
response the FFOLD pin voltage.
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15
NCP1632A
DRV1
SYNCbar
R
ICH
CLK1
Generation
latch
5 V
SYNC
CLK1
OSC
Q
S
S
COSC
OSC
latch
Q_ph1
SYNCbar
Phase1
Q
R
DRV2
divider
by two
R
CLK2
Generation
latch
CLK2
Phase2
Q
S
IDISCH
Q_ph1
SYNCbar
4 V
VOSCL
ICS (from CS block)
FFOLD mode
Control
of the
oscillator
low
FFOLD
1 V and 3 V
clamps
1 V
3 V
threshold
( VOSCL
)
HFC
mode
FFOLD
mode
+
−
4 V / 3 V
Figure 14. FFOLD Mode Management
If a capacitorC
frequency is provided by:
is applied to the OSC pin, the oscillator
significant dead−time and prevent transitions between CrM
and DCM within the input voltage sinusoid.
OSC
In Figure 15 a) configuration, a single oscillator sets a
60 @ 10*6
fosc
^
C
OSC ) (10 @ 10*12
)
frequency clamp. For instance, C
= 220 pF forces
OSC
(eq. 22)
120 kHz to be the maximum frequency within each branch
(the FFOLD mode reduces this level in light load
conditions). Such a clamp value is likely to force DCM
operation in part of the input voltage sinusoid. To be able to
force full CrM operation over a large working range, we
And the switching frequency of each individual branch is
clamped to the following f
:
clamp
30 @ 10*6
fosc
2
fclamp
+
^
C
OSC ) (10 @ 10*12
)
(eq. 23)
would need to reduce C
to a very low value (if not, the
OSC
clamp frequency can be lower than the switching one
leading to DCM operation near the line zero crossing in
particular). Still however, the oscillator must keep able to
keep synchronized to the current cycle for proper
out−of−phase control. This requires the oscillator swing to
not to exceed its 1 V to 5 V range even in heavy load
conditions when the switching frequency in each individual
branch generally drops below 100 kHz. This is generally not
possible with a single small capacitor on the OSC pin.
Recommended Configuration
As detailed above, the circuit automatically transitions
between CrM and DCM depending on the current cycle
duration being longer or shorter than the clamp frequency
set by the oscillator. However, these transitions can lead to
small discontinuities of the line current. To avoid them, the
circuit should be operated in CrM without frequency−clamp
interference when the line current is high and in deep DCM
when it is below a programmed level. Deep DCM means that
the switching frequency is low enough to ensure a
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16
NCP1632A
OSC pin
OSC pin
OSC pin
ROSC
COSC
ROSC
(e.g., 5.1 kW)
COSC
(e.g., 82 pF)
(e.g., 5.1 kW)
(e.g., 68 pF)
COSC
(e.g., 220 pF)
CFF
(e.g., 270 pF)
CFF
(e.g., 330 pF)
a) Basic configuration
b) Option 1
c) Option 2
Figure 15. External Components Driving the OSC Pin
Instead, the schematic of either Figure 15 b) or
Figure 15 c) is to be used where:
• C sets the frequency in light load where the frequency
FF
foldback can force deep DCM operation (deep DCM
means operation with a large dead−time to be far from the
zone where the circuit can transition from CrM to DCM
• C
(which value is much less than the second
OSC
capacitance C ) sets the high−frequency operation
FF
necessary for operating in CrM
and vice versa). As previously mentioned, C also
FF
ensures that the oscillator voltage can stay above 1 V in
deep CrM conditions.
• R
limits the influence of the C capacitor as long as
OSC
FF
the oscillator swing remains below (R
.I
) where
OSC OSC
I
is the charge or discharge current depending on the
being limited by
OSC
Finally, Figure 15 b) and c) configurations provide some
kind of variable−capacitance oscillator. For instance, Option
b) provides the following typical characteristics:
sequence. The voltage across C
R
much−higher−value capacitor (C ) is engaged when
OSC
(to about 1 V with 5.1 kW), the second
OSC
FF
heavy−load CrM operation imposes a larger oscillator
swing.
1
vramp
1
vramp
7.00
5.00
7.00
5.00
5 V
5 V
1
1
3 V
4 V
3.00
3.00
ms
Tbranch ^3.3
ms
Tbranch ^13.6
1.00
1.00
−1.00
−1.00
396u
398u
400u
time in seconds
402u
404u
392u
396u
400u
time in seconds
404u
408u
300 kHz frequency clamp in HFC
mode (V > 4 V)
73 kHz frequency clamp when entering
FFOLD mode (V
= 3 V)
FFOLD
FFOLD
1
vramp
7.00
5.00
5 V
3.00
1
1 V
1.00
ms
Tbranch ^36
−1.00
360u
380u
400u
420u
440u
time in seconds
28 kHz minimum frequency clamp (deepest
DCM @ V = 1 V)
FFOLD
Figure 16. Clamp Frequency in Each Individual Branch with the Configuration of Figure 15 b)
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17
NCP1632A
Figure 17 illustrates the oscillator operation at a low
FFOLD voltage.
3
IL1
VDS1
2
7
7.00
VDS2
IL2
6
5
5 V
5.00
VOSC
8
3.00
9
1.00
VFFOLD forces the OSC valley
V
is in the range of 1.1 V
FFOLD
4
−1.00
FFOLD / HFC Flag (high in FFOLD mode)
9.50m
9.54m
9.58m
time in seconds
9.62m
9.66m
Figure 17. Operation at a Low VFFOLD Value (VFFOLD = 1.1 V)
HFC vs FFOLD Modes
The transitions between the HFC and FFOLD modes and
the frequency foldback characteristics are controlled by the
FFOLD pin.
The NCP1632A optimizes the PFC stage efficiency over
the whole load range by entering the frequency foldback
(FFOLD) mode when the line current magnitude is lower
than a programmed level (see next section). More
specifically, the circuit operates in:
• Frequency foldback (FFOLD) mode when the line
current magnitude is lower than a programmed level. In
this mode, the circuit frequency clamp level is reduced as
a function of the FFOLD pin voltage in order to reduce the
frequency in medium− and light−load operation. The
frequency can decrease down to about 30 kHz at very low
power (depending on the OSC pin capacitor)
• High frequency clamp (HFC) mode when the line current
is high. In this mode, the clamp level of the switching
frequency is set high so that the PFC stage mostly runs in
critical conduction mode which is more efficient than the
discontinuous conduction mode in heavy load conditions.
Frequency Foldback (FFOLD) Management
As detailed in the “current sense” section, the NCP1632A
CS pin sources a current proportional to the input current
(I of Figure 14). I is internally copied and sourced out
CS
CS
of the FFOLD pin. This current is changed into a dc voltage
by means of an external (R//C) network applied to the
FFOLD pin. The obtained V
voltage is proportional to
FFOLD
the line average current. As illustrated by Figure 18, the PFC
stage enters the frequency foldback mode (FFOLD mode)
when
V
goes below 3.0 V, and recovers
FFOLD
high−frequency clamp mode (HFC mode) when the FFOLD
voltage exceeds 4 V.
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18
NCP1632A
V
V
OUT
IN
I
IN
EMI
Filter
PFC Stage
C
IN
R
SENSE
I
IN
I
CS
Current Mirror
R
CS
Low−pass filter to
build a signal
proportional to
the average input
current
I
I
CS
CS
CS
I
CS
9
(ICS is
proportional
to the total
input current)
Negative clamp
Oscillator low
FFOLD
6
threshold control
HFC
mode
FFOLD
mode
+
−
4 V / 3 V
Figure 18. Frequency Foldback Control
In HFC mode, the oscillator lower threshold (V
) is
• 60% load at 270 V rms
OSCL
fixed and equal to V
In FFOLD mode, V
voltage as follows:
(4 V typically).
OSC(low)
The PFC stage will recover HFC mode (V
• 27% load at 90 V rms
= 4 V) at:
FFOLD
is modulated by the FFOLD pin
if V is between 1 and 3 V
FFOLD
OSCL
• 81% load at 270 V rms
• V
• V
• V
= V
= 1 V if V
= 3 V if V
OSCL
OSCL
OSCL
FFOLD
Above values assume a ripple−free V
voltage. The
FFOLD
is below 1 V
exceeds 3 V
FFOLD
power thresholds for transition can be shift and the
hysteresis reduced by the V ripple.
At the transition between the two modes, the oscillator
low threshold is 3 V. In the example of Figure 19, this leads
the branch clamp frequency to be 73 kHz when entering and
just before leaving the FFOLD mode.
FFOLD
FFOLD
As an example, the FFOLD external resistor can be
= 3 V) when the line current
selected so that (V
FFOLD
threshold is equal to 20% of the maximum current.
In a 90 to 270 V rms application, above criterion leads the
PFC stage to enter FFOLD mode at:
• 20% load at 90 V rms
Figure 19 shows a “natural” transition FFOLD to HFC
mode.
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19
NCP1632A
7
6
VDS1
IL1
7.00
IL2
VDS2
5
2
5 V
3 V
VOSC
5.00
4
1
3.00
VFFOLD exceeds the 4 V threshold
1.00
DCM operation
CrM operation
−1.00
FFOLD / HFC Flag (high in FFOLD mode)
3
8.44m
8.48m
8.52m
8.56m
8.60m
time in seconds
Figure 19. “Natural” Transition FFOLD to HFC Mode when VFFOLD exceeds 4 V
HFC−mode Recovery
able to provide the full power. To solve this, the NCP1632A
forces HFC operation whenever the DRE comparator trips*
and remains in HFC mode until the output voltage recovers
its regulation level (that is when OVLFlag1 of Figure 21
turns low). At that moment, the conduction mode is
normally selected as a function of the FFOLD pin voltage.
See Figure 20.
The FFOLD pin sources a current proportional to the input
current. Placing a resistor and a capacitor between the
FFOLD and GND pins, we obtain the voltage representative
of the line current magnitude necessary to control the
frequency foldback characteristics. The NCP1632A
naturally leaves the FFOLD mode operation when the
sensed input current being large enough, the FFOLD pin
*The dynamic response enhancer (DRE) comparator trips
when the output voltage drops below 95.5% of its
regulation level.
voltage (V
) exceeds 4 V. Such a FFOLD to HFC
FFOLD
transition is shown by Figure 19.
DRE
Skip Mode of Operation
The circuit enters skip mode when the regulation block
HFC mode
S
Q
Q
5
2
output (V
) drops to its 0.6 V lower clamp level. At
CONTROL
very light load and low line conditions, on−times can be
short enough no to enter the low−consumption skip mode.
To prevent such an inefficient continuous operation from
occurring, the NCP1632A forces a minimum on−time which
corresponds to 10% the maximum on−time.
R6
100k
R
OVLFlag1
3
(high when V < V
)
FB
REF
This does not mean that the PFC stage will enter skip
mode when the load is less than 10% of the full load (or even
much more considering the necessary headroom in the max
Figure 20. Easing HFC−mode Recovery
Now, the FFOLD pin is heavily filtered and this time
on−time setting when selecting R ). Since, the NCP1632A
constant may cause long V
settling phases. If while in
t
FFOLD
reduces the switching frequency in light load (FFOLD
mode), this minimum on−time corresponds to much lower
power levels, typically, in the range of 2% of the full power.
very light−load conditions, the load abruptly rises, the
FFOLD pin time constant may dramatically delay the
HFC−mode recovery. As a result, during the FFOLD mode
of operation, the PFC stage may run in DCM and may not be
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20
NCP1632A
♦ Excessive die temperature detected by the thermal
shutdown.
♦ Under−Voltage Protection (“UVP” high)
♦ Brown−out situation (“BONOK” high)
♦ Latching−off of the circuit by an external signal
applied to pin 10 and exceeding 2.5 V (“STDWN” of
the block diagram turns high).
Low Clamp
♦ Too low the current sourced by the R pin (“R
”)
t(open)
t
• During the PFC stage start−up, that is, until the output
voltage reaches its regulation level. The start−up phase is
detected by the latch “L ” of the block diagram.
STUP
“L ” is in high state when the circuit enters or recovers
STUP
Figure 21. VCONTROL Low Clamp
operation after one of above major faults and resets when
the error amplifier stops charging its output capacitor, that
is, when the output voltage of the PFC stage has reached
its desired regulation level. At that moment, “STUP” falls
down to indicate the end of the start−up phase.
The circuit consumption is minimized (below 1 mA) for
a skipping period of time.
PfcOK / REF5V Signal
The NCP1632A can communicate with the downstream
converter. The signal “pfcOK/REF5V” is high (5 V) when
the PFC stage is in nominal operation and low otherwise.
More specifically, “pfcOK/REF5V” is low:
Finally, “pfcOK/REF5V” is high when the PFC output
voltage is properly and safely regulated. “pfcOK/REF5V”
should be used to allow operation of the downstream
converter.
• Whenever a major fault condition is detected which turns
off the circuit, i.e.:
Brown−Out Protection
The brown−out pin is designed to receive a portion of the
♦ Incorrect feeding of the circuit (“UVLO” high). The
UVLO signal turns high when V
drops below
CC
input voltage (V ). As V is a rectified sinusoid, a capacitor
IN
IN
V
(10 V typically) and remains high until V
CC(OFF)
CC
must be applied to the BO pin so that V is proportional to
BO
exceeds V
(12 V typically).
CC(ON)
the average value of V .
IN
Feed−Forward
Circuitry
Current Mirror
Rt
I
BO
Vbo (BO pin voltage)
Rt
Vbo
IBO2 charges the timing
I
BO
V
in
capacitorforbothphases of
the interleaved PFC
Ac line
BO−COMP
EMI
Filter
R
R
Vbo
VBO−COMP (high when VBO < 1 V)
bo1
bo2
1 V
BO
BO_NOK
C
in
T
S
delay
2
S
C
bo
R
cs
50−ms
50−ms
delay
L
Q
BO
delay
R
Vdd
980 mV
reset
reset
reset
7 mA
This PNP transistor maintains
the BO pin below the BO
threshold when the circuit is
not fed enough to control the
state of the BO block
Circuitry for
S
1
brown−out
detection
Figure 22. Brown−out Block
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21
NCP1632A
The BO pin voltage is used by two functions (refer to
Figure 22):
• The line lower threshold is:
R
bo1 ) R
Rbo2
p
(Vin,rms
)
+
@
bo2 @ VBO(th)
boL
• Feedforward. Generation of an internal current
Ǹ
2 2
proportional to the input voltage average value (I ). V
Rt
BO
Hence the ratio upper over lower
is:
@ǒ1 )
thǓreshold
is buffered and made available on the R pin (pin 3).
t
(Vin,rms
)
R
bo1 @ Rbo2 @ IBO
2
p
Hence, placing a resistor between pin 3 and ground,
enables to adjust a current proportional to the average
boH
boL
+
(Vin,rms
)
(Rbo1 ) Rbo2 @ VBO(th)
input voltage. This current (I ) is internally copied and
As in general R
is large compared to R , the
Rt
bo1
bo2
squared to form the charge current for the internal timing
capacitor of each phase. Since this current is proportional
to the square of the line magnitude, the conduction time
is made inversely proportional to the line magnitude. This
feed−forward feature makes the transfer function and the
power delivery independent of the ac line level. Only the
precedent equation can simplify as follows:
(Vin,rms
)
R
bo2 @ IBO
2
boH
boL
@ǒ1 ) Ǔ
^
p
VBO(th)
(Vin,rms
)
Details of Operation of the Circuitry for Brown−out
Detection
regulation output (V
) controls the power amount.
In nominal operation, the voltage applied to pin 7 must be
higher than the 1 V internal voltage reference. In this case,
REGUL
Note that if the I current is too low (below 7 mA
Rt
the output of the comparator BO−COMP (V
) is
typically), the controller goes in OFF mode to avoid
damaging the MOSFETs with too long conduction time.
BO−COMP
low (see Figure 22). Conversely, if V goes below 1 V,
BO
V
turns high and a 980 mV voltage source is
In particular, this addresses the case when the R pin is
BO−COMP
t
connected to the BO pin to maintain the pin level near 1 V.
The high state of V is used to detect a brown−out
condition. However, the brown−out detection is not
open.
BO−COMP
• Brown−out protection. A 7 mA current source lowers the
BO pin voltage when a brown−out condition is detected.
This is for hysteresis purpose as required by this function.
In traditional applications, the monitored voltage can be
very different depending on the phase:
immediate. First, as soon as a high level occurs, this
information is stored by a latch (L of Figure 22) and a
BO
50 ms delay is activated. No BO fault can be detected until
this time has elapsed. The main goal of the 50 ms lag is to
help meet the hold−up requirements. In case of a short mains
interruption, no fault is detected and hence, the “pfcOK”
signal remains high and does not disable the downstream
converter. In addition, the BO pin voltage being kept at
980 mV, there is almost no extra delay between the line
♦ Before operation, the PFC stage is off and the input
bridge acts as a peak detector (refer to Figure 23). As
a consequence, the input voltage is approximately flat
and nearly equates the ac line amplitude:
Ǹ
vinꢀ(t) + 2 @ Vin,rms, where V
is the rms voltage
in,rms
of the line. Hence, the voltage applied to the BO pin
Rbo2
(pin 7) is: VBO + 2 @ Vin,rms
recovery and the occurrence of the steady state V voltage,
BO
Ǹ
which otherwise would exist because of the large capacitor
typically placed between pin7 and ground to filter the input
voltage ripple. As a result, the NCP1632A effectively
“blanks” any mains interruption that is shorter than 38 ms
(minimum guaranteed value of the 50 ms timer).
At the end of this 50 ms blanking delay, another timer is
activated that sets a 50 ms window during which a fault can
be detected. This is the role of the second 50 ms timer of
Figure 22:
• If the output of OPAMP is high at the end of the first delay
(50 ms blanking time) and before the second 50 ms delay
time is elapsed, a brown−out fault is detected (BO_NOK
is high).
@
.
R
bo1 ) Rbo2
♦ After the PFC stage has started operation, the input
voltage becomes a rectified sinusoid and the voltage
Ǹ
2 2 @ Vin,rms
Rbo2
applied to pin7 is: VBO
+
@
,
p
R
bo1 ) Rbo2
i.e., about 64% of the previous value. Therefore, the
same line magnitude leads to a V voltage which is
36% lower when the PFC is working than when it is
off. That is why a large hysteresis (in the range of 50%
of the upper threshold) is required.
BO
Other applications may require a different hysteresis
amount. That is why the hysteresis is made programmable
and dependent on the internal 7 mA current source. More
specifically, re−using the components of Figure 22:
• If the output of OPAMP remains low for the duration of
the second delay, no fault is detected.
• The
line
upper
BO
threshold
is:
In any case, the L latch and the two delays are reset at
the end of the second delay.
When the “BO_NOK” signal is high, the driver is
BO
R
bo1 ) Rbo2
Rbo2
R
bo1 @ Rbo2 @ IBO
1
ǒ
Ǔ
(Vin,rms
)
+
@
VBO(th) )
boH
Ǹ
R
bo1 ) Rbo2
2
disabled, the “V ” pin is grounded to recover operation
control
where V
is the BO comparator threshold (1 V
BO(th)
with a soft−start when the fault has gone and the “pfcOK”
typically) and I , the 7 mA current source.
BO
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22
NCP1632A
voltage turns low to disable the downstream converter. In
addition, both 50 ms timers are reset, the 980 mV clamp is
removed (S is off) and I , the 7 mA current source, is
enabled to lower the pin7 voltage for hysteresis purpose (as
explained above).
to guarantee that the circuit starts operation in the right state,
that is, “BONOK” high. When V exceedsV , the pnp
transistor turns off and the circuit enables the 7 mA current
source. The 7 mA current source remains on until the BO pin
voltage exceeds the 1 V BO threshold.
CC
CC(on)
2
BO
A pnp transistor ensures that the BO pin voltage remains
below the 1 V threshold until V reaches V
. This is
CC
CC(on)
Figure 23. Typical Input Voltage of a PFC Stage
Output Drive Section
Thermal Shutdown (TSD)
An internal thermal circuitry disables the circuit gate drive
and then keeps the power switch off when the junction
temperature exceeds 140°C typically. The output stage is
then enabled once the temperature drops below about 80°C
(60°C hysteresis).
The circuit embeds two drivers to control the two
interleaved branches. Each output stage contains a totem
pole optimized to minimize the cross conduction current
during high frequency operation. The gate drive is kept in a
sinking mode whenever the Under−Voltage Lockout
(UVLO) is active or more generally whenever the circuit is
off. Its high current capability (−500 mA/+800 mA) allows
it to effectively drive high gate charge power MOSFET.
The temperature shutdown keeps active as long as the
circuit is not reset, that is, as long as V keeps higher than
CC
V
. The reset action forces the TSD threshold to be
CC(reset)
the upper one (140°C). This ensures that any cold start−up
will be done with the right TSD level.
Reference Section
The circuit features an accurate internal reference voltage
(V ). V
is optimized to be 2.4% accurate over the
Under−Voltage Lockout Section
REF
REF
The NCP1632A incorporates an Under−Voltage Lockout
block to prevent the circuit from operating when the power
supply is not high enough to ensure a proper operation. An
temperature range (the typical value is 2.5 V). V
voltage reference used for the regulation and the
over−voltage protection. The circuit also incorporates a
is the
REF
UVLO comparator monitors the pin 12 voltage (V ) to
precise current reference (I
)
that allows the
CC
REF
allow the NCP1632A operation when V exceeds 12 V
Over−Current Limitation to feature a 6% accuracy over
CC
typically. The comparator incorporates some hysteresis
the temperature range.
(2.0 V typically) to prevent erratic operation as the V
CC
Fault Mode
The following block details the function.
crosses the threshold. When V goes below the UVLO
CC
comparator lower threshold, the circuit turns off.
The circuit off state consumption is very low: < 50 mA.
This low consumption enables to use resistors to charge
the V capacitor during the start−up without the penalty of
CC
a too high dissipation.
www.onsemi.com
23
NCP1632A
Internal
Thermal
Shutdown
Vref
Vcc
VDD
Regul
TSD
Iref
Stdwn
UVP
Vcc_OK
BO_NOK
Rt(open)
UVLO
+
−
12 V / 10 V
Q
R
S
30−ms
blanking
time
IRt_Low
(Ipin3 < 7 mA)
OFF
Fault
management
Figure 24. Fault Management Block
The circuit detects a fault if the R pin is open. Practically,
• Under−Voltage Protection (“UVP”)
• Latch−off condition (“Stdwn”)
• Die over−temperature (“TSD”)
t
if the pin sources less than 7 mA, the “I ” signal sets a
Rt_Low
latch that turns off the circuit if its output (R ) is high.
t(open)
A 30 ms blanking time avoids parasitic fault detections. The
• Too low the current sourced by the R pin (“R
”)
t(open)
t
latch is reset when the circuit is in UVLO state (too low V
levels for proper operation).
CC
• “UVLO” (improper Vcc level for operation)
When any of the following faults is detected:
• brown−out (“BO_NOK”)
The circuit turns off. It recovers operation when the fault
disappears.
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24
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
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