NCP1608_10 [ONSEMI]
Critical Conduction Mode PFC Controller Utilizing a Transconductance Error Amplifier; 临界导通模式PFC控制器利用一个跨导误差放大器
| 型号： | NCP1608_10 |
| 厂家： | 
ONSEMI |
| 描述： | Critical Conduction Mode PFC Controller Utilizing a Transconductance Error Amplifier |
| 文件： | 总24页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1608
Critical Conduction Mode
PFC Controller Utilizing a
Transconductance Error
Amplifier
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MARKING
The NCP1608 is an active power factor correction (PFC)
controller specifically designed for use as a pre−converter in ac−dc
adapters, electronic ballasts, and other medium power off−line
converters (typically up to 350 W). It uses critical conduction mode
(CrM) to ensure near unity power factor across a wide range of input
voltages and output power. The NCP1608 minimizes the number of
external components by integrating safety features, making it an
excellent choice for designing robust PFC stages. It is available in a
SOIC−8 package.
DIAGRAM
8
8
1
1608B
ALYW
G
SOIC−8
D SUFFIX
CASE 751
1
A
L
= Assembly Location
= Wafer Lot
General Features
• Near Unity Power Factor
• No Input Voltage Sensing Requirement
• Latching PWM for Cycle−by−Cycle On Time Control (Voltage
Mode)
• Wide Control Range for High Power Application (>150 W) Noise
Immunity
• Transconductance Error Amplifier
• High Precision Voltage Reference ( 1.6% Over the Temperature
Range)
Y
W
G
= Year
= Work Week
= Pb−Free Package
PIN CONNECTION
FB
Control
Ct
V
CC
DRV
GND
ZCD
CS
(Top View)
ORDERING INFORMATION
• Very Low Startup Current Consumption (≤ 35 mA)
• Low Typical Operating Current Consumption (2.1 mA)
• Source 500 mA / Sink 800 mA Totem Pole Gate Driver
• Undervoltage Lockout with Hysteresis
• Pin−to−Pin Compatible with Industry Standards
• This is a Pb−Free and Halide−Free Device
†
Device
Package
Shipping
NCP1608BDR2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Safety Features
• Overvoltage Protection
• Undervoltage Protection
• Open/Floating Feedback Loop Protection
• Overcurrent Protection
• Accurate and Programmable On Time Limitation
Typical Applications
• Solid State Lighting
• Electronic Light Ballast
• AC Adapters, TVs, Monitors
• All Off−Line Appliances Requiring Power Factor Correction
©
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
June, 2010 − Rev. 3
NCP1608/D
NCP1608
V
in
L
V
out
D
N :N
B
ZCD
LOAD
(Ballast,
R
ZCD
SMPS, etc.)
V
CC
R
NCP1608
out1
+
8
7
6
5
+
1
2
3
4
C
in
V
CC
FB
C
bulk
EMI
Filter
M
AC Line
Control
Ct
DRV
GND
ZCD
R
out2
CS
C
COMP
C
t
R
sense
Figure 1. Typical Application
OVP
+
−
V
CC
+
+
V
CC
V
out
V
OVP
UVLO
+
-
V
DD
UVP
POK
−
+
V
DDGD
+
C
bulk
R
R
out1
V
DD
Reg
V
UVP
(Enable EA)
FB
E/A
−
mV
DD
+
g
m
out2
D
+
R
FB
V
REF
Fault
Haversine
Control
V
Control
L
V
in
V
EAH
C
COMP
Clamp
N :N
POK
B
ZCD
V
DD
PWM
I
charge
−
C
t
Add Ct
Offset
+
C
t
S Q
M
DRV
CS
OCP
R
Q
+
LEB
V
−
V
CC
+
V
R
ILIM
sense
UVLO
DRV
GND
Demag
+
−
S Q
S Q
+
R
Q
R
Q
ZCD(ARM)
V
DDGD
+
Reset
Off Timer
mV
−
+
mV
DD
ZCD
S Q
V
ZCD(TRIG)
R
ZCD
R
Q
ZCD Clamp
S Q
DD
R
Q
POK
All SR Latches are Reset Dominant
Figure 2. Block Diagram
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2
NCP1608
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Function
1
FB
The FB pin is the inverting input of the internal error amplifier. A resistor divider scales the output voltage to V
to main-
REF
tain regulation. The feedback voltage is used for overvoltage and undervoltage protections. The controller is disabled
when this pin is forced to a voltage less than V , a voltage greater than V , or floating.
UVP
OVP
2
Control The Control pin is the output of the internal error amplifier. A compensation network is connected between the Control pin
and ground to set the loop bandwidth. A low bandwidth yields a high power factor and a low Total Harmonic Distortion (THD).
3
Ct
The Ct pin sources a current to charge an external timing capacitor. The circuit controls the power switch on time by com-
paring the Ct voltage to an internal voltage derived from V
end of the on time.
. The Ct pin discharges the external timing capacitor at the
Control
4
CS
The CS pin limits the cycle−by−cycle current through the power switch. When the CS voltage exceeds V
, the drive
ILIM
turns off. The sense resistor that connects to the CS pin programs the maximum switch current.
5
6
7
8
ZCD
GND
DRV
The voltage of an auxiliary winding is sensed by this pin to detect the inductor demagnetization for CrM operation.
The GND pin is analog ground.
The integrated driver has a typical source impedance of 12 W and a typical sink impedance of 6 W.
V
CC
The V pin is the positive supply of the controller. The controller is enabled when V exceeds V and is disabled
CC(on)
CC
CC
CC
when V decreases to less than V
.
CC(off)
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
FB Voltage
V
−0.3 to 10
10
FB
FB
FB Current
I
mA
V
Control Voltage
Control Current
Ct Voltage
V
−0.3 to 6.5
−2 to 10
−0.3 to 6
10
Control
Control
I
mA
V
V
Ct
Ct Current
I
Ct
mA
V
CS Voltage
V
−0.3 to 6
10
CS
CS
CS Current
I
mA
V
ZCD Voltage
ZCD Current
DRV Voltage
DRV Sink Current
DRV Source Current
Supply Voltage
Supply Current
V
−0.3 to 10
10
ZCD
ZCD
I
mA
V
V
−0.3 to V
800
DRV
DRV(sink)
CC
I
mA
mA
V
I
500
DRV(source)
V
CC
−0.3 to 20
20
I
mA
mW
°C/W
CC
2
Power Dissipation (TA = 70°C, 2.0 Oz Cu, 55 mm Printed Circuit Copper Clad)
P
D
450
Thermal Resistance Junction−to−Ambient
(2.0 Oz Cu, 55 mm Printed Circuit Copper Clad)
Junction−to−Air, Low conductivity PCB (Note 3)
Junction−to−Air, High conductivity PCB (Note 4)
2
R
R
R
178
168
127
q
JA
JA
JA
q
q
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
T
−40 to 125
150
°C
°C
°C
°C
J
T
J(MAX)
T
−65 to 150
300
STG
Lead Temperature (Soldering, 10 s)
T
L
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Pins 1– 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.
2. This device contains Latch−Up protection and exceeds ± ±100 mA per JEDEC Standard JESD78.
2
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
2
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
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3
NCP1608
Table 3. ELECTRICAL CHARACTERISTICS
V
= 2.4 V, V
= 4 V, Ct = 1 nF, V = 0 V, V
= 0 V, C
= 1 nF, V = 12 V, unless otherwise specified
FB
Control
CS
ZCD
DRV CC
(For typical values, T = 25°C. For min/max values, T = −40°C to 125°C, unless otherwise specified)
J
J
Characteristic
Test Conditions
Symbol
Min
Typ
Max
Unit
STARTUP AND SUPPLY CIRCUITS
Startup Voltage Threshold
V
Increasing
Decreasing
V
11
8.8
2.2
−
12
9.5
2.5
24
12.5
10.2
2.8
V
V
CC
CC(on)
Minimum Operating Voltage
Supply Voltage Hysteresis
V
CC
V
CC(off)
H
V
UVLO
cc(startup)
Startup Current Consumption
0 V < V < V
− 200 mV
I
35
mA
mA
CC
CC(on)
No Load Switching
Current Consumption
C
DRV
= open, 70 kHz Switching,
I
−
1.4
1.7
cc1
V
= 2 V
CS
Switching Current Consumption
70 kHz Switching, V = 2 V
I
−
−
2.1
2.6
mA
mA
CS
cc2
Fault Condition Current Consumption
No Switching, V = 0 V
I
0.75
0.95
FB
cc(fault)
OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
Overvoltage Detect Threshold
Overvoltage Hysteresis
V
= Increasing
V
/V
105
20
−
106
60
108
100
800
%
mV
ns
FB
OVP REF
V
OVP(HYS)
Overvoltage Detect Threshold
Propagation Delay
V
= 2 V to 3 V ramp,
dV/dt = 1 V/ms
t
500
FB
OVP
V
= V
to V
= 10%
FB
OVP
DRV
Undervoltage Detect Threshold
V
= Decreasing
V
0.25
100
0.31
200
0.4
V
FB
UVP
Undervoltage Detect Threshold
Propagation Delay
V
= 1 V to 0 V ramp,
t
300
ns
FB
UVP
dV/dt = 10 V/ms
= V to V = 10%
UVP
V
FB
DRV
ERROR AMPLIFIER
Voltage Reference
T = 25°C
T = −40°C to 125°C
V
REF
2.475
2.460
2.500
2.500
2.525
2.540
V
J
J
Voltage Reference Line Regulation
Error Amplifier Current Capability
V
CC(on)
+ 200 mV < V < 20 V
V
−10
−
10
mV
CC
REF(line)
V
FB
= 2.6 V
I
6
10
10
20
20
30
mA
EA(sink)
V
FB
= 1.08*V
I
EA(sink)OVP
REF
V
FB
= 0.5 V
I
−250
−210
−110
EA(source)
Transconductance
V
FB
= 2.4 V to 2.6 V
gm
mS
T = 25°C
T = −40°C to 125°C
90
70
110
110
120
135
J
J
Feedback Pin Internal Pull−Down
Resistor
V
FB
= V
to V
R
FB
2
4.6
10
MW
UVP
REF
Feedback Bias Current
Control Bias Current
V
= 2.5 V
I
0.25
−1
5
0.54
−
1.25
1
mA
mA
V
FB
FB
V
= 0 V
I
Control
FB
Maximum Control Voltage
I
= 10 mA,
REF
V
EAH
5.5
6
Control(pullup)
V
FB
= V
Minimum Control Voltage to Generate
Drive Pulses
V
= Decreasing until
Ct
0.37
4.5
0.65
4.9
0.88
5.3
V
V
Control
DRV
(offset)
V
is low, V = 0 V
Ct
Control Voltage Range
V
– Ct
V
EA(DIFF)
EAH
(offset)
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NCP1608
Table 3. ELECTRICAL CHARACTERISTICS (Continued)
= 2.4 V, V = 4 V, Ct = 1 nF, V = 0 V, V = 0 V, C
V
= 1 nF, V = 12 V, unless otherwise specified
CC
FB
Control
CS
ZCD
DRV
(For typical values, T = 25°C. For min/max values, T = −40°C to 125°C, unless otherwise specified)
J
J
Characteristic
Test Conditions
Symbol
Min
Typ
Max
Unit
RAMP CONTROL
Ct Peak Voltage
V
V
= open
= open
V
4.775
235
4.93
275
5.025
297
V
Control
Ct(MAX)
On Time Capacitor Charge Current
I
mA
Control
= 0 V to V
charge
V
Ct
Ct(MAX)
Ct Capacitor Discharge Duration
PWM Propagation Delay
V
= open
t
−
−
50
150
220
ns
ns
Control
Ct(discharge)
V
Ct
= V
−100 mV to 500 mV
Ct(MAX)
dV/dt = 30 V/ms
= V
to V
t
130
PWM
V
Ct
− Ct
Control (offset)
= 10%
DRV
CURRENT SENSE
Current Sense Voltage Threshold
Leading Edge Blanking Duration
V
0.45
100
40
0.5
190
100
0.55
350
170
V
ILIM
V
= 2 V, V
= 90% to 10%
t
ns
ns
CS
DRV
LEB
Overcurrent Detection Propagation
Delay
dV/dt = 10 V/ms
= V to V = 10%
t
CS
CS
V
CS
ILIM
DRV
Current Sense Bias Current
ZERO CURRENT DETECTION
ZCD Arming Threshold
ZCD Triggering Threshold
ZCD Hysteresis
V
CS
= 2 V
I
−1
−
1
mA
V
ZCD
= Increasing
V
1.25
0.6
500
− 2
9.8
−0.9
−
1.4
0.7
700
−
1.55
0.83
900
+ 2
V
V
ZCD(ARM)
V
ZCD(TRIG)
V
ZCD
= Decreasing
V
mV
mA
V
ZCD(HYS)
ZCD Bias Current
V
ZCD
= 5 V
I
ZCD
Positive Clamp Voltage
Negative Clamp Voltage
ZCD Propagation Delay
I
= 3 mA
V
10
12
ZCD
ZCD
CL(POS)
CL(NEG)
I
= −2 mA
V
−0.7
100
−0.5
170
V
V
ZCD
= 2 V to 0 V ramp,
t
ns
ZCD
dV/dt = 20 V/ms
to V
V
ZCD
= V
= 90%
DRV
ZCD(TRIG)
Minimum ZCD Pulse Width
t
−
70
−
ns
SYNC
Maximum Off Time in Absence of ZCD
Transition
Falling V
= 10% to
DRV
t
75
165
300
ms
DRV
start
Rising V
= 90%
DRIVE
Drive Resistance
I
= 100 mA
= 100 mA
R
R
OL
−
−
12
6
20
13
W
source
OH
I
sink
Rise Time
10% to 90%
90% to 10%
t
−
−
−
35
25
−
80
70
ns
ns
V
rise
Fall Time
t
fall
out(start)
Drive Low Voltage
V
CC
= V
−200 mV,
V
0.2
CC(on)
I
= 10 mA
sink
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NCP1608
TYPICAL CHARACTERISTICS
107.0
106.5
106.0
80
70
60
105.5
105.0
50
40
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. Overvoltage Detect Threshold vs.
Junction Temperature
Figure 4. Overvoltage Hysteresis vs. Junction
Temperature
0.330
7
6
5
4
3
2
0.325
0.320
0.315
0.310
0.305
0.300
1
0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. Undervoltage Detect Threshold vs.
Junction Temperature
Figure 6. Feedback Pin Internal Pull−Down
Resistor vs. Junction Temperature
2.54
2.53
2.52
2.51
2.50
2.49
2.48
100
50
0
Device in UVP
−50
−100
−150
−200
−250
2.47
2.46
−50 −25
0
25
50
75
100
125
150
0
0.5
1.0
, FEEDBACK VOLTAGE (V)
FB
1.5
2.0
2.5
3.0
T , JUNCTION TEMPERATURE (°C)
V
J
Figure 7. Reference Voltage vs. Junction
Temperature
Figure 8. Error Amplifier Output Current vs.
Feedback Voltage
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NCP1608
TYPICAL CHARACTERISTICS
16
14
12
10
220
V
= 2.6 V
FB
215
210
205
200
195
190
8
6
V
FB
= 0.5 V
185
180
−50 −25
0
25
50
75
100 125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. Error Amplifier Sink Current vs.
Junction Temperature
Figure 10. Error Amplifier Source Current vs.
Junction Temperature
200
180
160
140
120
100
80
200
125
180
160
140
120
100
80
120
115
110
105
100
95
Phase
Transconductance
R
Control
C
Control
= 100 kW
= 2 pF
60
60
V
FB
= 2.5 Vdc, 1 Vac
40
40
V
CC
= 12 V
90
85
T = 25°C
A
20
0
20
0
1000
−50 −25
0
25
50
75
100
125 150
0.01
0.1
1
10
100
T , JUNCTION TEMPERATURE (°C)
J
f, FREQUENCY (kHz)
Figure 11. Error Amplifier Transconductance
vs. Junction Temperature
Figure 12. Error Amplifier Transconductance
and Phase vs. Frequency
1.0
278
276
274
272
270
0.9
0.8
0.7
0.6
0.5
268
0.4
0.3
266
264
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Minimum Control Voltage to Generate
Drive Pulses vs. Junction Temperature
Figure 14. On Time Capacitor Charge Current
vs. Junction Temperature
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NCP1608
TYPICAL CHARACTERISTICS
6.0
5.5
5.0
170
160
150
140
130
120
4.5
4.0
110
100
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. Ct Peak Voltage vs. Junction
Temperature
Figure 16. PWM Propagation Delay vs.
Junction Temperature
0.520
0.515
0.510
0.505
0.500
0.495
220
210
200
0.490
190
180
0.485
0.480
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 17. Current Sense Voltage Threshold
vs. Junction Temperature
Figure 18. Leading Edge Blanking Duration vs.
Junction Temperature
190
185
180
175
170
165
160
18
16
14
12
10
8
R
OH
R
OL
6
4
155
150
2
0
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 19. Maximum Off Time in Absence of
ZCD Transition vs. Junction Temperature
Figure 20. Drive Resistance vs. Junction
Temperature
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NCP1608
TYPICAL CHARACTERISTICS
13
12
26
24
22
20
18
V
CC(on)
11
10
V
CC(off)
9
8
16
14
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. Supply Voltage Thresholds vs.
Junction Temperature
Figure 22. Startup Current Consumption vs.
Junction Temperature
2.16
2.14
2.12
2.10
2.08
2.06
2.04
2.02
2.00
−50 −25
0
25
50
75
100 125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. Switching Current Consumption vs.
Junction Temperature
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NCP1608
Introduction
• Overcurrent Protection (OCP). The inductor peak
current is accurately limited on a cycle-by-cycle basis.
The maximum inductor peak current is adjustable by
modifying the current sense resistor. An integrated
LEB filter reduces the probability of noise
The NCP1608 is a voltage mode, power factor correction
(PFC) controller designed to drive cost−effective
pre-converters to comply with line current harmonic
regulations. This controller operates in critical conduction
mode (CrM) suitable for applications up to 350 W. Its
voltage mode scheme enables it to obtain near unity power
factor without the need for a line-sensing network. A high
precision transconductance error amplifier regulates the
output voltage. The controller implements comprehensive
safety features for robust designs.
inadvertently triggering the overcurrent limit.
• Shutdown Feature. The PFC pre-converter is shutdown
by forcing the FB pin voltage to less than V . In
UVP
shutdown mode, the I current consumption is
CC
reduced and the error amplifier is disabled.
Application Information
The key features of the NCP1608 are:
Most electronic ballasts and switching power supplies
use a diode bridge rectifier and a bulk storage capacitor to
produce a dc voltage from the utility ac line (Figure 24).
This DC voltage is then processed by additional circuitry
to drive the desired output.
• Constant On Time (Voltage Mode) CrM Operation. A
high power factor is achieved without the need for
input voltage sensing. This enables low standby power
consumption.
• Accurate and Programmable On Time Limitation. The
NCP1608 uses an accurate current source and an
external capacitor to generate the on time.
• Wide Control Range. In high power applications (>
150 W), inadvertent skipping can occur at high input
voltage and high output power if noise immunity is
not provided. The noise immunity provided by the
NCP1608 prevents inadvertent skipping.
• High Precision Voltage Reference. The error amplifier
reference voltage is guaranteed at 2.5 V 1.6% over
process and temperature. This results in accurate
output voltages.
Rectifiers
Converter
AC
Line
+
Bulk
Load
Storage
Capacitor
Figure 24. Typical Circuit without PFC
This rectifying circuit consumes current from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. This occurs near the line voltage peak and the
resulting current is non-sinusoidal with a large harmonic
content. This results in a reduced power factor (typically <
0.6). Consequently, the apparent input power is higher than
the real power delivered to the load. If multiple devices are
connected to the same input line, the effect increases and
a “line sag” is produced (Figure 25).
• Low Startup Current Consumption. The current
consumption is reduced to a minimum (< 35 mA)
during startup, enabling fast, low loss charging of
V . The NCP1608 includes undervoltage lockout and
CC
provides sufficient V hysteresis during startup to
CC
reduce the value of the V capacitor.
CC
• Powerful Output Driver. A Source 500 mA / Sink
800 mA totem pole gate driver enables rapid turn on
and turn off times. This enables improved efficiencies
and the ability to drive higher power MOSFETs. A
combination of active and passive circuits ensures that
V
peak
Rectified DC
0
Line
Sag
the driver output voltage does not float high if V
CC
AC Line Voltage
does not exceed V
.
CC(on)
• Accurate Fixed Overvoltage Protection (OVP). The
OVP feature protects the PFC stage against excessive
output overshoots that may damage the system.
Overshoots typically occur during startup or transient
loads.
0
AC Line Current
Figure 25. Typical Line Waveforms without PFC
• Undervoltage Protection (UVP). The UVP feature
protects the system if there is a disconnection in the
Government regulations and utilities require reduced
line current harmonic content. Power factor correction is
implemented with either a passive or an active circuit to
comply with regulations. Passive circuits contain a
combination of large capacitors, inductors, and rectifiers
that operate at the ac line frequency. Active circuits use a
power path to C
(i.e. C
is unable to charge).
bulk
bulk
• Protection Against Open Feedback Loop. The OVP
and UVP features protect against the disconnection of
the output divider network to the FB pin. An internal
resistor (R ) protects the system when the FB pin is
FB
floating (Floating Pin Protection, FPP).
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NCP1608
high frequency switching converter to regulate the input
significantly reduces the harmonic current content. Active
PFC circuits are the most popular way to meet harmonic
content requirements because of the aforementioned
benefits. Generally, active PFC circuits consist of inserting
a PFC pre−converter between the rectifier bridge and the
bulk capacitor (Figure 26).
current harmonics. Active circuits operate at a higher
frequency, which enables them to be physically smaller,
weigh less, and operate more efficiently than a passive
circuit. With proper control of an active PFC stage, almost
any complex load emulates a linear resistance, which
PFC Pre−Converter
Converter
Rectifiers
High
AC Line
Bulk
Storage
Capacitor
+
+
Frequency
Bypass
Capacitor
Load
NCP1608
Figure 26. Active PFC Pre−Converter with the NCP1608
The boost (or step up) converter is the most popular
topology for active power factor correction. With the
proper control, it produces a constant voltage while
consuming a sinusoidal current from the line. For medium
power (<350 W) applications, CrM is the preferred control
method. CrM occurs at the boundary between
discontinuous conduction mode (DCM) and continuous
conduction mode (CCM). In CrM, the driver on time begins
when the boost inductor current reaches zero. CrM
operation is an ideal choice for medium power PFC boost
stages because it combines the reduced peak currents of
CCM operation with the zero current switching of DCM
operation. The operation and waveforms in a PFC boost
converter are illustrated in Figure 27.
Diode Bridge
Diode Bridge
I
L
I
L
V
in
V
V
drain
in
+
+
L
L
+
+
+
V
out
AC Line
AC Line
V
drain
−
−
The power switch is ON
The power switch is OFF
The inductor current flows through the diode. The inductor
voltage is (V − V ) and the inductor current linearly decays
With the power switch voltage being about zero, the
input voltage is applied across the inductor. The inductor
out
in
current linearly increases with a (V /L) slope.
with a (V − V )/L slope.
in
out in
Inductor
Current
(V − V )/L
Critical Conduction Mode:
Next current cycle starts
when the core is reset.
out
in
V /L
in
I
L(peak)
V
drain
V
out
V
in
If next cycle does not start
then V rings towards V
drain
in
Figure 27. Schematic and Waveforms of an Ideal CrM Boost Converter
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11
NCP1608
V (t)
When the switch is closed, the inductor current increases
in
V
I
in(peak)
linearly to the peak value. When the switch opens, the
inductor current linearly decreases to zero. When the
inductor current decreases to zero, the drain voltage of the
I
I (t)
L
L(peak)
switch (V
) is floating and begins to decrease. If the next
drain
I (t)
in
in(peak)
switching cycle does not begin, then V
rings towards
drain
V . A derivation of equations found in AND8123 leads to
in
the result that high power factor in CrM operation is
achieved when the on time (t ) of the switch is constant
on
during an ac cycle and is calculated using Equation 1.
ON
MOSFET
2 @ Pout @ L
OFF
t
+
(eq. 1)
on
h @ Vac2
Figure 28. Inductor Waveform During CrM Operation
Where P is the output power, L is the inductor value, h
out
is the efficiency, and Vac is the rms input voltage.
A description of the switching over an ac line cycle is
illustrated in Figure 28. The on time is constant, but the off
time varies and is dependent on the instantaneous line
voltage. The constant on time causes the peak inductor
Error Amplifier Regulation
The NCP1608 regulates the boost output voltage using
an internal error amplifier (EA). The negative terminal of
the EA is pinned out to FB, the positive terminal is
connected to a 2.5 V 1.6% reference (V ), and the EA
current (I ) to scale with the ac line voltage. The
L(peak)
REF
output is pinned out to Control (Figure 29).
NCP1608 represents an ideal method to implement a
constant on time CrM control in a cost−effective and robust
solution by incorporating an accurate regulation circuit, a
low current consumption startup circuit, and advanced
protection features.
A feature of using a transconductance error amplifier is
that the FB pin voltage is only determined by the resistor
divider network connected to the output voltage, not the
operation of the amplifier. This enables the FB pin to be
used for sensing overvoltage or undervoltage conditions
independently of the error amplifier.
OVP
+
OVP Fault
POK
+
+
−
V
OVP
V
out
UVP
−
+
UVP Fault
R
R
V
out1
UVP
PWM BLOCK
EA
(Enable EA)
FB
−
+
+
gm
t
R
FB
on(MAX)
V
REF
out2
Ct
Slope +
I
charge
Control
V
Control
t
on
C
COMP
t
PWM
Ct
(offset)
V
EAH
V
Control
Figure 29. Error Amplifier and On Time Regulation Circuits
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12
NCP1608
A resistor divider (R
and R ) scales down the boost
Vout
Ibias(out)
out1
out2
(eq. 3)
Rout1
+
output voltage (V ) and is connected to the FB pin. If the
out
output voltage is less than the target output voltage, then
Where I
is the output divider network bias current.
bias(out)
V
FB
is less than V
and the EA increases the control
REF
voltage (V
). This increases the on time of the driver,
R
R
is dependent on V , R , and R .
FB
Control
out2
out2
out out1
which increases the power delivered to the output. The
increase in delivered power causes V to increase until the
target output voltage is achieved. Alternatively, if V is
greater than the target output voltage, then V
decreases to cause the on time to decrease until V
decreases to the target output voltage. This cause and effect
regulates V so that the scaled down V that is applied
to FB through R
is calculated using Equation 4:
out
R
out1 @ RFB
(eq. 4)
Rout2
+
out
Vout
Control
@ ǒ Ǔ
RFB
* 1 * Rout1
VREF
out
The PFC stage consumes a sinusoidal current from a
out
out
sinusoidal line voltage. The converter provides the load
with a power that matches the average demand only. The
output capacitor (C ) compensates for the difference
between the delivered power and the power consumed by
the load. When the power delivered to the load is less than
and R is equal to V . The
out2 REF
out1
presence of R (4.6 MW typical value) for FPP is included
in the divider network calculation.
The output voltage is set using Equation 2:
FB
bulk
the power consumed by the load, C
discharges. When
R
R
out2 ) RFB
out2 @ RFB
bulk
(eq. 2)
@ ǒ
) 1Ǔ
V
out + VREF
Rout1 @
the delivered power is greater than the power consumed by
the load, C charges to store the excess energy. The
bulk
The divider network bias current is selected to optimize
the tradeoff of noise immunity and power dissipation. R
situation is depicted in Figure 30.
out1
is calculated using the bias current and output voltage using
Equation 3:
Iac
Vac
P
in
P
out
V
out
Figure 30. Output Voltage Ripple for a Constant Output Power
Due to the charging/discharging of C , V contains
Where f
is the crossover frequency and gm is the
bulk
out
CROSS
a ripple at a frequency of either 100 Hz (for a 50 Hz line
error amplifier transconductance. The crossover frequency
frequency in Europe) or 120 Hz (for a 60 Hz line frequency
is set below 20 Hz.
in the USA). The V ripple is attenuated by the regulation
out
On Time Sequence
loop to ensure V
is constant during the ac line cycle
Control
The switching pattern consists of constant on times and
variable off times for a given rms input voltage and output
load. The NCP1608 controls the on time with the capacitor
connected to the Ct pin. A current source charges the Ct
capacitor to a voltage derived from the Control pin voltage
for the proper shaping of the line current. To ensure V
is constant during the ac line cycle, the loop bandwidth is
typically set below 20 Hz. A type 1 compensation network
Control
consists of a capacitor (C ) connected between the
COMP
Control and ground pins (see Figure 1). The capacitor value
that sets the loop bandwidth is calculated using Equation 5:
(V
). V
Ct(off)
is calculated using Equation 6:
Ct(off)
2 @ Pout @ L @ Icharge
gm
VCt(off) + VControl − Ct(offset)
+
CCOMP
+
(eq. 6)
(eq. 5)
h @ Vac2 @ Ct
2 @ p @ fCROSS
When V
is reached, the drive turns off (Figure 31).
Ct(off)
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NCP1608
MOSFET Conduction
Diode Conduction
I
L
V
Control
Control
Ct
I
L(peak)
V
DD
PWM
−
+
0 A
0 V
I
charge
+
DRV
t
on
DRV
Ct
V
(offset)
drain
V
Ct
V
out
V
− Ct
(offset)
Control
V
Ct(off)
0 V
0 V
V
ZCD(WIND)
t
on
V
ZCD(WIND),off
DRV
Figure 31. On Time Generation
V
ZCD(WIND),on
V
Control
varies with the rms input voltage and output
V
ZCD
load, which naturally satisfies Equation 1. The on time is
constant during the ac line cycle if the values of
compensation components are sufficient to filter out the
V
CL(POS)
V
ZCD(ARM)
V
out
ripple. The maximum on time of the controller occurs
V
ZCD(TRIG)
when V
is at the maximum. The Ct capacitor is sized
Control
0 V
to ensure that the required on time is reached at maximum
output power and the minimum input voltage condition.
The on time is calculated using Equation 7:
V
CL(NEG)
t
on
t
diode
t
off
Ct @ VCt(MAX)
ton
+
(eq. 7)
Icharge
T
SW
Figure 32. Ideal CrM Waveforms Using a ZCD
Winding
Combining Equation 7 with Equation 1, results in
Equation 8:
2 @ Pout @ LMAX @ Icharge
h @ VacLL 2 @ VCt(MAX)
The voltage induced on the ZCD winding during the switch
Ct w
(eq. 8)
on time (V
) is calculated using Equation 9:
ZCD(WIND),on
−Vin
NB : NZCD
To calculate the minimum Ct value:
= 4.775 V (minimum value),
VZCD(WIND),on
+
(eq. 9)
V
Ct(MAX)
I
= 297 mA (maximum value), Vac
is the
LL
charge
Where V is the instantaneous input voltage and N :N
ZCD
is the turns ratio of the boost winding to the ZCD winding.
The voltage induced on the ZCD winding during the
in
B
minimum rms input voltage, and L
inductor value.
is the maximum
MAX
switch off time (V
Equation 10:
) is calculated using
ZCD(WIND),off
Off Time Sequence
In CrM operation, the on time is constant during the ac
line cycle and the off time varies with the instantaneous
input voltage. When the inductor current reaches zero, the
V
out * Vin
VZCD(WIND),off
+
(eq. 10)
NB : NZCD
drain voltage (V
in Figure 27) resonates towards V .
is a way to determine when the inductor
drain
in
When the inductor current reaches zero, the ZCD pin
voltage (V ) follows the ZCD winding voltage
Measuring V
drain
ZCD
current reaches zero. To measure the high voltage V
drain
(V
) and begins to decrease and ring towards zero
ZCD(WIND)
directly is generally not economical or practical. Instead,
a winding is added to the boost inductor. This winding,
called the Zero Current Detection (ZCD) winding,
provides a scaled representation of the inductor voltage
that is sensed by the controller. Figure32 shows waveforms
of ideal CrM operation using a ZCD winding.
volts. The NCP1608 detects the falling edge of V
and
ZCD
turns the driver on. To ensure that a ZCD event is not
inadvertently detected, the NCP1608 logic verifies that
V
ZCD
exceeds V and then senses that V
ZCD(ARM) ZCD
decreases to less than V
(Figure 33).
ZCD(TRIG)
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14
NCP1608
N
B
V
in
N
ZCD
Demag
+
−
S
Q
Reset
Dominant
Latch
+
V
ZCD(ARM)
DRIVE
R
Q
+
−
R
sense
+
V
ZCD(TRIG)
ZCD
R
ZCD
ZCD Clamp
Figure 33. Implementation of the ZCD Block
MOSFET Conduction
Diode Conduction
This sequence achieves CrM operation. The maximum
sets the maximum turns ratio and is calculated
using Equation 11:
V
ZCD(ARM)
t
z
I
L
I
Ǹ
L(peak)
* ǒ
Ǔ
Vout
2 @ VacHL
(eq. 11)
NB : NZCD v
0 A
0 V
VZCD(ARM)
I
L(NEG)
DRV
Where Vac
is the maximum rms input voltage and
HL
V
= 1.55 V (maximum value).
ZCD(ARM)
V
drain
V
The NCP1608 prevents excessive voltages on the ZCD
pin by clamping V . When the ZCD winding is negative,
out
ZCD
the ZCD pin is internally clamped to V . Similarly,
CL(NEG)
when the ZCD winding is positive, the ZCD pin is
internally clamped to V . A resistor (R in
0 V
CL(POS)
ZCD
V
ZCD(WIND)
ZCD(WIND),off
Minimum Voltage Turn on
Figure 33) is necessary to limit the current into the ZCD
pin. The maximum ZCD pin current (I ) is limited
V
ZCD(MAX)
to less than 10 mA. R
is calculated using Equation 12:
ZCD
0 V
Ǹ
2 @ VacHL
V
ZCD(WIND),on
(eq. 12)
R
ZCD w
I
ZCD(MAX) @ (NB : NZCD)
V
ZCD
CL(POS)
V
The value of R
and the parasitic capacitance of the
ZCD
ZCD pin determine when the ZCD winding signal is
detected and the drive turn on begins. A large R value
creates a long delay before detecting the ZCD event. In this
V
ZCD(ARM)
ZCD
V
ZCD(TRIG)
0 V
V
CL(NEG)
t
diode
case, the controller operates in DCM and the power factor
t
on
is reduced. If the R
value is too small, the drive turns
ZCD
R
ZCD
Delay
t
off
on when the drain voltage is high and efficiency is reduced.
A popular strategy for selecting R is to use the R
value that achieves minimum drain voltage turn on. This
ZCD
ZCD
T
SW
value is found experimentally. Figure 34 shows the realistic
Figure 34. Realistic CrM Waveforms Using a ZCD
Winding with RZCD and the ZCD Pin Capacitance
waveforms for CrM operation due to R
capacitance.
and the ZCD pin
ZCD
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NCP1608
During the delay caused by R
and the ZCD pin capacitance, the equivalent drain capacitance (C ) discharges
EQ(drain)
ZCD
through the path shown in Figure 35.
L
V
out
I
L
D
I
in
+
+
C
in
C
bulk
C
EMI
Filter
EQ(drain)
AC Line
Figure 35. Equivalent Drain Capacitance Discharge Path
C
is the combined parasitic capacitances of the
stored in the inductor (L) to be reduced. The result is that
V does not exceed V and the drive remains off
ZCD
EQ(drain)
MOSFET, the diode, and the inductor. C is charged by the
in
ZCD(ARM)
energy discharged by C
. The charging of C
until t
expires. This sequence results in pulse skipping
EQ(drain)
in
start
reverse biases the bridge rectifier and causes the input
current (I ) to decrease to zero. The zero input current
and reduced power factor.
in
Noise Induced Voltage Spike
causes THD to increase. To reduce THD, the ratio (t / T
)
SW
z
V
Control
is minimized, where t is the period from when I = 0 A to
Z
L
when the drive turns on. The ratio (t / T ) is inversely
Ct
(offset)
z
SW
proportional to the square root of L.
Low V
V
Voltage
Control
During startup, there is no energy in the ZCD winding
and no voltage signal to activate the ZCD comparators.
This means that the drive never turns on. To enable the PFC
stage to start under these conditions, an internal watchdog
V
Ct
V
− Ct
Ct(off)
Control
(offset)
timer (t ) is integrated into the controller. This timer
start
Low V
Voltage
Ct(off)
turns the drive on if the drive has been off for more than
165 ms (typical value). This feature is deactivated during a
fault mode (OVP or UVP), and reactivated when the fault
is removed.
DRV
V
ZCD
Wide Control Range
The Ct charging threshold (V
V
ZCD(ARM)
V
ZCD(ARM)
) decreases as the
Ct(off)
is Not Exceeded
output power is decreased from the maximum output
power to the minimum output power in the application. In
V
ZCD(TRIG)
high power applications (>150 W), V
is reduced to
0 V
Control
V
CL(NEG)
a low voltage at a large output power and Ct
remains
(offset)
constant. The result is that V
voltage at a large output power. The low V
is reduced to a low
Ct(off)
DRV Remains Off
and
Control
t
on(loop)
V
Ct(off)
voltages are susceptible to noise. The large output
power combined with the low V
and V
increase
Control
Ct(off)
t
t
the probability of noise interfering with the control signals
and on time duration (Figures 36 and 37). The noise induces
voltage spikes on the Control pin and Ct pin that reduces the
drive on time from the on time determined by the feedback
on
start
Figure 36. Control Pin Noise Induced On Time
Reduction and Pulse Skipping
loop (t ). The reduced on time causes the energy
on(loop)
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NCP1608
V
Control
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
V = 265 Vac
in
Ct
(offset)
NCP1608
Low V
Voltage
Control
V
Ct
Noise Induced Voltage Spike
− Ct
V
V
Ct(off)
Control
(offset)
3 V Control
Range
Low V
Voltage
Ct(off)
0.05
0
DRV
25
75
125
175
225
275
P
, OUTPUT POWER (W)
out
V
ZCD
Figure 38. Comparison of Ct Charging Threshold
vs. Output Power
V
ZCD(ARM)
is Not Exceeded
V
ZCD(ARM)
V
ZCD(TRIG)
Startup
Generally, a resistor connected between the rectified ac
line and V charges the V capacitor to V . The low
V
0 V
CL(NEG)
CC
CC
CC(on)
startup current consumption (< 35 mA) enables minimized
DRV Remains Off
standby power dissipation and reduced startup durations.
t
on(loop)
When V exceeds V , the internal references and
CC(on)
CC
logic of the NCP1608 are enabled. The controller includes
an undervoltage lockout (UVLO) feature that ensures that
t
on
t
start
the NCP1608 is enabled until V decreases to less than
CC
Figure 37. Ct Pin Noise Induced On Time
Reduction and Pulse Skipping
V . This hysteresis ensures sufficient time for the
CC(off)
auxiliary winding to supply V (Figure 39).
CC
The wide control range of the NCP1608 increases
and V in comparison to devices with less
V
Control
Ct(off)
V
CC(on)
V
CC
control range. Figure 38 compares V
of the NCP1608
Ct(off)
to a device with a 3 V control range for an application with
the following parameters:
V
CC(off)
P
= 250 W
out
Figure 39. Typical VCC Startup Waveform
L = 200 mH
h = 92%
When the PFC pre-converter is loaded by a switch−mode
power supply (SMPS), it is generally preferable for the
SMPS controller to startup first. The SMPS then supplies
Vac = 85 Vac
LL
Vac = 265 Vac
HL
the NCP1608 V . Advanced controllers, such as the
Figure 38 shows that V
of the NCP1608 is 50%
CC
Ct(off)
NCP1230 or NCP1381, control the enabling of the PFC
stage (see Figure 40) and achieve optimal system
performance. This sequence eliminates the startup resistors
and improves the standby power dissipation of the system.
larger than the 3 V control range device. The 50% increase
enables the NCP1608 to prevent inadvertent skipping at
high input voltages and high output power.
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NCP1608
D
+
C
bulk
PFC(Vcc)
+
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
V
CC
+
+
+
+
−
NCP1230
NCP1608
Figure 40. NCP1608 Supplied by a Downstream SMPS Controller (NCP1230)
Soft Start
When V exceeds V
V
CC
, t
begins counting. When
CC
CC(on) start
V
CC(on)
t
expires, the error amplifier is enabled and begins
start
V
CC(off)
charging the compensation network. The drive is enabled
when V exceeds Ct . The charging of the
I
Control
(offset)
switch
compensation network slowly increases the drive on time
from the minimum time (t ) to the steady state on time.
PWM
This creates a natural soft start mode that reduces the stress
of the power components (Figure 41).
FB
V
REF
Output Driver
The NCP1608 includes a powerful output driver capable
of sourcing 500 mA and sinking 800 mA. This enables the
controller to drive power MOSFETs efficiently for medium
power (≤ 350 W) applications. Additionally, the driver
stage provides both passive and active pull−down circuits
(Figure 42). The pull−down circuits force the driver output
to a voltage less than the turn−on threshold voltage of a
Control
Natural Soft Start
Ct
(offset)
V
out
power MOSFET when V
is not reached.
CC(on)
t
start
Figure 41. Startup Timing Diagram Showing the
Natural Soft Start of the Control Pin
V
CC
UVLO
DRV
DRV IN
V
DD
+
−
UVLO
V
ddGD
+
V
DD REG
mV
DD
GND
Figure 42. Output Driver Stage and Pull−Down Circuits
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NCP1608
Overvoltage Protection (OVP)
The value of C
is sized to ensure that OVP is not
bulk
The low bandwidth of the feedback network causes
active PFC stages to react to changes in output load or input
voltages slowly. Consequently, there is a risk of overshoots
during startup, load steps, and line steps. For reliable
operation, it is critical that overvoltage protection (OVP)
prevents the output voltage from exceeding the ratings of
the PFC stage components. The NCP1608 detects
inadvertently triggered by the 100 Hz or 120 Hz ripple of
V
out
. The minimum value of C
is calculated using
bulk
Equation 14:
Pout
2 @ p @ Vripple(peak−peak) @ fline @ Vout
Cbulk
w
(eq. 14)
Where V
is the peak−to−peak output voltage
ripple(peak-peak)
excessive output voltages and disables the driver until V
out
ripple and f
V
is the ac line frequency.
line
ripple(peak-peak)
decreases to a safe level, which ensures that V is within
out
is calculated using Equation 15:
the PFC stage component ratings. An internal comparator
connected to the FB pin provides the OVP protection. The
OVP detection voltage is calculated using Equation 13:
ǒ
Ǔ
Vripple(peak−peak) t 2 @ Vout(OVP) * Vout
(eq. 15)
The OVP logic includes hysteresis (V ) to
OVP(HYS)
(eq. 13)
ensure that V has sufficient time to discharge before the
out
V
VREF
Rout2 ) RFB
OVP @ VREF
Rout1 @
NCP1608 attempts to restart and to ensure noise immunity.
The output voltage at which the NCP1608 attempts a restart
@ ǒ
) 1Ǔ
Vout(OVP)
+
R
out2 @ RFB
(V ) is calculated using Equation 16:
out(OVPL)
Where V
/V
is the OVP detection threshold.
OVP REF
V
VREF
Rout2 ) RFB
Rout2 @ RFB
Vout(OVPL)
+
OVP @ VREF * VOVP(HYS)
Ǔ
Rout1
@
(eq. 16)
ǒ
ǒ
Ǔ
@ ǒ
) 1Ǔ
Figure 43 depicts the operation of the OVP circuitry.
V
out
V
out(OVP)
V
out(OVPL)
DRV
OVP Fault
Figure 43. OVP Operation
Open Feedback Loop Protection
Undervoltage Protection (UVP)
When the input voltage is applied to the PFC stage, V
The NCP1608 features comprehensive protection
against open feedback loop conditions by including OVP,
UVP, and FPP. Figure 44 illustrates three conditions in
which the feedback loop is open. The corresponding
number below describes each condition shown in
Figure 44.
out
is forced to equate to the peak of the line voltage. The
NCP1608 detects an undervoltage fault if V is unusually
out
low, such that V is less than V
. During an UVP fault,
FB
UVP
the drive and error amplifier are disabled. The UVP feature
protects the system if there is a disconnection in the power
path to C
(i.e. C
is unable to charge) or if R
is
1. UVP Protection: The connection from R
to
bulk
bulk
out1
out1
disconnected.
the FB pin is open. R
pulls down the FB pin
out2
The output voltage that causes an UVP fault is calculated
using Equation 17:
to ground. The UVP comparator detects an UVP
fault and the drive and error amplifier are
disabled.
R
out2 ) RFB
2. OVP Protection: The connection from R
to
@ ǒ
) 1Ǔ
Vout(UVP) + VUVP
Rout1 @
(eq. 17)
out2
R
out2 @ RFB
the FB pin is open. R
pulls up the FB pin to
out1
V . The ESD diode clamps the FB voltage to
out
10 V and R
limits the current into the FB pin.
out1
The OVP comparator detects an OVP fault and
the drive is disabled.
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19
NCP1608
3. FPP Protection: The FB pin is floating. R
conditions. If FPP is not implemented and a manufacturing
FB
pulls down the FB voltage below V . The UVP
error causes the FB pin to float, then V is dependent on
UVP
FB
comparator detects an UVP fault and the drive
and error amplifier are disabled.
the coupling within the system and the surrounding
environment. The coupled V
may be within the
FB
UVP and OVP protect the system from low bulk voltages
and rapid operating point changes respectively, while FPP
protects the system against floating feedback pin
regulation limits (i.e. V
controller to deliver excessive power. The result is that V
increases until a component fails due to the voltage stress.
< V < V ) and cause the
UVP FB REF
out
OVP
+
+
−
V
out
V
OVP
UVP
POK
−
+
+
R
R
C
bulk
out1
V
UVP
Condition 1
Condition 2
(Enable EA)
FB
E/A
−
+
Condition 3
g
m
+
out2
R
FB
V
REF
Fault
V
Control
Control
V
EAH
Clamp
C
COMP
Figure 44. Open Feedback Loop Protection
Shutdown Mode
Overcurrent Protection (OCP)
The dedicated CS pin of the NCP1608 senses the
inductor peak current and limits the driver on time if the
The NCP1608 enables the user to set the controller in a
standby mode of operation. To shutdown the controller, the
voltage of the CS pin exceeds V . The maximum
ILIM
FB pin is forced to less than V . When using the FB pin
UVP
inductor peak current is programmed by adjusting R
The inductor peak current is calculated using Equation 18:
.
for shutdown (Figure 46), the designer must ensure that no
significant leakage current exists in the shutdown circuitry.
Any leakage current affects the output voltage regulation.
sense
VILIM
Rsense
IL(peak)
+
(eq. 18)
V
out
An internal LEB filter (Figure 45) reduces the
probability of switching noise inadvertently triggering the
overcurrent limit. This filter blanks out the CS signal for a
R
out1
NCP1608
duration of t . If additional filtering is necessary, a small
LEB
1
2
3
4
8
7
6
5
RC filter is connected between R
and the CS pin.
sense
CS
DRV
Shutdown
R
out2
OCP
+
LEB
−
+
V
ILIM
R
sense
optional
Figure 45. OCP Circuitry with Optional
External RC Filter
Figure 46. Shutting Down the PFC Stage
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20
NCP1608
Application Information
The electronic design tool allows the user to easily
determine most of the system parameters of a boost
pre−converter. The demonstration board is a boost
pre−converter that delivers 100 W at 400 V. The circuit
schematic is shown in Figure 47. The pre−converter design
is described in Application Note AND8396/D.
ON Semiconductor provides an electronic design tool, a
demonstration board, and an application note to facilitate
the design of the NCP1608 and reduce development cycle
time. All the tools can be downloaded or ordered at
www.onsemi.com.
Rstart1
Rstart2
J3
Lboost
Dboost
NTC
t°
Bridge
C3
D1
R1
L1
F1
Rctup1
Rctup2
+
8
Ro1a
Ro1b
Daux
Rzcd
CVcc
Dvcc
L2
J2
C1
C2
U1
NCP1608
Cbulk
+
J1
Cin
CVcc2
1
Ddrv
Vcc
FB
2
3
4
7
6
5
DRV
GND
ZCD
Control
Ct
CS
Q1
Rdrv
Rout2a
Rct
Rout2b
Rcomp1
Ccomp
Ccomp1
Rcs
Czcd
Rs2 Rs1
Rs3
Ct2
Ccs
Ct1
Figure 47. Application Schematic
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21
NCP1608
BOOST DESIGN EQUATIONS Components are identified in Figure 1
Input rms Current
h (the efficiency of only the PFC
stage) is generally in the range of 90
− 95%. Vac is the rms ac line input
voltage.
Pout
h @ Vac
Iac +
Inductor Peak Current
Inductor Value
The maximum inductor peak current
occurs at the minimum line input
voltage and maximum output power.
Ǹ
2 @ 2 @ Pout
h @ Vac
IL(peak)
+
f
is the minimum desired
SW(MIN)
V
out
2
switching frequency. The maximum L
is calculated at both the minimum
line input voltage and maximum line
input voltage.
Vac @ ǒ * VacǓ@ h
Ǹ
2
L v
Ǹ
2 @ Vout @ Pout @ fSW(MIN)
On Time
Off Time
The maximum on time occurs at the
minimum line input voltage and max-
imum output power.
2 @ L @ Pout
ton
+
h @ Vac2
The off time is a maximum at the
peak of the ac line voltage and ap-
proaches zero at the ac line zero
crossings. Theta (q) represents the
angle of the ac line voltage.
ton
Vout
Ǹ
toff
+
* 1
Ť
Ť
Vac@sinq@ 2
Switching Frequency
On Time Capacitor
Ǹ
Vac 2 @ h
2 @ L @ Pout
|
|
Vac @ sinq @ 2
fSW
+
@
ǒ
1 *
Ǔ
Vout
Where Vac is the minimum line in-
LL
put voltage and L
is the maxim-
and
2 @ Pout @ LMAX @ Icharge
h @ VacLL 2 @ VCt(MAX)
MAX
um inductor value. I
Ct w
charge
V
are shown in the specifica-
Ct(MAX)
tion table.
Inductor Turns to ZCD
Turns Ratio
Where Vac is the maximum line
ZCD(ARM)
the specification table.
Ǹ
HL
* ǒ
Ǔ
Vout
2 @ VacHL
input voltage. V
is shown in
NB : NZCD v
VZCD(ARM)
Resistor from ZCD
Winding to the ZCD pin
Where I is maximum rated
Ǹ
ZCD(MAX)
2 @ VacHL
current for the ZCD pin (10 mA).
R
ZCD w
I
ZCD(MAX) @ (NB : NZCD
)
Output Voltage and Output
Divider
Where V is the internal reference
REF
R
R
out2 ) RFB
out2 @ RFB
voltage and R is the pull−down
FB
@ ǒ
) 1Ǔ
V
out + VREF
Rout1 @
resistor used for FPP. V
and R
REF
FB
are shown in the specification table.
is the bias current of the out-
I
Vout
Ibias(out)
bias(out)
Rout1
Rout2
+
put voltage divider.
R
out1 @ RFB
+
V
out
@ ǒ Ǔ
RFB
* 1 * Rout1
V
REF
Output Voltage OVP
Detection and Recovery
V
/V
and V
are
OVP REF
OVP(HYS)
V
VREF
Rout2 ) RFB
OVP @ VREF
Rout1 @
shown in the specification table.
@ ǒ
Ǔ−V
) 1Ǔ
Vout(OVP)
+
R
out2 @ RFB
V
R
) R
out2
FB
OVP
ǒ
ǒ
@ǒR
Ǔ
) 1Ǔ
V
+
@ V
@
out1
REF
out(OVPL)
OVP(HYS)
V
R
@ R
out2 FB
REF
Output Voltage Ripple and
Output Capacitor Value
Where f
is the ac line frequency
line
ǒ
Ǔ
Vripple(peak−peak) t 2 @ Vout(OVP) * Vout
and V
is the peak−to−
ripple(peak−peak)
peak output voltage ripple. Use f
=
line
Pout
47 Hz for universal input worst case.
Cbulk
w
2 @ p @ Vripple(peak−peak) @ fline @ Vout
Output Capacitor rms
Current
Where I
is the rms load cur-
load(RMS)
Ǹ
2
2 @ 32 @ Pout
rent.
2
+ Ǹ
IC(RMS)
* Iload(RMS)
9 @ p @ Vac @ Vout @ h2
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22
NCP1608
BOOST DESIGN EQUATIONS Components are identified in Figure 1 (Continued)
Output Voltage UVP
V
is shown in the specification
UVP
R
out2 ) RFB
Detection
table.
@ ǒ
) 1Ǔ
Vout(UVP) + VUVP
Rout1 @
R
out2 @ RFB
Inductor rms Current
2 @ Pout
IL(RMS)
+
Ǹ
3 @ Vac @ h
Output Diode rms
Current
Ǹ
Pout
2 @ 2
4
3
@ Ǹ
ID(RMS)
+
@
p
h @ Ǹ
Vac @ Vout
MOSFET rms Current
Current Sense Resistor
Ǹ
Pout
h @ Vac
2 @ 8 @ Vac
2
3
@ ǒ Ǔ@ ǒ Ǔ
IM(RMS)
+
1 *
Ǹ
Ǹ
3 @ p @ Vout
V
is shown in the specification
VILIM
ILIM
Rsense
+
table.
IL(peak)
PR
+ IM(RMS) 2 @ Rsense
sense
Type 1 Compensation
Where f
is the crossover fre-
CROSS
gm
quency and is typically less than
20 Hz. gm is shown in the specifica-
tion table.
CCOMP
+
2 @ p @ fCROSS
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23
NCP1608
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.10 (0.004)
0.10
0.19
0.40
0
M
J
H
D
8
0
8
_
_
_
_
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
ǒinches
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
The products described herein (NCP1608), may be covered by one or more of the following U.S. patents: 6,362,067, 5,359,281, 5,073,850. There may be
other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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