NCP1589LMNTWG [ONSEMI]
同步降压控制器，低电压，带轻型负载能效和瞬变性能增强;
| 型号： | NCP1589LMNTWG |
| 厂家： | 
ONSEMI |
| 描述： | 同步降压控制器，低电压，带轻型负载能效和瞬变性能增强 控制器 开关 光电二极管 |
| 文件： | 总9页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1589L
Low Voltage Synchronous
Buck Controller with Light
Load Efficiency and
Transient Enhancement
http://onsemi.com
MARKING
The NCP1589L is a low cost PWM controller designed to operate
from a 5 V or 12 V supply. This device is capable of producing an
output voltage as low as 0.8 V and converting voltage from as low as
2.5 V. It is easy to operate and provides an optimal level of integration
to reduce size and cost of the power supply. It operates in Ramp Pulse
Modulation mode for superior load step and release response. In
addition to fast transient response, it also includes a 1.5 A gate driver
design and light load efficiency features such as adaptive non−overlap
circuitry and diode emulation. It normally operates at a range of
200−500 kHz in continuous current conduction mode, which reduces
with current at light load for further power saving. Protection features
include programmable overcurrent protection, output overvoltage and
undervoltage protection and input undervoltage lockout (UVLO).
DIAGRAM
1589L
ALYWG
G
DFN10
CASE 485C
1589L = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
(Note: Microdot may be in either location)
Features
• V Range from 4.5 V to 13.2 V
CC
• Adjustable Operating frequency
• Boost Pin Operates to 35 V
PIN CONNECTIONS
• Ramp Pulse Modulation Control
• Precision 0.8 V Internal Reference
• Adjustable Output Voltage
PGOOD
1
2
3
4
5
BOOT
LX
10
9
VORPM
FB
8
UG
• Internal 1.5 A Gate Drivers
• 80% Max Duty Cycle
LG
7
COMP/DIS
Flag
V
CC
GND
6
• Input Under Voltage Lockout
• Programmable Current Limit
• Adaptive Diode Mode Emulation in Light Load
• This is a Pb−Free Device
(Top View)
ORDERING INFORMATION
Applications
†
Device
NCP1589LMNTWG
Package
Shipping
• Graphics Cards
• Desktop Computers
• Servers / Networking
• DSP & FPGA Power Supply
• DC−DC Regulator Modules
DFN10
(Pb−Free)
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
August, 2013 − Rev. 2
NCP1589L/D
NCP1589L
V
= 4.5 V − 13.2 V
V
= 4.5 V − 15 V
V = 2.5 V − 19 V
IN
CC
BST
VCC
PGOOD
BOOT
COMP/DIS
UG
R2
C2
C1
VOUT
LX
LG
FB
FLAG
GND VORPM
C3
R3
R4
R1
R9
R10
GND
Figure 1. Typical Application Diagram
PGOOD
10
PGOOD
MONITOR
OV and UV
9
VORPM
10% of V
ref
25% of V
ref
0.8 V
(V
)
ref
POR
UVLO
VCC
6
+
VOCP
FAULT
LATCH
−
8
1
3
2
BOOT
UG
FB
−
FAULT
−
+
R
+
PWM
OUT
Q
0.8 V
(V
S
)
ref
LX
+
−
RPMSET
RAMP
COMP VPRM
2 V
+
LX
−
VCC
VORPM
LG
4
5
7
COMP/DIS
FAULT
GND
AZCD logic
LX
Figure 2. Detailed Block Diagram
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2
NCP1589L
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Description
1
BOOT
Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired
input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (C ) between this pin and
BOOT
the LX pin. Typical values for C
range from 0.1 mF to 1 mF. Ensure that C
is placed near the IC.
BOOT
BOOT
2
LX
Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top
MOSFET. Also used for low side MOSFET R current detection and diode emulation.
DS(on)
3
4
UG
LG
Top gate MOSFET driver pin. Connect this pin to the gate of the top N−channel MOSFET.
Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−channel MOSFET. Also used to
set the overcurrent limit.
5
6
GND
VCC
IC ground reference. All control circuits are referenced to this pin. Connect to FLAG.
Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor
to GND. Ensure that this decoupling capacitor is placed near the IC. Also low−side MOSFET drive voltage.
7
8
COMP/DIS
FB
Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM com-
parator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. Pull this
pin low for disable.
This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to com-
pensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly
to V
.
out
9
VORPM
PGOOD
Output voltage information for RPM threshold
10
Power Good output. Pulled Low if VFB is outside 10% of 0.8 V V .
ref
ABSOLUTE MAXIMUM RATINGS
Pin Name
Symbol
VCC
V
V
MIN
MAX
Main Supply Voltage Input
Bootstrap Supply Voltage Input
15 V
−0.3 V
BOOT
35 V wrt/GND
40 V < 100 ns
15 V wrt/LX
−0.3 V
−0.3 V
−0.3 V
Switching Node (Bootstrap Supply Return)
LX
35 V
40 V for < 100 ns
−5 V
−10 V for < 200 ns
High−Side Driver Output (Top Gate)
UG
30 V wrt/GND
15 V wrt/LX
40 V for < 100 ns
−0.3 V wrt/LX
−5 V for < 200 ns
Low−Side Driver Output (Bottom Gate)
LG
15 V
−0.3 V
−5 V for < 200 ns
Feedback, VORPM
COMP/DIS
FB, VORPM
COMP/DIS
PGOOD
6.0 V
5.5 V
7 V
−0.3 V
−0.3 V
−0.3 V
PGOOD
MAXIMUM RATINGS
Rating
Symbol
Value
165
Unit
°C/W
°C/W
°C
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
R
q
JA
R
45
q
JC
T
J
0 to 150
0 to 95
−55 to +150
1
T
A
°C
T
stg
°C
MSL
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
NCP1589L
ELECTRICAL CHARACTERISTICS (0°C < T < 95°C; 4.5 V < [BOOT−LX] < 13.2 V, 4.5 V < BOOT < 30 V, 0 V < LX < 21 V,
A
C
= C = 1.0 nF, for min/max values unless otherwise noted.)
TG
BG
Characteristic
Input Voltage Range
Conditions
Min
4.5
Typ
Max
13.2
30
Unit
V
V
CC
BOOT Voltage Range
dV/dt on V
13.2 V wrt LX
4.5
V
−10
10
V/ms
CC
VREF AND ERROR AMPLIFIER
Reference Voltage
Vref
0.8
2.5
V
Output Voltage Accuracy
Reference and Error Amplifier Excluding
External Resistive Divider Tolerance
−1.0
1.0
%
SUPPLY CURRENT
V
CC
Quiescent Supply Current
No Switching, V = 13.2 V
3.8
mA
CC
BOOT Quiescent Current
No Switching
0.1
100
mA
UNDERVOLTAGE LOCKOUT
V
CC
V
CC
V
CC
UVLO Threshold
UVLO Threshold
UVLO Hysteresis
V
Rising
Falling
4.4
4.0
V
V
CC
V
CC
V
CC
Rising or V Falling
400
mV
CC
SWITCHING REGULATOR
Ramp Slope
0.5
1.50
0
V/ms
V
Ramp−Amplitude Voltage
Minimum Duty Cycle
Maximum Duty Cycle
LG Minimum on Time
ERROR AMPLIFIER
Open Loop DC Gain (Note 1)
%
70
83
92
%
200
350
ns
80
120
dB
Output Source Current
Output Sink Current
V
fb
V
fb
< 0.8 V
> 0.8 V
2.0
2.0
mA
Unity Gain Bandwidth (Note 1)
Disable Threshold
15
MHz
V
0.7
0.8
10
0.9
40
Output Source Current During Disable
GATE DRIVERS
mA
Upper Gate Source
BOOT − LX = 5 V
BOOT − LX = 5 V
1.5
1.5
A
W
A
Upper Gate Sink
1.8
Lower Gate Source
V
CC
V
CC
= 5 V
= 5 V
Lower Gate Sink
1.2
20
W
ns
UG Falling to LG Rising Delay Tdead1
(Note 1)
V
= 12 V, UG−LX < 1.0 V, LG > 1.0 V
Only Valid for CCM Operating Mode
30
30
CC
LG Falling to UG Rising Delay Tdead2
(Note 1)
V
CC
= 12 V, LG < 1.0 V, UG > 1.0 V
Only Valid for CCM Operating Mode
20
ns
UG Internal Resistor to LX
LX Internal Resistor to GND
SOFT−START
Unbiased, BOOT − LX = 0
45
45
kW
kW
Soft−Start Time
V
CC
> 4.5 V, COMP w Disable Threshold
2.0
2.6
ms
Enable to Soft−Start Delay (Note 1)
V
CC
> 4.5 V, COMP Rises and Crosses
Disable Threshold
500
ms
1. Guaranteed by design but not tested in production.
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4
NCP1589L
ELECTRICAL CHARACTERISTICS (0°C < T < 95°C; 4.5 V < [BOOT−LX] < 13.2 V, 4.5 V < BOOT < 30 V, 0 V < LX < 21 V,
A
C
= C = 1.0 nF, for min/max values unless otherwise noted.)
TG
BG
Characteristic
POWER GOOD INCLUDING OVP AND UVP THRESHOLD
Conditions
Min
Typ
Max
Unit
Output Voltage
Logic Low, Sinking 4 mA
0.4
V
Overvoltage until PGOOD goes low
Undervoltage until PGOOD goes low
PGOOD High Upper Limit Hysteresis
PGOOD High Lower Limit Hysteresis
OVP Threshold to Part Disable
UVP Threshold to Part Disable
Power Good Delay (Note 1)
880
720
16
902
mV
mV
mV
mV
mV
mV
ms
698
16
950
570
1000
600
1030
630
1.0
ZERO CURRENT DETECTION (LX Pin)
Zero Current Detection Blank Timer after
TG < 1.0 V
LX > 50 mV, LG on time
200
250
350
40
ns
ns
Capture Time for LX Voltage (Note 1)
Time to Capture LX Voltage Once LG is <
1.0 V
ZERO CURRENT V ADJUSTMENT DETECTION (LX Pin)
th
Negative LX Detection Voltage
Positive LX Detection Voltage
Vbdls
Vbdhs
200
0.2
3.0
300
0.5
400
1.0
3.7
40
mV
V
Time for V Adjustment and Settling Time
300 kHz
ms
ns
th
Zero Current Detection Blank Timer after
LG < 1.0 V (Note 1)
Blanking Time After LG is < 1.0 V
Initial Negative Current Detection
Threshold Voltage Setpoint (Note 1)
LX−GND, Includes $2 mV Offset Range
−5.0
−16
−3.0
−1.0
mV
mV
V
th
Adjustable Range (Note 1)
0
15
OVERCURRENT PROTECTION
OC Current Source
Sourced from LG pin, before SS
9.5
1.0
10
10.5
5.0
mA
OCP Programming Time
V
CC
> 4.5 V, R
= 60 kW
ms
oscset
1. Guaranteed by design but not tested in production.
Phase
Ugate to Phase
1 V
Lgate
Tdead1
Tdead2
Figure 3. Dead Time Definition
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5
NCP1589L
APPLICATIONS INFORMATION
Overcurrent Protection (OCP)
from 0 to 2.5 V in 4.2 ms; however if the output capacitors
already has 1.2 V voltage, the NCP1589L will not discharge
the capacitors, instead the soft−start sequence will begin at
1.2 V and then ramp the output up to 2.5 V.
The NCP1589L monitors the voltage across the low side
MOSFET and used this information to determine if there is
excessive output current. The voltage across the low side
MOSFET is measured from the LX pin when it is conducted,
and is referenced to ground. The overcurrent measurement
is timed to occur at the end of the low side MOSFET
conduction period.
If the voltage drop across the bottom MOSFET exceeds
the overcurrent protection threshold, then an internal
counter is triggered and incremented. If the voltage drop
does not exceed the threshold for the next cycle, the internal
counter will be reset. The NCP1589L will latch the over
current protection fault condition after 4 consecutive cycles
of overcurrent events.
Power Good
The PGOOD pin is an open drain connection, with an
active high output to signal the condition of the converter.
PGOOD is pulled low during soft−start cycle, and if there is
overvoltage or undervoltage fault. If the voltage on the FB
pin is within 10% of V (800 mV) then the PGOOD pin
ref
will not be pulled low. The PGOOD pin does not have an
internal pull-up resistor.
Overvoltage Protection (OVP)
If the voltage on the FB pin exceeds the overvoltage
When the NCP1589L latches an overcurrent protection
fault, both the high side and low side MOSFETs are turned
off. To reset the overcurrent protection fault, the power to the
threshold (1000 mV, 125% of V ), the NCP1589L will
ref
latch an overvoltage fault. During an overvoltage fault event
the UG pin will be pulled low, and the LG pin will stay high
V
CC
pin must be cycled.
until the voltage on the FB pin goes below V /2 (400 mV).
ref
The overcurrent threshold can be set externally, by
varying the R resistor shunted from low side gate pin
If the overvoltage fault condition stays, the NCP1589L will
continue drive the LG pin, LG will go high if FB exceeds
1000 mV, then go low when FB is below 400 mV. The power
of the NCP1589L needs to be cycled up to clear the
overvoltage fault.
OCSET
to ground. During power on reset, after the V and BOOT
pins both pass the undervoltage lockout threshold, the
NCP1589L will source a 10 mA current from LG pin through
CC
the R
resistor and produce a voltage. This voltage will
OCSET
be sampled and locked by the device as the overcurrent
protection threshold. For example, if R is set to 10 kW,
Undervoltage Protection (UVP)
If the voltage on the FB pin falls below the undervoltage
threshold after the soft−start cycle completes, then the
NCP1589L will latch an undervoltage fault. During an
undervoltage fault, both the UG and LG pins will be pulled
low. Toggling power or COMP pin will reset the
undervoltage protection unit.
OCSET
the 10 mA of current will yield a 100 mV threshold, and if
the voltage across the low side MOSFET exceeds 100 mV
at the end of the its conduction period, an overcurrent event
will be detected. The OCP threshold is only associated with
power on reset, and won’t be wiped out by pulling COMP
pin down (disabling the part).
VORPM (RPM threshold)
If the R
resistor is not present, the overcurrent
OCSET
The NCP1589L runs in RPM mode, its switching
frequency is controlled by COMP ripple voltage and RPM
threshold. The VORPM pin is connected to the output
voltage through an external divider. This voltage value is
proportional to the output voltage and sets the RPM
threshold voltage internally with input voltage information
obtained through the switch node. The internal RPM
protection threshold will max out at 640 mV. The
recommended range for R is 5 kW to 60 kW which
yields a threshold voltage range of 50 mV to 600 mV.
OCSET
Internal Soft−Start
To prevent excess inrush current during startup, the
NCP1589L uses a calibrated current source with an internal
soft−start capacitor to ramp the reference voltage from 0 V
to 800 mV over a period of around 4 ms. The soft−start ramp
generator will reset if the input power supply voltages reach
the undervoltage lockout threshold, or if the NCP1589L is
disabled by having the COMP pin pulled low.
threshold voltage (DTH) is a function of both V and V .
out
in
R9
Vout
R10)R9
(eq. 1)
DTH +
Vramp ) Voffset
Vin
Where R9/R10 (Figure 1) is the input voltage divider of
VORPM pin V is the internal ramp amplitude, V is
ramp
offset
Startup into a Precharged Load
the offset voltage of the threshold.
During a startup, the NCP1589L will detect the residual
charge on the output capacitors. Instead of fully discharging
the capacitors, the soft−start will begin from the precharged
output voltage level. For example, if the NCP1589L is
configured to provide a regulated output voltage of 2.5 V, the
normal soft−start sequence will ramp the output voltage
Each time when COMP voltage exceeds RPM threshold
voltage, an internal ramp signal is started and UG is driven
high. When the internal ramp intercepts with COMP
voltage, the UG pin is reset low. The NCP1589L system
operates at pseudo-fixed frequency in continuous current
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6
NCP1589L
conduction mode. The output frequency can be determined
by the following equation:
the minimum amount of diode conduction period to further
reduce the converter power consumption in the light load
condition.
Vout
Vin
k1 Ramp_slope
1
FSW
+
1 ) k2
R9
Feedback Voltage
V
out
R10)R9
ǒ
Vramp ) Voffset
Ǔ
V
The NCP1589L allows the output voltage to be adjusted
from 0.8 V to 5 V via an external resistor divider network
(R1, R4 in Figure 1). The controller will try to maintain
0.8 V at the FB pin. Thus, if a resistor divider circuit was
in
(eq. 2)
Where k1, k2 is an internal trimmed value; by default,
k1 = 1, k2 = 0, Ramp_slope = 0.5 V/ms, V = 1.5 V,
ramp
V
offset
= 20 mV.
placed across the feedback pin to V , the controller will
out
regulate the output voltage in proportion to the resistor
divider ratio in order to maintain 0.8 V at the FB pin. The
relation between the resistor divider network and the output
voltage is show in the following equation:
Light Load Operation
In continuous current conduction mode, the operating
frequency of the NCP1589L is almost constant. In light load,
it runs in a discontinuous current mode with a scaled-down
frequency as a function of the load current. Internal zero
current detection threshold will change adaptively to ensure
Vref
0.8 V
(eq. 3)
ǒ Ǔ+ R1 ǒ Ǔ
R4 + R1
V
out * Vref
V
out * 0.8 V
4.4 V
4.0 V
VCC
Internal
UVLO
Fault
1.3 V
COMP
LG
UG
V
OUT
0.8 V
FB
PGOOD
POR
NORMAL
OCP
Programming Time
Soft−Start Time
Figure 4. Typical Startup Sequence
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE F
SCALE 2:1
DATE 16 DEC 2021
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
(Note: Microdot may be in either location) not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03161D
DFN10, 3X3 MM, 0.5 MM PITCH
PAGE 1 OF 1
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相关型号：
NCP1589MNTZG
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