NCP13994AADR2G [ONSEMI]
Current Mode Resonant Controller with Integrated High Voltage Drivers, High Performance, Active X2;型号: | NCP13994AADR2G |
厂家: | ONSEMI |
描述: | Current Mode Resonant Controller with Integrated High Voltage Drivers, High Performance, Active X2 |
文件: | 总45页 (文件大小:860K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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High Performance Current
Mode Resonant Controller
with Integrated High-Voltage
Drivers
16
1
SOIC−16 NB MISSING PINS 2 AND 13
CASE 751DU
NCP13994
MARKING DIAGRAM
16
The NCP13994 is a high performance current mode controller for
half bridge resonant converters. This controller implements
700 V gate drivers, simplifying layout and reducing external
component count. The built−in Brown−Out input function eases
implementation of the controller in all applications. In applications
where a PFC front stage is needed, the NCP13994 features a dedicated
output to drive the PFC controller. This feature together with quiet
skip mode technique further improves light load efficiency of the
whole application. The NCP13994 provides a suite of protection
features allowing safe operation in any application. This includes:
overload protection, over−current protection to prevent hard switching
cycles, brown−out detection, line brown−out, line OVP, X2 cap
discharge, open optocoupler detection, automatic dead−time adjust,
over−voltage (OVP) and over−temperature (OTP) protections.
NCP13994xy
AWLYWWG
1
NCP13994 = Device Code
xy
A
WL
Y
WW
G
= Specific Device Option
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
HV
1
16 VBOOT
15 HB
Features
• Up to 700 V Operating Range for High Side Driver
• Up to 700 V Operating Range for HV Startup Current Source
• Line Brown−out and OVP Protections
• X2 Cap Discharge Function
• Clamped Output Drivers
• Up to 30 V Supply
• High−Frequency Operation from 20 kHz up to 750 kHz
• Current Mode Control Scheme
VBULK
SKIP/REM
LLC FB
3
4
5
6
7
8
14 MUPPER
12 MLOWER
11 GND
LLC CS
OVP/OTP
FB FREEZE
10 VCC
9
PFC MODE
(Top View )
• Automatic Dead−time with Maximum Dead−time Clamp
• Enhanced Startup Sequence for Fast Resonant Tank Stabilization
• Light Load Operation Mode for Improved Efficiency
ORDERING INFORMATION
See detailed ordering and shipping information on page 44 of
this data sheet.
• Quiet Skip Operation Mode for Minimize Transformer Acoustic
Noise
• Off−mode Operation for Extremely Low No−load Consumption
• Latched or Auto−recovery Overload Protection
Features (continued)
• Latched or Auto−recovery Output Short Circuit Protection with
• Pin to Adjacent Pin / Open Pin Fail Safe
• This is a Pb−Free Device
Current Reduction
• Latched Input for Severe Fault Conditions, e.g. OVP or OTP
• Out of Resonance Switching Protection
Typical Applications
• Open Feedback Loop Protection
• Adapters and Offline Battery Chargers
• Flat Panel Display Power Converters
• Computing Power Supplies
• Precise Brown−out Protection
• PFC Stage Operation Control According to Load Conditions
• Startup Current Source with Extremely Low Leakage Current
• Dynamic Self−Supply (DSS) Operation in Off−mode or Fault Modes
• Industrial and Medical Power Sources
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
July, 2022 − Rev. 0
NCP13994/D
NCP13994
D5
R9
TR1
D11
D10
Vout
RTN
D1
D2
D3
D4
L5
L6
C3
C11
Q2
Q3
D8
D7
C5
IC2 − NCP13994
C9
D6
HV input
Mupper
Vboot
R18
R5
L3
OVP/OTP
C4
HB
D12
R10
C1
D9
Q1
C14
C15
L4
Mlower
VCC
D15
PFC Mode
R19
R21
C7
C13
C10
FB FREEZE
L2
L1
C6
8
6
5
7
4
1
3
2
R6
R7
VCC
ISNS
VSNS
C2
R2
VBulk
Skip
LLC CS
R14
R15
C8
DRIVE
LED
R12
OK1
GND LLC FB
R8
R22
R20
VMIN
R13
D13
D14
4
3
1
2
R11
GND
OFFDE T
C12
R3
U1
NCP435x
R16
R4
R23
R17
Figure 1. Typical Application Example without PFC Stage
D7
L3
C3
C7
D1
D2
D3
R6
D5
D12
Q2
Q3
D10
D11
D9
IC2 − NCP13994
TR1
C13
D4
D8
HV
Mupper
Vboot
R8
R11
L4
D13
OVP/OTP
C9
IC1 − NCP16xx
C16
C8
HB
L6
Vctrl
FB
VCC
DRV
R18
R21
R19
R14
C1
CS/ZCD
GND
C6
L5
Mlower
R5
PFC Mode
FB FREEZE
VBulk
C5
VCC
L7
Q1
C10
C11
C14
R12
R13
C15
L2
C2
VDR1
C4
L1
D14
LLC CS
C12
R17
R20
Skip/REM GND LLC FB
C17
R9
OK1
R10
R15
4
3
1
2
IC1
RX2
R22
R16
R1
F1
Figure 2. Typical Application Example with PFC Stage
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2
NCP13994
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Pin Description
1
HV
High−voltage startup current
Connects to rectified AC line or to bulk capacitor to perform functions of
Start−up Current Source and Dynamic Self−Supply. Provides X2 cap
discharge and line BO/OVP functions when connected to AC line.
source input
2
3
4
NC
Not connected
Bulk voltage monitoring input
Skip threshold adjust
Increases the creepage distance.
VBULK
Receives divided bulk voltage to perform Brown−out protection.
SKIP/REM
Sets the skip in threshold via a resistor connected to ground. Controls
off−mode operation for active−on version (version dependend).
5
6
LLC FB
LLC CS
LLC feedback input
Defines operating frequency based on given load conditions. Activates
skip/LL mode operation under light load conditions. Activates off−mode
operation for active −off version.
LLC current sense input
Senses divided resonant capacitor voltage to perform on−time modula-
tion, out of resonant switching protection, over−current protection and
secondary side short circuit protection.
7
8
9
OTP / OVP
FB FREEZE
Over−temperature and
Implements over−temperature and over−voltage protection on single pin.
over−voltage protection input
Minimum internal FB level
Adjusts minimum internal FB level that can be reached during light load
operation.
PFC MODE/SKIP
PFC and external HV switch
control output
Provides supply or control voltage for PFC front stage controller. Sets
the skip out threshold.
10
11
VCC
GND
Supplies the controller
Analog ground
The controller supply pin.
Common ground connection for adjust components, sensing networks
and DRV output.
12
13
14
15
16
MLOWER
NC
Low side driver output
Not connected
Drives the lower side MOSFET
Increases the creepage distance
Drives the higher side MOSFET
Connects to the half−bridge point.
The floating supply for the upper stage.
MUPPER
HB
High side driver output
Half−bridge connection
Bootstrap pin
VBOOT
Figure 3. Internal Circuit Architecture
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3
NCP13994
MAXIMUM RATINGS
Symbol
Parameter
Value
−0.3 to 700
−0.3 to 5.5
Unit
V
V
HV Startup Current Source HV Pin Voltage (Pin 1)
VBULK Pin Voltage (Pin3)
HV
BULK/PFC FB
V
V
V
SKIP
SKIP/REM Pin Voltage (Pin 4)
−0.3 to 5.5
V
V
LLC FB Pin Voltage (Pin 5)
−0.3 to 5.5
V
FB
CS
V
LLC CS Pin Voltage (Pin 6)
−5 to 5
V
V
OVP/OTP Pin Voltage (Pin 7)
−0.3 to 5.5
V
OVP/OTP
P ON/OFF
V
FB FREEZE Pin Voltage (Pin 8)
PFC MODE Pin Output Voltage (Pin 9)
VCC Pin Voltage (Pin 10)
−0.3 to 5.5
V
V
−0.3 to VCC + 0.3
−0.3 to 30
V
PFC MODE
V
V
CC
DRV_MLOWER
V
Low Side Driver Output Voltage (Pin 12)
High Side Driver Output Voltage (Pin 14)
−0.3 to VCC + 0.3
V
V
VHB – 0.3 to
VBOOT + 0.3
V
DRV_MUPPER
V
HB
High Side Offset Voltage (Pin 15)
VBoot −30 to
VBoot +0.3
V
V
High Side Floating Supply Voltage (Pin 16)
−0.3 to 730
V
V
BOOT
V
High Side Floating Supply Voltage (Pin 15 and 16)
Allowable Output Slew Rate on HB Pin (Pin 15)
Junction Temperature
−0.3 to 30
Boot–VHB
dV/dt
100
V/ns
°C
max
T
J
−50 to 150
T
STG
Storage Temperature
−55 to 150
°C
R
Thermal Resistance Junction−to−air
130
4
°C/W
kV
q
JA
−
−
−
Human Body Model ESD Capability per JEDEC JESD22−A114F (Except Pins 14, 15, 16)
Human Body Model ESD Capability per JEDEC JESD22−A114F (Pin 14, 15, 16)
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
2
kV
1
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78
(Except Pin 5 and Pin 8, Pin 5 − 50 mA, Pin 8 − 10 mA).
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4
NCP13994
ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless
otherwise noted)
Symbol
Parameter
Pin
Min
Typ
Max
Unit
HV STARTUP CURRENT SOURCE
V
Minimum Voltage for Current Source Operation
(V = V − 0.5 V, I Drops to 95 %)
1
1
−
−
−
−
50
50
V
V
HV_MIN1
CC
CC_ON
START2
V
Minimum Voltage for Current Source Operation
(V = V − 0.5 V, I Drops to 5 mA)
HV_MIN2
CC
CC_ON
START2
I
I
Current Flowing Out of V Pin (V = 0 V)
1, 10
1, 10
1
0.2
6
0.5
9
0.8
13
25
−
mA
mA
mA
START1
CC
CC
Current Flowing Out of V Pin (V = V −0.5 V)
CC_ON
START2
CC
CC
I
Off−state Leakage Current (V = 15 V)
−
−
START_OFF
CC
T
Temperature where I
Drops to 95% of I
START2
1
−
130
°C
HV_CS_CLAMP
START2
SUPPLY SECTION
V
Turn−on Threshold Level, V Going Up
10
10
15.2
8.5
5.8
1.25
−
16
9
16.8
9.5
V
V
CC_ON
CC
V
Minimum Operating Voltage after Turn−on
CC_OFF
V
V
Level at which the Internal Logic Gets Reset
10
6.5
2.00
150
900
7.2
V
CC_RESET
CC_INHIBIT
CC
CC
V
V
Level for I
to I
Transition
10
2.75
300
1400
V
START1
START2
I
Controller Supply Current in Off−mode
Controller Supply Current in Skip−mode,
10, 11
10, 11
mA
mA
CC_OFF−MODE
I
−
CC_SKIP−MODE
V
CC
= 15 V, OVP/OTP Block De−biased During Skip Mode
I
Controller Supply Current in Latch−off Mode
Controller Supply Current in Auto−recovery Mode
Controller Supply Current in Normal Operation,
10, 11
10, 11
10, 11
−
−
−
150
135
−
300
350
6.5
mA
mA
CC_LATCH
I
CC_AUTOREC
CC_OPERATION
I
mA
f
= 100 kHz, C
= 1 nF, V = 15 V
sw
load CC
I
Controller Supply Current in Normal Operation, fsw = 100 kHz,
Cload 1 nF, VCC = 15 V
10, 11
−
−
4.5
mA
CC_LIGHTLOAD
HV SENSE
V
Line Brown−In Threshold, V Going Up
1
1
1
1
1
1
100
93
110
103
64
122
114
80
V
V
HV_UP
HV
V
Line Brown−Out Thresholds, V Going Down
HV_DOWN
HV
t
Timer Duration for Line Cycle Drop−out, (Note 2)
57
ms
V
HV
V
Line Overvoltage Threshold, V Going Up
371
15
412
20
454
25
HV_OVP
HV
V
Line Overvoltage Comparator Hysteresis, V Going Down
V
HV_OVP_HYST
HV_OVP_BLANK
HV
t
Blanking Duration for Line Overvoltage Detection, (Note 2)
227
250
317
ms
X2 DISCHARGE
I
X2 Discharge Current, V = 45 V
1
1
1
1
1
3
−
4
4
5
8
mA
V
DISCH
HV
V
Comparator Hysteresis Observed at HV Pin
HV Signal Sampling Period
HV_X2
t
−
1.0
100
30
−
ms
ms
V
SAMPLE
t
Timer Duration for No Line Detection, (Note 2)
HV Pin Voltage when X2 Discharging Process is Ended
90
20
127
40
X2_DET
V
X2_END
BOOTSTRAP SECTION
V
Startup Voltage on the Floating Section (Note 3)
Cutoff Voltage on the Floating Section
16, 15
16, 15
16, 15
16, 15
9.0
8.0
30
−
9.7
8.7
85
10.5
9.5
V
V
BOOT_ON
V
BOOT_OFF
I
I
Upper Driver Consumption, No DRV Pulses, V
= 12 V
BOOT
130
1.5
mA
mA
BOOT1
BOOT2
Upper Driver Consumption, C
= 1 nF between Pins 13 & 15
1.3
load
f
= 100 kHz, V
= 12 V, HB Connected to GND
sw
BOOT
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5
NCP13994
ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless
otherwise noted) (continued)
Symbol
Parameter
Pin
Min
Typ
Max
Unit
HB DISCHARGER
I
I
HB Sink Current Capability V = 30 V
15
15
15
15
−
1
−
−
6
6
10
9
mA
mA
V
HB_DISCHARGE1
HB_DISCHARGE2
HB
HB Sink Current Capability V = V
HB
HB_MIN
V
HB Voltage @ I
Changes from 2 to 0 mA
−
20
−
HB_MIN
HB_DISCH_CLAMP
DISCHARGE
T
Temperature where I
Drops to 95% of I
130
°C
HB_DISCHARGE1
HB_DISCHARGE1
DRIVER OUTPUTS
t
Output Voltage Rise−time @ C = 1 nF, 10 − 90% of Output Signal
12, 14
12, 14
12, 14
12, 14
14, 15
12, 11
12, 14
−
−
−
−
50
50
ns
ns
W
W
V
r
L
t
Output Voltage Fall−time @ C = 1 nF, 10 − 90% of Output Signal
f
L
R
OH
Source Resistance
Sink Resistance
−
6
32
R
−
4
11
OL
DRVH_CLAMP
V
Upper Driver Clamp Voltage, R
Lower Driver Clamp Voltage, R
= 33 kW, C
= 33 kW, C
= 220 pF
= 220 pF
12.5
12.5
−
14.5
14.5
1
17.5
17.5
−
DRV
load
V
V
DRVL_CLAMP
DRVSOURCE
DRV
load
I
Output High Short Circuit Pulsed Current
= 0 V, PW ≤ 10 ms GBD
A
V
DRV
I
Output High Short Circuit Pulsed Current
= VCC, PW ≤ 10 ms GBD
12, 14
−
−
1
−
A
DRVSINK
V
DRV
I
Leakage Current on High Voltage Pins to GND
14, 15,
16
−
15
mA
HB_CELL_LEAK
dV/dt DETECTOR
P
N
P
N
Positive Slew Rate on V
in above which is dV/dt_P Sensor
Pin above which is dV/dt_N Sensor
in above which is dV/dt_P Sensor
16
16
16
16
−
−
−
−
300
300
100
100
−
−
−
−
V/ms
V/ms
V/ms
V/ms
dV/dt_th1
dV/dt_th1
dV/dt_th2
dV/dt_th2
BOOT P
Triggered, V Rising Linearly
HB
Negative Slew Rate on V
BOOT
Triggered, V Rising Linearly
HB
Positive Slew Rate on V
BOOT P
Triggered, V Rising Linearly
HB
Negative Slew Rate on V
in above which is dV/dt_N Sensor
BOOT P
Triggered, V Rising Linearly
HB
OVP/OTP
V
OVP Threshold Voltage (V
OTP Threshold Voltage (V
Going Up)
7
7
7
7
7
7
7
7
2.35
0.76
0.72
0.45
8.20
−
2.50
0.80
0.8
2.65
0.84
0.88
0.55
9.80
−
V
V
OVP
OVP/OTP
V
Going Down)
OTP
OTP_HIGH
OVP/OTP
V
OTP Threshold Voltage (OTP Going Up − Hysteretic Mode)
OTP Threshold Voltage (OTP Going Down − Hysteretic Mode)
OTP Resistance Threshold (Resistance is Going Down)
V
V
0.5
V
OTP_LOW
R
R
R
8.95
9
kW
kW
kW
mA
OTP
OTP
OTP
OTP
OTP Resistance Threshold (Resistance is Going Down), T = 80°C
j
OTP Resistance Threshold (Resistance is Going Down), T = 110°C
−
9.05
90
−
j
I
OTP/OVP Pin Source Current for External NTC – During Normal
Operation
81
99
I
OTP/OVP Pin Source Current for External NTC – During Startup
Internal Filter for OVP Comparator, (Note 2)
7
7
7
7
7
7
162
35
180
39
198
48
mA
ms
ms
ms
V
OTP_BOOST
t
OVP_FILTER
t
Internal Filter for OTP Comparator, (Note 2)
320
3.6
1.1
2.0
350
4
435
5
OTP_FILTER
t
Blanking Time for OTP Input During Startup, (Note 2)
BLANK_OTP
V
OVP/OTP Pin Clamping Voltage @ I
= 0 mA
= 1 mA
1.2
2.4
1.3
2.8
CLAMP_OVP/OTP_1
CLAMP_ OVP/OTP_2
OVP/OTP
OVP/OTP
V
OVP/OTP Pin Clamping Voltage @ I
V
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NCP13994
ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless
otherwise noted) (continued)
Symbol
Parameter
Pin
Min
Typ
Max
Unit
START−UP SEQUENCE
t
Initial Mlower DRV On−time Duration, (Note 2)
Initial Mupper DRV On−time Duration, (Note 2)
On−time Period Increment During Soft−start, (Note 2)
Internal FB Ramp Increment During Soft Start
12
2.30
0.71
18
2.56
0.79
20
2.820
0.87
22
ms
ms
ns
−
1st_MLOWER_TON
t
14
1st_MUPPER_TON
t
12, 14
12, 14
12, 14
12, 14
14
TON_SS_INC
N
K
−
7
−
FB_SS_INC
FB_SS_INC
WATCHDOG
Soft−Start Increment Division Ratio, (Note 2)
−
1
−
−
t
Time Duration to Restart IC if Start−up Phase is not Finished
First Mupper On−time Increment after Watchdog Elapses
0.46
−
0.51
0.125
0.56
−
ms
−
K
1st_MUPPER_INC
FEEDBACK SECTION
R
Internal Pull−up Resistor on FB Pin
5
5
5
5
5
15
15
18
18
25
25
kW
kW
−
FB
FB_SKIP
R
Internal Pull−up Resistor on FB Pin at Skip Off−time
K
FB
V
FB
V
FB
to Internal Current Set Point Division Ratio
0.96
2.2
1.00
2.5
2.3
1.04
2.6
Internal Voltage Reference on the FB Pin
V
V
Internal Clamp on FB Input of On−time Comparator Referred to
External FB Pin Voltage
2.15
2.45
V
FB_CLAMP
V
Internal FB Offset Voltage to Compensate Opto−coupler Saturation
Level
5, 6
190
216
242
mV
FB_OFFSET
V
V
V
Compensation During Soft Start
5, 6
5, 6
3, 6
−
115
−
0
−
185
−
mV
mV
V/V
FB_OFFSET_COMP_SS
FB_OFFSET
FB_OFFSET
V
Compensation During Normal Operation
152
0.25
FB_OFFSET_COMP
LFF
Line Feed Forward Gain Applied on Internal FB
(V > V
_GAIN
)
BO
VBULK
CURRENT SENSE INPUT SECTION
On−time Comparator Delay to Mupper Driver Turn Off
t
5, 6
6
−
−
110
ns
CS_DELAY
V
= 2.5 V, V Goes Up from –2.5 V to 2.5 V with Rising Edge of
FB
100 ns
CS
I
Current Sense Input Leakage Current for V
=
CS
3 V
−
−
130
440
mA
CS_LEAKAGE
t
Leading Edge Blanking Time of the On−time Comparator Output,
(Note 2)
5, 6,
14
360
400
ns
LEB
SKIP
st
t
On−time Duration of 1 Mlower Pulse when FB Cross
FB_SKIP_IN
5, 12
0.57
0.64
63
0.71
ms
1st_MLOWER_SKIP
V
+ V
Threshold, (Note 2)
FB_SKIP_HYST
st
V
Internal FB Level Reduction During 1 Mupper Pulse when FB Cross
5, 6,
14
−
−
−
1st_MUPPER_SKIP
V
+ V
Threshold (Note 2)
FB_SKIP_IN
FB_SKIP_HYST
SKIP INPUT
I
Internal Skip Pin Current Source
4
9
18
18
−
20
20
−
22
22
10
mA
mA
nF
SKIP_IN
I
Internal Skip Out Pin Current Source
SKIP_OUT
SKIP_LOAD_MAX
C
Maximum Loading Capacitance for Skip Pin Voltage Filtering (Note 2)
4, 9
QUIET−SKIP
V
Feedback Voltage Thresholds to Enter Light Load Mode
Feedback Voltage Thresholds to Exit Light Load Mode
5
5
0.97
1.02
−
1.08
1.14
25
1.19
1.25
−
V
V
FB_LL_IN
V
FB_LL_OUT
LAST_ML_PATTERN
t
The Portion of Previous MU On−time that is Place for Last ML Pulse
in Pattern
12
%
t
The Portion of Previous MU On−time that is Place for Last ML Pulse
before the LL or Skip Mode is Activated
12
−
150
−
%
LAST_ML_SKIP
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NCP13994
ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless
otherwise noted) (continued)
Symbol
Parameter
Pin
Min
Typ
Max
Unit
QUIET−SKIP
t
Skip Burst Off−time Duration that is Needed to Increase Number of
12, 14
12, 14
12, 14
−
−
5
−
−
ms
ms
ms
GEAR_UP
Skipped Valleys/Peaks between Following Patterns
t
Skip Burst On−time Duration that is Needed to Decrease Number of
Skipped Valleys/Peaks between Following Patterns
30
GEAR_DOWN
t
Time Duration to Force Valley/Peak Count Logic if Valley or Peak is
not Detected, (Note 2)
9.1
10.2
11.3
VALPK_WD
t
Quiet Timer Duration
12, 14
12, 14
−
−
30
2
−
−
ms
QS_timer
N
N
N
N
Number of Patterns Adjustment when Bust Period is Shorter than 1/4
of QS_timer Duration
−
QS_1Q4
QS_2Q4
QS_3Q4
QS_4Q4
Number of Patterns Adjustment when Bust Period is Longer than 1/4
and Shorter than 2/4 of QS_timer Duration
12, 14
12, 14
12, 14
12, 14
−
−
−
−
1
0
−
−
−
−
−
−
−
−
Number of Patterns Adjustment when Bust Period is Longer than 2/4
and Shorter than 3/4 of QS_timer Duration
Number of Patterns Adjustment when Bust Period is Longer than 3/4
and Shorter than 4/4 of QS_timer Duration
−2
−4
N
Number of Patterns Adjustment when Bust Period is Longer than
QS_timer Duration
QS_INF
N
Initial Number of Patterns Placed when LL or Skip Mode is Activated
Number of MU Pulses During which FB_LL_IN cmp is Blanked Once
12, 14
14
−
−
1
−
−
−
−
PATTERN_INIT
N
50
LL_BLANK
VFB > V
FB_LL_OUT
V
Voltage on CS in when Last ML is Terminated Earlier than
Preselected Portion
6, 12
−0.21 −0.13 −0.05
V
CS_ZCD
FB FREEZE INPUT
I
FB Freeze Pin Current Source
4
4
18
20
22
10
mA
FB_FREEZE
FB_FREEZE_LOAD_MAX
C
Maximum Loading Capacitance for FB Freeze Pin Voltage Filtering
(Note 2)
−
−
nF
FAULTS AND AUTO−RECOVERY TIMER
t
Maximum On−time Clamp, (Note 2)
12, 14
8.6
9.6
2
10.6
ms
−
TON_MAX
TON_MAX_COUNTER
N
Number of TON_MAX Events to Confirm Fault
FB Voltage when FB Fault is Detected
12,14
V
5
−
2.21
72
2.2
−
2.31
80
2.4
5
2.45
100
2.6
−
V
FB_FAULT
FB_FAULT_TIMER
t
FB Fault Timer Duration, (Note 2)
ms
V
V
N
CS Voltage when CS Fault is Detected (NCP13994xA)
Number of CS_fault cmp. Pulses to Confirm CS Fault
6
CS_FAULT
CS_FAULT
−
−
K
Increment of Ramp Compensation Gain when VCS_FAULT is
Reached
5, 6
−
50
−
%
RC_GAIN_INC
N
Number of Drive Pulses to Start Decrement of CS Fault Counter
5,6
−
60
−
−
CS_FAULT_DEC
t
Maximum Dead−time Value if No dV/dt Falling/Rising Edge is
Received, (Note 2)
12, 14 1350
1500
1650
ns
DT_MAX
N
Number of DT_MAX Events to Enters IC into Fault
12, 14,
16
−
−
−
−
DT_MAX
t
Auto−recovery Duration (Common Timer for All Fault Condition) ,
(Note 2)
−
0.9
1.0
1.1
s
A−REC_TIMER
BROWN−OUT PROTECTION
V
Brown−out Turn−off Threshold
3
3
3
0.96
−
1.000
0
1.04
−
V
BO
BO_DOWN
I
Brown−out Pull Down (Hysteresis) Current, (V
Brown−Out Comparator Hysteresis
< V )
BO
mA
mV
VBULK/PFC_FB
V
−
12
30
BO_HYST
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8
NCP13994
ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless
otherwise noted) (continued)
Symbol
Parameter
Pin
Min
Typ
Max
Unit
BROWN−OUT PROTECTION
I
Brown−Out Input Bias Current
3
3
3
3
3
−
−
100
628
2.2
2
nA
ms
ms
W
BO_LEAKAGE
t
BO Filter Duration, (Note 2)
BO Blank Duration, (Note 2)
451
1.8
0.7
90
500
2.0
1.1
100
BO_FILTER
t
BO_BLANK
R
BO Pin Pull Down Switch On−state Resistance, V = 1 V
BO_SW
BO_SW_ONESHOT
BO
t
BO Pin Pull Down Switch On−state Duration (when Communication
with PFC Controller Enabled)
125
ms
RAMP COMPENSATION
RC
Ramp Compensation Gain
−
−
83
118
156
mV/ms
ms
GAIN
t
Ramp Compensation Time Shift
−
0.16
−
RC_SHIFT
TEMPERATURE SHUTDOWN PROTECTION
T
Temperature Shutdown T Going Up
−
−
−
−
124
101
−
−
°C
°C
TSD_ENTER
J
T
Temperature Shutdown Hysteresis
TSD_RELEASE
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design.
3. Minimal resistance connected in series with bootstrap diode is 3.3 W.
IC OPTIONS
FB Fault at
SS
FB Fault
Peak
Cumulative
FB Fault
Cumulative
CS Fault
Option
FB Mode
FB Fault
CS Fault
CS Fault at SS
NCP13994AA
Voltage
Auto−recovery
OFF
OFF
OFF
Auto−recovery
OFF
ON
OVP/OTP
Bias at Skip
VCC_OFF
Fault
Dead Time
Control
Dead Time
Fault
Dead Time
Repeater
Option
TON_MAX
OVP
OTP
NCP13994AA Auto−recovery Auto−recovery Auto−recovery
OFF
OFF
ZVS or
DT_max
OFF
OFF
Line BO
Status
Line OVP
Status
X2 Cap.
Discharger
Latch
Release
BO Skip
Function
Dedicated
Soft_start_seq
Start−up
Watchdog
Option
BO Status
NCP13994AA
ON
ON
ON
X2 cap. disch.
ON
Switch
ON
ON with inc.
OCP_RC_INC Ramp Comp
Quiet Skip
Mode
ZCD at
Quiet Skip
OFF−mode
Status
PFCM Skip/
LL Status
at SS
Status
Option
OCP_RC_INC
Skip Mode
NCP13994AA
ON
OFF
Without r. shift Quiet Skip
Unipolar
ON
OFF
OFF
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9
NCP13994
TYPICAL CHARACTERISTICS
0,57
0,55
0,53
0,51
0,49
0,47
0,45
0,43
10,6
10,3
10
9,7
9,4
9,1
8,8
8,5
8,2
7,9
−55
−25
5
35
65
95
95
95
125
125
125
−55
−25
5
35
65
95
95
95
125
125
125
Temperature (°C)
Temperature (°C)
Figure 4. ISTART1 vs. Temperature
Figure 5. ISTART2 vs. Temperature
12,06
12,04
12,02
12,00
11,98
11,96
11,94
11,92
9,10
9,08
9,06
9,04
9,02
9,00
8,98
8,96
8,94
8,92
8,90
−55
−25
5
35
65
−55
−25
5
35
65
Temperature (°C)
Temperature (°C)
Figure 6. VCC_ON vs. Temperature
Figure 7. VCC_OFF vs. Temperature
6,55
6,54
6,53
6,52
6,51
6,50
6,49
6,48
6,47
6,46
6,45
6,7
6,6
6,5
6,4
6,3
6,2
6,1
6,0
−55
−25
5
35
65
−55
−25
5
35
65
Temperature (°C)
Temperature (°C)
Figure 8. VCC_RESET vs. Temperature
Figure 9. IHB_DISCHARGE1 vs. Temperature
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10
NCP13994
TYPICAL CHARACTERISTICS (continued)
10,50
10,30
10,10
9,90
9,70
9,50
9,30
9,10
8,90
9,40
9,20
9,00
8,80
8,60
8,40
8,20
8,00
−55
−25
5
35
65
95
125
125
125
−55
−25
5
35
65
95
125
125
125
Temperature (°C)
Temperature (°C)
Figure 10. VBOOT_ON vs. Temperature
Figure 11. VBOOT_OFF vs. Temperature
2,515
0,801
2,510
2,505
2,500
2,495
2,490
2,485
2,480
2,475
0,800
0,799
0,798
0,797
0,796
0,795
0,794
0,793
−55
−25
5
35
65
95
−55
−25
5
35
65
95
Temperature (°C)
Temperature (°C)
Figure 12. VOVP vs. Temperature
Figure 13. VOTP vs. Temperature
1,211
1,209
1,207
1,205
1,203
1,201
1,199
1,197
90,5
90,0
89,5
89,0
88,5
88,0
87,5
87,0
−55
−25
5
35
65
95
−55
−25
5
35
65
95
Temperature (°C)
Temperature (°C)
Figure 14. VCLAMP_OVP/OTP1 vs. Temperature
Figure 15. IOTP vs. Temperature
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11
NCP13994
TYPICAL CHARACTERISTICS (continued)
19,6
19,4
19,3
19,1
19,0
18,8
18,7
18,5
4,600
4,595
4,590
4,585
4,580
4,575
4,570
4,565
−55
−25
5
35
65
95
95
95
125
125
125
−55
−25
5
35
65
95
125
125
125
Temperature (°C)
Temperature (°C)
Figure 16. RFB vs. Temperature
Figure 17. VFB_CLAMP vs. Temperature
1,006
1,005
1,004
1,003
1,002
1,001
1,000
0,999
6,02
5,99
5,96
5,93
5,90
5,87
5,84
5,81
−55
−25
5
35
65
−55
−25
5
35
65
95
Temperature (°C)
Temperature (°C)
Figure 18. VBO vs. Temperature
Figure 19. IBO vs. Temperature
111,6
111,4
111,2
111,0
110,8
110,6
110,4
110,2
104,2
104,0
103,8
103,6
103,4
103,2
103,0
102,8
−55
−25
5
35
65
−55
−25
5
35
65
95
Temperature (°C)
Temperature (°C)
Figure 20. VHV_UP vs. Temperature
Figure 21. VHV_DOWN vs. Temperature
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12
NCP13994
VCC Management with High−voltage Startup Current
Source
The NCP13994 controller features a HV startup current
source that allows fast startup time and extremely low
standby power consumption. Two startup current levels
over−temperature protection to prevent IC damage for any
failure mode that may occur in the application. The HV
startup current source is primarily enabled or disabled based
on V level. The startup HV current source can be also
CC
enabled by BO_OK rising edge, auto−recovery timer end,
off−mode and TSD end event. The HV startup current
source charges the VCC capacitor before IC start−up.
(I
and I
) are provided by the system for safety in
start1
start2
case of short circuit between VCC and GND pins. In
addition, the HV startup current source features a dedicated
to line input
HV
HV sensing features (Line BO, Line OVP)
VCC_ON
signal
Temp
Regulator
S
Q
VCC_ON
VCC
from auxiliary
winding
R /Q
VCC_OFF
signal
C_VCC
R /Q
VCC_OFF
REM
TSD
S
Q
Auto−recovery timer end
R /Q
BO_OK
S
Q
VCC_RESET
signal
to PFC_MODE
regulator
VCC_RESET
GND
Figure 22. Internal Connection of the VCC Management Block
The NCP13994 controller disables the HV startup current
source once the VCC pin voltage level reaches V
Figure 56 to find an illustration of the NCP13994 VCC
management system under all operating conditions/modes.
The HV startup current source features an independent
CC_ON
threshold – refer to Figure 22. The application then starts
operation and the auxiliary winding maintains the voltage
bias for the controller during normal and skip−mode
operating modes. The IC operates in so called Dynamic Self
Supply (DSS) mode when the bias from auxiliary winding
over–temperature protection system to limit I
current
start2
when the die temperature reaches T . At this
HV_CS_CLAMP
temperature,I
will be progressively regulated to prevent
start2
the die temperature from rising above T
.
HV_CS_CLAMP
is not sufficient to keep the V voltage above V
CC
CC_OFF
Brown−out Protection − VBULK Input
threshold (i.e. V voltage is cycling between V
and
CC
CC_ON
Resonant tank of an LLC converter is always designed to
operate within a specific bulk voltage range. Operation
below minimum bulk voltage level would result in current
and temperature overstress of the converter power stage.
The NCP13994 controller features a VBULK input in order
to precisely adjust the bulk voltage turn−ON and turn−OFF
levels. This Brown−Out protection (BO) greatly simplifies
application level design.
V
thresholds with no driver pulses on the output
CC_OFF
during positive V ramp). The HV source is also operated
in DSS mode when the low voltage controller enters
off−mode or fault−mode operation. In this case the VCC pin
voltage will cycle between V
thresholds and the controller will not deliver any driver
pulse – waiting for return from the off−mode or latch mode
operation. Please refer to figures Figure 53 through
CC
and V
CC_ON
CC_OFF
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13
NCP13994
Figure 23. Internal Connection of the Brown−out Protection Block
The internal circuitry shown in Figure 23 allows
running, the I
sink is disabled. The bulk voltage
BO_DOWN
monitoring the high−voltage input rail (V ).
A
turn−off threshold (V ) is then given by BO
bulk_OFF
bulk
high−impedance resistive divider made of R
and R
comparator reference voltage directly on the resistor divider.
The advantage of this solution is that the V
upper
lower
resistors brings a portion of the V
rail to the VBULK pin.
bulk
bulk_OFF
The Current sink (I
) is active below the bulk
threshold precision is not affected by I
(hysteresis)
BO_DOWN
BO_DOWN
voltage turn−on level (V
). Therefore, the bulk
current sink tolerance.
bulk_ON
voltage turn−on level is higher than defined by the division
ratio of the resistive divider. To the contrary, when the
internal BO_OK signal is high, i.e. the application is
The V
using equations below:
and V
levels can be calculated
bulk_ON
bulk_OFF
The I
is ON:
BO_DOWN
Rlower
Rlower @ Rupper
RLowr ) Rupper
@ ǒ
Ǔ
V
BO ) VBOhyst + Vbulk_ON
@
* IBO_DOWN
(eq. 1)
Rlower ) Rupper
The I is OFF:
information. The BO comparator then authorizes or disables
the LLC stage operation based on the actual V level.
BO
Rlower
Rlower ) Rupper
bulk
VBO + Vbulk_OFF
@
The low hysteresis current of the NCP13994 brown out
protection system allows increasing the bulk voltage divider
resistance and thus reduces the application power
consumption during light load operation. On the other hand,
the high impedance divider can be noise sensitive due to
capacitive coupling to HV switching traces in the
(eq. 2)
One can extract R
equation 1 to get needed R
term from equation 2 and use it in
lower
value:
upper
V
bulk_ON@VBO
* VBO * vBOhyst
Vbulk_OFF
DRlower
+
application. This is why a filter (t
) is added after the
BO_FILTER
(eq. 3)
(eq. 4)
VBO
comparator on Vbulk pin in order to increase the system
noise immunity. Despite the internal filtering, it is also
recommended to keep a good layout for BO divider resistors
and use a small external filtering capacitor on the VBULK
pin if precise BO detection wants to be achieved.
The bulk voltage divider can be disconnected by HV
switch (controlled by signal from the PFC MODE pin)
during off−mode operation. This technique further reduces
the no−load power consumption down again since the power
losses of voltage divider are not affected by the bulk voltage
at all.
@ ǒ1 *
Ǔ
IBO_DOWN
Vbulk_OFF
V
bulk_OFF * VBO
Rupper + Rlower
@
VBO
Note that the VBULK pin is pulled down by an internal
switch when the controller is in startup phase − i.e. when the
V
V
voltage ramps up from V < V
towards the
CC
CC
CC_RESET
level on the VCC pin. This feature assures that the
CC_OFF
VBULK pin voltage will not ramp up before the IC
operation starts. The I hysteresis current sink is
activated and BO discharge switch is disabled once the V
voltage crosses V
voltage then ramps up naturally according to the BO divider
BO_DOWN
CC
The NCP13994 is able to generate Power Good (PG)
signal based on bulk capacitor voltage via BO_PG
comparator sensing VBULK pin voltage.
threshold. The VBULK pin
CC_OFF
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14
NCP13994
The VBULK pin voltage is also used by Line Feed
threshold, an auto−recovery line brown−out protection, line
overvoltage protection and X2 capacitor discharge function.
It is allowed only to work with an unfiltered, rectified ac
input to ensure the X2 capacitor discharge function, which
is described in following paragraph. The brown−out
protection thresholds are internally selectable in specific
steps, to fit most of the standard ac−dc conversion
applications.
Forward block (LFF). Please refer to ON−time modulation
and feedback loop block description for more information
about LFF function.
The processed VBULK information are blanked when
BO switch is activated or at specific events during bulk
voltage modulation.
Please refer to Figure 53 through Figure 56 for an
illustration of NCP13994 Brown−out protection system in
all operating conditions/modes.
When the input voltage is below V
for time
HV_DOWN
longer then line brown−out timer duration (t ), a
HV
brown−out condition is detected, and the controller stops
generate drives pulses. The HV current source maintains
HV Sensing of Rectified AC Voltage
The NCP13994 features on its HV pin a true ac line
monitoring circuitry. It includes a minimum start−up
V
CC
between V
and V levels until the input
CC_ON
CC_OFF
voltage is back above V
.
HV_UP
HV timer elapsed
V
HV
VHV_UP
VHV_DOWN
time
Line BO
Brown−out
detected
t HV
time
Waits next
VccON before
starting
V
CC
VCC_ON
VCC_OFF
time
time
Brown−out
condition can
reset the
DRV
Internal Latch
Figure 24. Ac Line Drop−out Timing Diagram
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15
NCP13994
When V crosses the V
threshold, the controller
immediately after the device stop. The device restart is
HV
HV_UP
starts when the V crosses the next V
event. When
allowed only when system detects positive slope of input
signal for 2 ms (two sample clocks used at X2 cap discharge
logic). The basic principle is shown at Figure 25 with block
diagram at Figure 26.
CC
CC_ON
it crosses V
, it triggers a timer of duration t , this
HV_DOWN
HV
ensures that the controller doesn’t stop in case of line cycle
drop−out. The device restart is disabled when parasitic spike
is induced at HV pin by the residual energy in the EMI filter
HV timer elapsed
V
HV
VHV_UP
VHV_DOWN
time
Spike induced by
residual energy in
EMI filter
Line BO
Brown−out
detected
t HV
time
Waits next
VccON before
starting
V
CC
VCC_ON
VCC_OFF
time
time
Brown−out
condition can
reset the
DRV
Internal Latch
Figure 25. Ac Line Drop−out Timing Diagram with the Parasitic Spike
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16
NCP13994
Figure 26. Brown−out and Line Overvoltage Detection Schematic
The same system is used for the Line OVP, except that this
time the controller must not stop instantaneously when the
input voltage goes above V , in order to be insensitive
reset and starts counting. The IC can starts after the timer
elapses and all other start conditions are fulfil. The timer is
paused and afterwards reset if new Line OVP event occur
during the timer counting process as is shown at Figure 27.
When the Line OVP fault ends (the timer elapses) and the
HV_OVP
to spikes and voltage surges shorter than t
.
OVP_BLANK
Therefore a blanking circuit is inserted after the output of the
comparator.
input voltage is below V
the controller does not
HV_DOWN
When the overvoltage event occurs, Line OVP signal is
set and controller stops generate pulses. When the
starts and waits for another Brown−in event as is shown at
Figure 28.
overvoltage event finishes the timer with duration t
is
HV
Blanked
voltage
surge
V
HV
VHV(OV)
time
HV
OVP
detected
HV
timer
timer
starts
restarts
HV timer
Restarts at
VCC_ON
t HV
time
DRV
time
Figure 27. AC Input Line Overvoltage Timing Diagram
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17
NCP13994
V
HV
VHV_OVP
VHV_UP
HV timer
starts
HV timer
restarts
time
time
Line
thv
Line BO
time
DRVs pulses
starts
DVRs
time
Figure 28. AC Input Line Overvoltage and Brown Out Common Timer Behavior Timing Diagram
X2 Cap Discharge Feature
edge is detected for 10 ms from last detected positive edge
This feature saves approximately 16 mW – 25 mW input
power depending on the EMI filter X2 capacitors volume
and it saves the external components count as well. The
discharge feature is ensured via the start−up current source
with a dedicated control circuitry for this function. The X2
only). The additional offset V can be measured as the
OS
V
HV_X2
on the HV pin. If the comparator output produces
pulses it means that the positive or negative slope of input
signal is present. If the comparator output stays at low or
high level it means that the slope of input signal is lower than
set resolution level. There is used the detection timer which
is reset by any edge of the comparator output. If no edge
comes before the timer elapses then only dc signal or signal
with the small ac ripple is present at the HV pin. This type
of the ac detector detects both positive and negative voltage
slope, which fulfils the requirements for the ac line presence
detection.
In case of the dc signal presence on the high voltage input,
the direct sample of the high voltage obtained via the high
voltage sensing structure and the delayed sample of the high
voltage are equivalent and the comparator produces the low
level signal. No edges are present at the output of the
comparator, that’s why the detection timer is not reset and dc
detect signal appears.
capacitors are being discharged by current defined as I
DISCH
when line disconnection is detected. The discharging
current is lineary decreased based on HV pin voltage when
the voltage decrease below about 40 V to allow higher value
of external series resistor. The minimum discharging current
is about 1 mA at V
.
X2_END
There is used a dedicated structure called ac line unplug
detector inside the X2 capacitor discharge control circuitry.
See the Figure 29 for the block diagram for this structure and
figures Figure 30, Figure 31, Figure 32 for the timing
diagrams. The basic idea of ac line unplug detector lies in
comparison of the direct sample of the high voltage obtained
via the high voltage sensing structure with the delayed
sample of the high voltage. The delayed signal is hold by the
sample & hold structure.
The minimum detectable slope by this ac detector is given
by the ration between the maximum hysteresis observed at
The comparator used for the comparison of these signals
is without hysteresis inside. The resolution between the
slopes of the ac signal and dc signal is defined by the
HV pin V
and the sampling time:
HV_X2,max
VHV_X2,max
sampling time t
and additional internal offset V
.
Smin +
SAMPLE
OS
(eq. 5)
tSAMPLE
These parameters ensure the noise immunity. The additional
offset is added to the image of the sampled HV signal and its
Than it can be derived the relationship between the
detectable slope, the amplitude and frequency of the
sinusoidal input voltage:
analog sum is stored in the C storage capacitor. If the
1
voltage level of the HV sensing structure output crosses this
level the comparator CMP output signal resets the detection
VHV_X2,max
Vmax
+
timer (t
) and positive slope of HV signal is detected.
(eq. 6)
X2_DET
2 @ p @ f @ tSAMPLE
The negative slope is detected by similar way (the negative
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18
NCP13994
The X2 capacitor discharge feature is active under any
controller operation mode to ensure SMPS users safety. The
discharging process continues until the HV pin voltage
The controller operation is terminated and V voltage is
CC
droping due to IC consumption during the X2 discharging
process. The device start−up is blocked by the discharge
dorops below V
level. It is important to note that it
sequence.
X2_END
is not allowed to connect HV pin to any dc voltage, e.g.
directly to bulk capacitor.
Figure 29. The Ac Line Unplug Detector Simplified Structure Used for X2 Capacitor Discharge System
VHV
HV signal with
coupled noise
VHV_X2
VHV_X2
Sampled HV + VHV_X2
offset
t SAMPLE
time
Sampling control
signal
time
Timer
Reset signal
time
t DET
Timer
Detection
timer counts
Detection
timer is reset
time
Figure 30. The Ac Line Unplug Detector Timing Diagram Detail with Noise Effects
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NCP13994
VHV
AC line
unplug
X2 capacitor
discharge
VHV_UP
VHV_DOWN
VX2_END
time
time
AC line
Starts
HV
HV
Unplug
only at
VCC(on)
timer
starts
timer
detector starts
restarts
No AC
One Shot
detection
t HV
t DET
DRV
Brown−out
X2
discharge
time
time
X2 discharge
current
VCC_ON
VCC
VCC_OFF
time
Figure 31. HV Pin Ac Input Timing Diagram with X2 Capacitor Discharge Sequence when the Application is
Unplugged under Extremely Low Line Condition
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NCP13994
X2 capacitor
discharge
V HV
AC line unplug
VHV_UP
VHV_Down
X2 capacitor
discharged
time
HV
HV
Starts
only at
VCC(on)
timer
starts
timer
AC line
restarts
Unplug
detector starts
One Shot
No AC detection
t X2_DET
time
Device is
stopped
DRV
time
time
X2 discharge
X2 discharge
current
VCC_ON
VCC
VCC_OFF
time
Figure 32. HV Pin Ac Input Timing Diagram with X2 Capacitor Discharge Sequence when the Application is
Unplugged Under High Line Condition
Over−voltage and Over−temperature Protection
depending on the IC version − and triggered the protection
threshold (V or V ).
The OVP/OTP pin is a dedicated input to allow for a
simple and cost effective implementation of two key
protection features that are needed in adapter applications:
over−voltage (OVP) and over−temperature (OTP)
protections. Both of these protections can be either latched
or auto−recovery – depending on the version of NCP13994.
The OVP/OTP pin has two voltage threshold levels of
OTP
OVP
The internal current source I
allows a simple OTP
OTP
implementation by using a single negative temperature
coefficient (NTC) thermistor. An active soft clamp
composed from V
and R
components prevents the
clamp
clamp
OVP/OTP pin voltage from reaching the V
threshold
OVP
when the pin is pulled up by the I
current. An external
OTP
detection (V
and V ) that define a no−fault window.
OTP
pull−up current, higher than the pull−down capability of the
OVP
The controller is allowed to run when OVP/OTP input
voltage is within this working window. The controller stops
the operation, after filter time delay, when the OVP/OTP
input voltage is out of the no−fault window. The controller
then either latches−off or or starts an auto−recovery timer −
internal clamp (V ), has to be applied to pull
CLAMP_OVP/OTP
the OVP/OTP pin above V
threshold to activate the OVP
OVP
protection. The t
and t
filters are
OVP_FILTER
OTP_FILTER
implemented in the system to avoid any false triggering of
the protections due to application noise and/or poor layout.
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NCP13994
Figure 33. Internal Connection of OVP/OTP Input
Off−mode Control
The OTP protection could be falsely triggered during
controller startup due to the external filtering capacitor
The NCP13994 implements an ultra−low power
consumption mode of operation called off−mode. The
application output voltage is cycled between the nominal
and lower levels that are defined by the secondary side
off−mode controller (like NCP435x secondary off−mode
controller). The output voltage is thus not regulated to
nominal level but is always kept at a high enough voltage
level to provide bias for the necessary circuits in the target
application – for example this could be the case of
microcontroller with very low consumption that handles
VCC management in a notebook or TV. The no−load input
power consumption could be significantly reduced when
using described technique. The NCP13994 implements two
different off−mode control system approaches:
charging current. Thus the t
implemented in the system to overcome such behavior. The
OTP comparator output is ignored during t
period has been
BLANK_OTP
BLANK_OTP
period. In order to speed up the charging of the external
filtering capacitor C connected to OVP/OTP pin,
OVP_OTP
the I
current has been doubled to I
. The
OTP_BOOST
OTP
maximum value of filtering capacitor is 100 nF.
The OVP/OTP ON signal is set after the following events:
• the V voltage exceeds the V threshold during
CC
CC_RESET
first start−up phase (after VCC pin voltage was below
threshold)
V
CC_RESET
• IC returns from non−switching states to switching state
(like bulk BO, line BO, line OVP and VCC_OFF
protections, auto−recovery...) except hysteretic mode of
OTP protection
• Active ON off−mode control
• Active OFF off−mode control
These two off−mode operation control techniques differ
in the way the off−mode operation is started on the primary
side controller. Both of these methods are described
separately hereinafter.
The I
current source is disabled when:
OTP
• DRVs stop switching
IC option that keeps OVP/OTP block working during skip
mode is also available. The IC consumption is increased for
this version by OVP/OTP block bias.
Active ON Off−mode Control
OTP protection can operate (based on IC version) at
hysteretic mode where DRVs are stopped when voltage on
the pin drops below low threshold and operation is restarted
once voltage on the pin increase above high threshold.
OTP condition is not process when IC restarted from
off−mode state.
The NCP13994 device family could use a SKIP/REM pin
only for off−mode operation control– i.e. the pin is internally
connected to the Active ON off−mode control block and the
skip mode threshold level is not adjustable externally. The
skip mode comparator threshold can be adjusted only
internally (by IC option) in this option. The SKIP/REM pin
when used for off−mode control allows the user to activate
the ultra−low consumption mode during which the IC
consumption is reduced to only very low HV pin leakage
The latched OVP or OTP versions of NCP13994 enters
latched protection mode when V voltage cycles between
CC
V
CC_ON
and V
thresholds and no pulses are provided
CC_OFF
by drivers. The controller VCC pin voltage has to be cycled
down below V threshold or appropriate conditions
current (I
)
and very low VCC pin
HV_OFF−MODE
CC_RESET
consumption (I ). The off−mode is activated
CC_OFF−MODE
on HV pin have to occur in order to restart operation. This
would happen when the power supply is unplugged from the
mains.
when SKIP/REM pin voltage exceeds V
threshold.
REM_OFF
Normal operating mode is resumed when SKIP/REM pin
voltage drops below V threshold – refer to
REM_ON
Figure 34 for an illustration.
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NCP13994
aux.
winding
secondary
winding
D1
to Vcc
REM
to logic and Vcc management
C_Vcc
rect.
Vout
VREM_OFF
D2
C1
VVCC_ON
Q
S
R
off−mode
Fault
VCC_RESET
detect
/Q
Vout sense
R1
SKIP/REM
Stop condition
REM OK
Sec. side
reg. & off−mode
off−mode
control
Reset
REM
TIMER
controller
R2
regulation
C2
FB OK
GND
to FB
Figure 34. SKIP/REM Input Internal Connection – Active ON Version
The off−mode operation is activated by the secondary side
off−mode controller. The auxiliary bias for primary side
off−mode control is provided by a circuit composed from
the secondary side capacitors to the nominal output voltage
level. In this case we do not use REM TIMER because it
would increase the no−load power consumption by forcing
the application to run for a longer time than necessary.
The bias on VCC pin needs to be assured when off−mode
operation takes place. The auxiliary winding is no more able
to provide any bias thus the HV startup current source is
operated in DSS mode – i.e. the VCC pin voltage is cycling
components D , C , R , R and C . The SKIP/REM pin is
2
1
1
2
2
pulled up by this auxiliary supply circuit once the REM
optocoupler (REM OK) is released. The application then
operates in off−mode until the secondary side off−mode
controller activates the REM optocoupler or until the
auxiliary bias on C is lost. Normal operation mode is then
between V
and V
thresholds. This approach
1
CC_ON
CC_OFF
recovered via power stage startup. The application is thus
switching between ON−mode and OFF−mode states when
off−mode control is implemented. The OFF mode period
last significantly longer time (tens of seconds or more)
compared to the secondary capacitor refilling period (few
tens of milliseconds) – this explains why the no−load input
power consumption can be drastically reduced. The
auxiliary off−mode supply capacitor C1 can stay charged
while the secondary bias is lost – this can happen during
overload or other fault mode conditions. A REM TIMER is
thus implemented in the system to allow fast application
restart in such cases. The controller blanks the SKIP/REM
keeps IC biasing in order to memorize the current operation
sate.
Active OFF Off−mode Control
The NCP13994 device family could use LLC FB pin
voltage information for off−mode operation detection −
refer to Figure 35. The SKIP/REM pin is internally
connected to the skip mode block in this case and serves as
a V
threshold voltage adjust pin. The secondary
FB_SKIP_IN
off−mode controller reuses the LLC stage regulation
optocoupler in order to reduce total system cost. The
off−mode operation is initiated once the LLC FB pin is
pulled down below V
threshold followed by the
FB_REM_OFF
input information for t
time during controller
REM_TIMER
VCC pin voltage drop below V
threshold. The
CC_OFF
restart so that the secondary side bias can be restored and the
secondary off−mode controller can activate the REM
optocoupler. This REM TIMER blank sequence is activated
opto−coupler has to be active at all time the application is
held in off−mode. No biased is then provided by the
secondary off−mode controller during normal operation –
this is why this approach is called Active OFF off−mode
operation. The application no−load input power
consumption is slightly higher compared to Active ON
off−mode solution, previously described, because the
opto−coupler needs to be biased during off mode operation.
each time the VCC pin voltage reaches V
threshold –
CC_ON
except in the situation when after IC left off−mode operation
by standard way and V is restored – i.e. when the REM
CC
optocoupler is activated by the secondary off−mode
controller. The controller is active for very short time during
no−load conditions − just during the time needed to re−fill
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NCP13994
secondary
winding
rect.
Vref
Vout
off−mode
to FB block
REM
status
to logic and Vcc management
Vdd
REM_ON
REM_OFF
L @ Vcc < VCC_OFF
H @ VCC > VCC_OFF
RFB
off−mode
detect
Vout sense
FB OK
FB
VFB_REM_OFF
Sec. side
reg. & off−mode
reg.
GND
controller
C2
Figure 35. Active OFF Off−mode Internal Detection Based on the LLC FB Pin Voltage
The controller monitors the LLC FB pin voltage level and
restarts via regular startup sequence (including VCC pin
Please refer to Figure 56 for an illustration on how the
NCP13994 off−mode system works under all operating
conditions/modes.
voltage ramp−up to V
level and soft−start) once the
CC_ON
FB pin is released by the secondary off−mode controller.
The HV startup current source is working in DSS mode
during application off−mode operation – i.e. the VCC pin
PFC MODE Output
The NCP13994 has PFC MODE pin that can be used to
control aditional circuit based on actual application
operating state – please refer to Figure 36. The PFC MODE
output pin can be used for two main purposes:
voltage is cycling between V
and V
CC_ON
CC_OFF
thresholds. This approach keeps IC biased so that the actual
operation sate is memorized. The LLC FB pin pull−up
resistor is disconnected and off−mode pull up current source
st
1 to control the PFC front stage controller operation
nd
I
is activated when off−mode operation is
FB_REM_BIAS
2
to control PG optocoupler based on bulk capacitor
activated in order to reduce IC power consumption and also
needed current for opto−coupler driving from secondary
side.
voltage
VCC
from auxiliary
winding
C_VCC
ISKIP_OUT control
Off−mode
PFC_MODE
Fault condition
Stop condition
Main logic
PFC_controller
BO_PG
Skip/LL_MODE
Figure 36. Internal Connection of the PFC MODE Block
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NCP13994
There are three possible states of the PFC MODE output
that can be placed by the controller based on the application
operating conditions:
voltage levels is to fully bias PFC controller during
normal operation and keep limited bias (just below
PFC controller VCC_off level) to keep PFC
controller internal blocks biased with reduced
consumption of PFC controller.
c. The PFC MODE can be also at High Z state during
skip or light load mode to keep remaining charge of
PFC controller VCC capacitor. The combination of
High Z state with pull−down switch can be used to
control Power Good (PG) opto−coupler.
a. The PFC MODE output pin is pulled−down by an
internal MOSFET switch before controller startup.
This technique ensures minimum VCC pin current
consumption in order to ramp V voltage in a short
CC
time from the HV startup current source. This
approach speeds up the startup and restart time of an
SMPS. The PFC MODE output pin is also
pulled−down in off−mode, protection mode and at
stop conditions (except BO event via VBULK pin)
during which the HV startup current source is
operated in DSS mode. Application power
consumption is reduced in above cases. The
pull−down switch can be activate also in skip or light
load mode (depends on IC version)
The pin n.9 can be used for skip_out threshold level
definition when PFC_MODE functions are not required or
during application debugging.
Please refer to Figure 53 through Figure 56 for an
illustration of NCP13994 PFC operation control.
ON−time Modulation and Feedback Loop Block
The NCP13994 on−time modulation uses current mode
control scheme that ensures best transient response
performance and provides inherent cycle−by−cycle
over−current protection feature in the same time. The
current mode control principle used in this device can be
seen in Figure 37.
b. Second possible state of PFC MODE output is
regulated voltage. The two regulated levels V
REG1
and V
are available. Regulation level V
is
REG2
REG1
present on the output during normal operation and IC
can switch to V during skip or light−load
REG2
modes. The purpose of switching between two
Figure 37. Internal Connection of the NCP13994 Current Mode Control Scheme
The basic principle of current mode control scheme
ON−time comparator output is blanked by the leading edge
blanking (t ) after the Mupper switch is turned−on. The
ON−time comparator LEB period helps to avoid false
triggering of the on−time modulation due to noise generated
by the HB pin voltage transition.
The voltage signal for current sense input is prepared
externally via natural primary current integration by the
resonant tank capacitor Cs. The resonant capacitor voltage
is divided down by capacitive divider (Ccs1, Ccs2, Rcs1,
Rcs2) before it is provided to the CS input. The capacitive
implementation lies in the use of an ON−time comparator
that defines upper switch on−time by comparing voltage
ramp, derived from the current sense input voltage, to the
divided or not divided feedback pin voltage. The upper
switch on−time is then re−used for low side switch
conduction period. The switching frequency is thus defined
by the actual primary current and output load conditions.
Digital processing with 10 ns minimum on−time resolution
is implemented to ensure high noise immunity. The
LEB
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NCP13994
divider division ratio, which is fully externally adjustable,
and startup. The FB pin signal passes through the FB
processing block before it is brought to the ON−time
comparator input. The FB processing block scales the FB
defines the maximum primary current level that is reached
in case of maximum feedback voltage – i.e. the capacitive
divider division ration defines the maximum output power
of the converter for given bulk voltage. The CS pin is a
bipolar input where an input voltage swing is restricted to
5 V. The CS pin signal is also used for secondary side short
circuit detection – please refer to chapter dedicated to short
circuit protection.
signal down by a K ratio in order to limit the CS input
FB
dynamic voltage range and apply ramp compensation signal
(to ensure stability of the current mode control scheme), FB
freeze or LFF. The processed internal FB signal could be
overridden by a Soft−start generator output voltage during
device starts−up.
A fixed voltage offset is internally process to the FB pin
signal in order to assure enough voltage margin for operation
the feedback opto−coupler − the FB opto−coupler saturation
voltage is ~0.15 V (depending on type). However, the CS
pin useful signal for frequency modulation swings from 0 V,
so current mode regulation would not work under light load
conditions if no offset would be added.
The second input signal for the on−time comparator is
derived from the FB pin voltage. This internal FB pin signal
is also used for the following purposes: skip mode operation
detection, Light−load mode detection, off−mode detection
and overload / open FB pin fault detection. The detailed
description of these functions can be found in each dedicated
chapters. The internal pull−up resistor assures that the FB
pin voltage increases when the opto−coupler LED becomes
less biased – i.e. when output load is increased. The higher
FB pin voltage implies a higher reference level for on−time
comparator i.e. longer Mupper switch on−time and thus also
higher output power. The FB pin features a precise voltage
clamp which limits the internal FB signal during overload
The actual operating frequency of the converter is defined
based on the CS pin and FB pin input signals. The maximum
output power of the converter, under given input voltage, is
limited by maximum internal FB voltage clamp that is
reached when opto−coupler provides no current. The
maximum output power limit is bulk voltage dependent due
to changing ratio between magnetizing and load primary
current components. Line Feed Forward (LFF) system is
implemented in the controller to compensate for maximum
output power clamp variation. The LFF signal that is apply
to internal FB voltage is VBULK pin voltage proportional.
The different input voltage sensed by VBULK pin creates
change on internal FB signal. The Mupper switch on−time
is thus changed to represent similar FB pin voltage at
constant load across different input voltage. The LFF signal
is provided only when BO pin voltage exceeds BO_OK
threshold voltage.
Please refer to Figure 38 and below description for better
understanding principle of the NCP13994 frequency
modulation system.
Figure 38. NCP13994 On−time Modulation Principle
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NCP13994
The Mupper switch is activated by the controller after
switching cycles. Thus a special logic has been implemented
in NCP13994 in order to repeat the last valid on−time until
the current mode operation recovers – i.e. until the CS pin
signal balance is restored by the system.
dead−time (DT) period elapses in point A. The frequency
processing block increments the ON−time counter with 10
ns resolution until the internal CS signal crosses the internal
FB set point for the ON−time comparator in point B. A DT
period is then introduced by the controller to avoid any
shoot−through current through the power stage switches.
The DT period ends in point C and the controller activates
the Mlower switch. The ON−time processing block
decrements the ON_time counter down until it reaches zero.
The Mlower switch is then turned−OFF at point D and the
DT period is started. This approach results in perfect duty
cycle symmetry for Mlower and Mupper switches. The
Mupper switch on−time naturally increases and the
operating frequency drops when the FB pin voltage is
increased, i.e. when higher current is delivered by the
converter output – sequence E.
Overload and Open FB Protections
The overload protection and open FB pin detection are
implemented via FB pin voltage monitoring in this
controller. The FB fault comparator is triggered once the FB
pin voltage reaches the V
level. The fault timer is
FB_FAULT
then enabled – refer to Figure 39. The time period to the FB
fault event confirmation is defined by the preselected
t
parameter. The fault timer is reset once
FB_FAULT_TIMER
the FB fault condition diminishes or timer counts down
when cumulative option is selected. The speed of timer
counting when timer counts up and down can be different.
A digital noise filter has been added after the FB fault
comparator to overcome false triggering of the FB fault
timer due to possible noise on the FB input.
The resonant capacitor voltage and thus also CS pin
voltage can be out of balance in some cases – this is the case
during transition from full load to no−load operation when
skip mode is not used or adjusted correctly. The current
mode operation is not possible in such case because the
ON−time comparator output stays active for several
When FB pin voltage reaches V
level (FB
FB_FAULT_PEAK
fault peak function is selected) the FB fault timer duration
is reduced – i.e. the timer is speed up by multiplication
K
.
FB_PEAKFT_MULT
Figure 39. Internal FB Fault Management
The controller disables driver pulses and enters protection
mode once the FB fault event is confirmed by the FB fault
timer. Latched or auto−recovery operation is then
triggered – depends on selected IC option. The controller
overload operation and/or open FB pin conditions. The
primary current is naturally limited by the NCP13994
on−time modulation principle in this case. But the primary
current increases when the output terminals are shorted. The
NCP13994 controller will maintain zero voltage switching
operation in such case, however high currents will flow
through the power MOSFETS, transformer winding and
secondary side rectification. The NCP13994 implements a
dedicated secondary side short circuit protection system that
will shut down the controller much faster than the regular FB
fault event in order to limit the stress of the power stage
components. The CS pin signal is monitored by the
dedicated CS fault comparator − refer to Figure 37. The CS
fault counter is incremented each time the CS fault
comparator is triggered. The controller enters
auto−recovery or latched protection mode (depending on IC
option) in case the CS fault counter overflows refer to
Figure 40. The CS fault counter is then reset once the CS
adds an auto−recovery off−time period (t ) and
A−REC_TIMER
restarts the operation via soft start in case of auto−recovery
option. The application temperature runaway is thus
avoided in case of overload while the automatic restart is still
possible once the overload condition disappears. The IC
with latched FB fault option stays latched−off, supplied by
the HV startup current source working in DSS mode, until
the V
threshold is reached on the VCC pin or Line
CC_RESET
event is detected by HV pin – i.e. until user unplug power
supply from the mains.
Please refer to Figure 53 and Figure 54 for an illustration
of the NCP13994 FB fault detection block.
Secondary Short Circuit Detection with Primary and
Secondary Current Reduction
The protection system described previously, implemented
via FB pin voltage level detection, prevents continuous
fault comparator is inactive for at least N
CS_FAULT_DEC
Mupper upcoming pulses. This digital filtering improves CS
fault protection system noise immunity.
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NCP13994
Figure 40. NCP13994 CS Fault Principle
Dedicated Startup Sequence and Soft−Start
The CS fault comparator event increases Ramp
compensation (RC) gain by an increment K
that is a portion of selected nominal RC gain. The RC gain
is reduced to nominal level by a decrement when event of CS
Hard switching conditions can occur in a resonant SMPS
application when the resonant tank operation is started with
50 % duty cycle symmetry – refer to Figure 41. This hard
switching appears because the resonant tank initial
conditions are not optimal for the clean startup.
RC_GAIN_INC
fault cmp. is not present for N
Mupper driver
CS_FAULT_DEC
pulses. The decrement that is equal to increment is then
placed at each followed Mupper driver pulse until RC gain
reach nominal value or new CS fault cmp. event is detected.
Figure 41. Hard Switching Cycle Appears in the LLC Application when Resonant Tank is Excited by 50 % Duty
Cycle During Startup
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NCP13994
The initial resonant capacitor voltage level can differ
note that the magnetizing inductance does not participate in
resonance in this case. However, if the application starts−up
when the output capacitors is charged and there is no load
connected to the output, the secondary rectification diodes
is not conducting during each switching cycle of startup
sequence and thus the resonant frequency of resonant tank
is affected also by the magnetizing inductance. In this case,
the resonant frequency is much lower than in case of startup
into loaded/discharged output.
These facts show that a clean, hard switching free and
parasitic oscillation free, startup of an LLC converter is not
an easy task, and cannot be achieved by duty cycle
imbalance and/or simple resonant capacitor pre−charge to
Vbulk/2 level. These methods only work in specific startup
conditions.
depending on how long delay was placed before application
operation restart. The resonant capacitor voltage is close to
zero level when application restarts after very long delay –
for example several seconds, when the resonant capacitor is
discharged by leakage to the power stage. However, the
resonant capacitor voltage value can be anywhere between
Vbulk and 0 V when the application restarts operation after
a short period of time – like during periodical SMPS
turn−on/off. Another factor that plays significant role during
resonant power supply startup is the actual load impedance
seen by the power stage during the first pulses of startup
sequence. This impedance is not only defined by resonant
tank components but also by the output loading conditions
and actual output voltage level. The load impedance of
resonant tank is low when the output is loaded and/or the
output voltage is low enough to made secondary rectifies
conducting during first switching cycles of startup phase.
The resonant frequency of the resonant tank is given by the
resonant capacitor capacitance and resonant inductance −
This explains why the NCP13994 implements a
proprietary startup sequence − see Figure 42 and Figure 43.
The resonant capacitor is discharged down to V
HB_MIN
before any application restart − except when restarting from
skip mode.
Figure 42. Initial Resonant Capacitor Discharge before Dedicated Startup Sequence is Placed
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NCP13994
Figure 43. Dedicated Startup Sequence Detail
The resonant capacitor discharging process is simply
between previous Mupper turn−off event and upper
ZVS condition detection is equal or higher than two
times of the the previous Mupper pulse conduction
period
implemented by activating an internal current limited switch
connected between the HB pin and IC ground – refer to
Figure 42. This technique assures that the resonant capacitor
energy is dissipated in the controller without ringing or
oscillations that could swing the resonant capacitor voltage
to a positive or negative level. The controller detects that the
discharge process is complete via HB pin voltage level
monitoring. The discharge switch is disabled once the HB
b. The Mupper switch is activated for previous Mupper
conduction period in case the measured time
between previous Mupper turn−off event and upper
ZVS condition detection is lower than two times of
previous Mupper pulse conduction period
pin voltage drops below the V
threshold.
c. ZVS condition is not detected due to low or no
positive voltage swing on HB pin. Internal logic is
waiting for ZVS information without any time
limitation – i.e. stuck state. The stuck state can be
HB_MIN
The dedicated startup sequence continues by activation of
the Mlower driver output for Tl1 period (refer to Figure 43).
This technique ensures that the bootstrap capacitor is fully
charged before the first high−side driver pulse is introduced
by the controller. The first Mupper switch on−time Tup1
period is fixed and depends on the application parameters.
This period can be adjusted internally – various IC options
interrupted by IC reset (via V
by startup watchdog timer.
threshold) or
CC_RESET
The startup period then depends on the previous
condition. Another blank Mlower switch period is placed by
the controller in case condition a) occurred. A normal
Mlower driver pulse, with DC of 50 % to previous Mupper
DRV pulse, is placed in case condition b) is fulfilled.
The dedicated startup sequence is placed after the
resonant capacitor is discharged (refer to Figure 42 and
Figure 43) in order to exclude any hard switching cycles
during the startup sequence. The first Mupper switch cycle
in startup phase is always non−ZVS cycle because there is
no energy in the resonant tank to prepare ZVS condition.
However, there is no energy in the resonant tank at this time,
are available. The Mupper switch is released after T
up1
period and it is not followed by the Mlower switch
activation. The controller waits for a new ZVS condition for
Mupper switch instead and measures actual resonant tank
conditions this way. The Mupper switch is then activated
again after the Mlower blank period is used for measurement
purposes. The second Mupper driver conduction period is
then dependent on the previously measured conditions:
a. The Mupper switch is activated for 3/2 of previous
Mupper conduction period in case the measured time
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NCP13994
there is also no possibility that the power stage MOSFET
the first Mupper on−time duration can be incremented up to
two times of preselected first Mupper duration. The IC will
provide the first Mlower and first Mupper DRV pulses with
body diodes conducts any current. Thus the hard
commutation of the body diode cannot occur in this case.
The IC will not start and provide regular driver output
pulses until it is placed into the target application, because
the startup sequence cannot be finished until HB pin signal
is detected by the system. The IC features a startup watchdog
a t
off−time in−between startup attempts.
WATCHDOG
Soft−start
The dedicated startup sequence is complete when
condition b) from previous chapter is fulfilled and the
controller continues operation with the soft−start sequence.
A fully digital non−linear soft−start sequence has been
implemented in NCP13994 using a soft−start counter and
D/A converter that are gradually incremented by the Mlower
driver pulses. A block diagram of the NCP13994 soft−start
system is shown in Figure 44.
timer (t ) which restarted a dedicated startup
WATCHDOG
sequence periodically in case the IC is powered without
application (during bench testing) or in case the startup
sequence is not finished correctly. The first Mupper on−time
duration is automatically incremented when IC is restarted
by the startup watchdog (depends on IC option). The
increment is a portion of selected first Mupper duration and
Figure 44. Soft−start Block Internal Implementation
The soft−start block subsystems and operation are
described below:
for the Soft−Start counter can be divided down by
the SS clock divider (K ) in case the
FB_SS_INC
1. The Soft−Start counter is a unidirectional counter
that is loaded with the last Mupper on−time value
that is reached at the dedicated startup sequence end
(i.e. during condition b occurrence explained in
previous chapter). The on−time period used in the
initial period of the soft−start sequence is affected by
the first Mupper on−time period selection and the
dedicated startup sequence processing. The
Soft−Start counter counts up from this initial on time
period to its maximum value which corresponds to
soft−start period needs to be prolonged further – this
can be also done via IC option selection. The
Soft−Start period is terminated (i.e. the counter is
loaded to its maximum) when the FB pin voltage
drops below V
level or FB pin detect that
FB_SKIP_IN
application is under regulation.
2. The ON−time counter is a bidirectional counter that
is used as a main system counter for on−time
modulation during soft−start, normal operation or
overload conditions. The ON−time counter
counts−up during Mupper switch conduction period
and then counts down to zero – defining Mlower
switch conduction period. This technique assures
perfect 50 % duty cycle symmetry for both power
switches as afore mentioned. The ON−time counter
count−up mode can be switched to the count−down
the IC maximum on−time (t
). The
TON_MAX
Soft−Start counter is incremented by the soft−start
increment number (t ) during each
TON_SS_INC
Mlower switch on−time period. The soft−start start
increment, selectable via IC option, thus affects the
soft−start time duration. The Mlower clock signal
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31
NCP13994
st
mode by either of two events: 1 when the ON−time
is activated, or until ON−time comparator takes
action and overrides the Maximum ON−time
comparator.
counter value reaches the maximum on−time value
nd
(t
) or 2 when the actual Mupper on−time
TON_MAX
is terminated based on the current sense input
information – i.e. by ON−time comparator. 3
5. The Soft−Start D/A converter generates a soft−start
voltage ramp for ON−time comparator input
4. The Maximum ON−time comparator compares the
actual ON−time counter value with the maximum
synchronously
with
Soft−Start
counter
incrementing. The internal FB signal for ON−time
comparator input is artificially pulled−down and
then ramped−up gradually when soft−start period is
placed by the system – refer to Figure 45. The FB
loop is supposed to take over at certain point when
regulation loop is closed and output gets regulated so
that soft−start has no other effect on the on−time
modulation. The Soft−Start counter continues
counting−up until it reaches its maximum value
which corresponds to the IC maximum on−time
value – i.e. the IC minimum operating frequency.
The Soft−Start period is terminated (i.e. counter is
loaded to its maximum) when the FB pin voltage
on−time value (t
) and activates the latch
TON_MAX
(or auto−recovery) protection mode once IC detect
requested number of TON_MAX events. The
minimum operating frequency of the controller is
defined the same way. The Maximum ON−time
comparator reference is loaded by the Soft−Start
counter value on each switching cycle during
soft−start. The Maximum ON−time fault signal is
ignored during Soft−Start operation. The converter
Mupper switch on−time (and thus operating
frequency) is thus defined by the Soft−Start counter
value indirectly
– via Maximum ON−time
comparator. The Mupper switch on−time is
increased until the Soft−Start counter reaches
drops below V
output evolve accordingly to the Soft−Start counter
level. The D/A converter
FB_SKIP_IN
t
period and Maximum on−time protection
as it is loaded from its output data bus.
TON_MAX
Figure 45. Soft Start Behavior
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32
NCP13994
The Controller Operation During Soft−start Sequence
Evolves as Follows:
comparator reference voltage. This reference voltage thus
also increases non−linearly from initial zero level until the
level at which the current mode regulation starts to work.
The on−time of the Mupper and Mlower switch is then
defined by the ON−time comparator action instead of the
Maximum ON−time comparator. The soft−start then
continues until the regulation loop is closed and the on−time
is fully controlled by the secondary regulator. The Soft−Start
counter then continues in counting and saturates at its
maximum possible value which corresponds to IC minimum
operating frequency. The maximum on−time fault detection
system is enabled when Soft−Start counter value is equal to
The Soft−Start counter is loaded by last Mupper on−time
value at the end of the dedicated startup sequence. The
ON−time counter is released and starts count−up from zero
until the value that is equal to the actual Soft−Start counter
state. The Mupper switch is active during the time when
ON−time counter counts−up. The Maximum ON−time
comparator then changes counting mode of the ON−time
comparator from count−up to count−down. A dead−time is
placed and the Mlower switch is activated till the ON−time
counter reaches zero value. The Soft−Start counter is
incremented by selected increment during corresponding
Mlower on−time period so that the following Mupper switch
on−time is prolonged automatically – the frequency thus
drops naturally. Because the operating frequency of the
controller drops and Mlower DRV signal is used as a clock
source for the Soft−start counter, the soft−start speed starts
to decrease on each (or on each N−th) Mlower driver pulse
t
value.
TON_MAX
The previous on−time repetition feature, described above
in the ON−time modulation and feedback loop chapter, is
disabled in the beginning of soft start period. This is because
the ON−time comparator output stays high for several cycles
of soft start period – until the current mode regulation takes
over. The previous on−time repetition feature is enabled
once the current modulation starts to work fully, i.e. in the
time when the ON−time comparator output periodically
drops to low state within actual Mupper switch on−time
period. Typical startup waveform of the LLC application
driven by NCP13994 controller can be seen in Figure 46.
(where N is defined by K
) of switching cycle. So
FB_SS_INC
we have non−linear soft−start that helps to speed up output
charging in the beginning of the soft−start operation and
reduces the output voltage slope when the output is close to
the regulation level. The output bus of the Soft−Start counter
addresses the D/A converter that defines the ON−time
Figure 46. Application Startup with NCP13994 − Primary Current − Green, Vout − Magenta
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33
NCP13994
Skip Mode Operation
preselected level. Zero voltage switching technique is still
present for the power switches to achieve high light load
efficiency. Quiet skip mode operation is initiated when load
drops further and FB voltage drops below another FB
threshold that is user adjustable on the skip pin. The
frequency of skip burst is regulated by internal digital
controller around preselected quiet skip frequency clamp in
order to reduce acoustic noise. The skip frequency then
drops to very low values during no−load conditions. Refer
to Figure 47, Figure 48 and Figure 49 for typical application
waveforms during light load and quiet skip mode operating
modes.
Then NCP13994 implements proprietary light load and
quiet skip mode operating techniques that improve light load
efficiency, reduce no−load power consumption and
significantly reduce acoustic noise. Controller uses 50 %
duty cycle symmetry under full and medium load
conditions. Normal current mode frequency modulation
takes place during this operating mode – refer to on−time
processing section of this datasheet. The 50 % duty cycle
symmetry operating mode is replaced by continues
operation with minimum switching patterns repeated after
controlled amount of off−time when load is decreased below
Figure 47. No−load Operation
Figure 48. Quiet Skip Mode Operation
Figure 49. Light−load Operation
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NCP13994
The High Voltage Half−bridge Driver
architecture of the drivers section. The device incorporates
The driver features a traditional bootstrap circuitry,
requiring an external high voltage diode with resistor in
series for the capacitor refueling path. Minimum series
resistor Rboot value is 3.3 W. Figure 50 shows the internal
an upper UVLO circuitry that makes sure enough V is
GS
available for the upper side MOSFET. The output drivers are
clamped to specific value to protect MOSFET gates when
VCC/VBOOT is higher than 20 V.
HV
Vboot
DRV
Clamp
Internal Mupper
Pulse
Trigger
Level
Shifter
Cboot
S
R
Mupper
Q
Q
HB
dV/dt_P signal
dV/dt_N signal
dV/dt
detector
Rboot
Dboot
UVLO
HB
discharger
V
CC
aux
HB disch. activation
V
CC
DRV
Clamp
Fault
Mlower
GND
Internal Mlower
Delay
CV
+
CC
Figure 50. The NCP13994 Internal DRVs Structure
Automatic Dead−time Adjust
The internal dV/dt sensor detects the HB pin voltage
transitions in order to setup the optimum DT period – please
refer to Dead−Time chapter. The internal HV discharge
switch is connected to the HB pin and discharges resonant
capacitor before application startup. The current through the
The dead−time period between the Mupper and Mlower
drivers is always needed in half bridge topologies to prevent
any cross conduction through the power stage MOSFETs
that would result in excessive current, high EMI noise
generation or total destruction of the application. Fixed
dead−time period is often used in the resonant converters
because this approach is simple to implement. However, this
method does not ensure optimum operating conditions in
resonant topologies because the magnetizing current is
changing with line and load conditions. The optimum
dead−time, under a given operating conditions, is equal to
the time that is needed for bridge voltage to transition
between upper and lower states and vice versa – refer to
Figure 51.
switch is regulated to I
level until the
HB_DISCHARGE1
V
threshold voltage is reached on the HB pin. The
HB_MIN
discharge system assures always the same startup conditions
for application – regardless of previous operating state. The
HB pin discharge current sink features an independent
over−temperature protection which limits its input current in
case the discharger temperature exceeds T
HB_DISCH_CLAMP
to avoid damage to the HB discharger silicon structure.
As stated in the maximum ratings section, the floating
portion can go up to 730 VDC on the BOOT pin. This
voltage range makes the IC perfectly suitable for offline and
lighting applications.
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NCP13994
Figure 51. Optimum Dead−time Period Adjust
The MOSFET body diode conduction time is minimized
example with extremely low bulk voltage or when some
critical failure occurs. This situation should not occur
normally in correctly designed application because several
other protections would prevent such a situation. The
NCP13994 implements maximum DT period clamp that
when optimum dead−time period is used which results in
maximum efficiency of a resonant converter power stage.
There are several methods to determine the optimum
dead−time period or to approximate it (for example using
auxiliary winding on main transformer or modulating
dead−time period with operating frequency of the
converter). These approaches however require a dedicated
pin for nominal dead−time adjust or auxiliary winding
voltage sensing. The NCP13994 uses a dedicated method
that senses the HB pin voltage internally and adjusts the
optimum dead−time period with respect to the actual
operating conditions of the converter. The high−voltage
dV/dt detector, connected to the HB pin, delivers two
internal digital signals that are indicating Mupper to Mlower
and Mlower to Mupper transitions that occur on the HB and
VBOOT pins after the corresponding MOSFET switch is
turned−off. The controller enables the opposite MOSFET in
the power stage once the corresponding dV/dt sensor output
provides information about HB (or VBOOT) pin transition
ends.
limits driver’s off−time period to the t
value. The
DT_MAX
corresponding MOSFET driver is forced to turn−on by the
internal logic regardless of missing dV/dt sensor signal. This
situation does not occur during normal operation and will be
considered a fault state by the device. There are several
possibilities on how the controller continues operation after
this event occurrence – depending on the IC option:
1. The opposite MOSFET switch is forced to turn−on
when t
period elapses and no fault is
DT_MAX
generated
2. The controller is latched−off in case the ZSV
condition is not detected within selected t
period
DT_MAX
3. The controller stops operation and restarts operation
after auto−recovery period in case the ZSV
condition has not been detected within the selected
The ZVS transition on the bridge pin (HB) could take a
longer time or even does not finish in some cases – for
t
period
DT_MAX
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36
NCP13994
A DT fault counter option is available. Selected number
(N ) or DT fault events have to occur in order to
confirm DT fault in this case.
A fixed DT option is also available for this device. The
internal dV/dt sensor signal is not used for this device option
the HV start−up in DSS mode) in order to memorize the TSD
event information. When the temperature falls below the
lower threshold, the full restart (including soft−start) is
initiated by the controller. The HV startup current source
features an independent over−temperature protection which
limits its output current in case the DIE temperature exceeds
TSD to avoid damage to the HV startup silicon structure.
DT_MAX
and the t
period is used as a regular DT period
DT_MAX
instead. The DT fault detection is disabled in this case.
Temperature Shutdown
Recommended Layout
The NCP13994 includes a temperature shutdown
protection. When the temperature rises above the upper
threshold, the controller stops switching instantaneously,
and goes into the off−mode with extremely low power
The correct layout is key step towards to reliable operation
of designed application. The recommended layout of
NCP13994 controller is illustrated on Figure 52. The most
important part of layout is connection of the GND path.
consumption. The V supply is maintained (by operating
CC
Figure 52. Recommended Layout
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37
NCP13994
APPLICATION INFORMATION
Controller Operation Sequencing of NCP13994 LLC
Controller
The paragraphs below describe controller operation
sequencing under several typical cases as well as transitions
between them.
VCC management controls the HV startup in DSS mode in
order to keep enough VCC level to hold the latch−up state
memorized while the application remains plugged−in to the
mains.
The power supply is removed from the mains at point H
and the VCC voltage drops down below
Application Start, Brown−out Off and Restart, OVP/OTP
Latch and then Restart – Figure 53
Application is connected to the mains at point A thus the
HV input of the controller becomes biased. The HV startup
V
level thus the controller is released from latch.
CC_RESET
A new application start occurs when the user plugs the
application the mains again.
current source starts charged VCC capacitor until V
Application Start, Brown−out Off and Restart, Output
Short Fault with Auto−recovery Restart – Figure 54
Operating waveforms descriptions for this figure is
similar to one for Figure 53 from point A till point G.
The LLC converter operation is stopped in point G
because the controller detects an overload condition (short
circuit event in this case as the Vout drops abruptly). The
controller disables almost all blocks. The HV startup DSS
operation is initiated in order to keep enough VCC level for
all internal blocks that need to be biased. Internal
auto−recovery timer counts down the recovery delay period
CC
reaches V
threshold.
CC_ON
The all analog blocks are enabled at V
threshold. A START_BLANK is activated at V
CC_RESET
CC_RESET
threshold also to ensure that the internal blocks are fully
biased and stabilized to correctly process conditions/faults
before IC start. The VCC pin voltage reached V
CC_ON
threshold in point B. The PFC front stage is activated via
PFC MODE pin that change status at mentioned threshold.
The IC DRVs were not enabled after first V
threshold
CC_ON
in this case as the voltage on VBULK is not enough high.
The IC keeps all internal blocks biased and operates in the
DSS (Dynamic Self−Supply) mode as long as the stop
conditions is still present.
t
.
A−REC_TIMER
The auto−recovery restart delay period lapses at point H.
The HV startup current source is activated to recharge VCC
capacitor before a new restart and all block are enabled with
START_BLANK period.
The BO_OK condition is received (voltage on VBULK
reach V level affected by hysteresis) at point C. The IC
BO
activates the startup current source to refill VCC capacitor
in order to assure sufficient energy for a new startup. The
The V
threshold is reached in point I. The controller
CC_ON
restores operation via the regular startup sequence and
soft−start after all startup condition are fulfil (no fault or stop
VCC capacitor voltage reaches V
level again. The
CC_ON
DRVs are enabled and the application is started because
there is no faults or stop condition at that time.
Line and also bulk voltage drops at point D so the BO_OK
condition detected and VCC is higher when V
CC_ON
threshold). The LLC converter operation is enabled,
including a dedicated startup and soft−start period. The
output short circuit is removed in between thus the Vout
ramped−up and the FB loop took over during the LLC
converter soft−start period.
signal become low (voltage on VBULK drops below V
BO
level). The LLC DRVs are disabled as well as OVP/OTP
block bias. The PFC MODE output stay high to keep the
PFC controller biased, so the BO block still monitors the
bulk voltage. The controller activates the HV startup current
source into DSS mode to keep enough VCC voltage for
operation of all blocks that are active while the IC is waiting
for BO_OK condition.
Startup, Skip−mode Operation, Low Line Detection and
Restart into Skip−mode – Figure 55
Application is connected to the mains at point A thus the
HV input of the controller becomes biased. The HV startup
current source starts charged VCC capacitor until V
CC
The line voltage and thus also bulk voltage increase at
point E so the Brown−out block provide the BO_OK signal
reaches V
threshold.
CC_ON
The all analog blocks are enabled at V
threshold. A START_BLANK is activated at V
CC_RESET
once the V (with hysteresis) level is reached. The startup
BO
CC_RESET
current source is activated after BO_OK signal is received
to charge the VCC capacitor for a new restart. The analog
blocks are enabled (biased) including START_BLANK
period at time when BO_OK signal is received.
threshold also to ensure that the internal blocks are fully
biased and stabilized to correctly process conditions/faults
before IC start. The VCC pin voltage reached V
CC_ON
threshold in point B. The PFC front stage is activated via
PFC MODE pin that change status at mentioned threshold.
The V
level is reached in point F. The controller
CC_ON
restores operation via the regular startup sequence and
soft−start after all startup condition are fulfil (no fault or stop
The IC DRVs were not enabled after first V
threshold
CC_ON
in this case as the voltage on VBULK is not enough high.
The IC keeps all internal blocks biased and operates in the
DSS (Dynamic Self−Supply) mode as long as the stop
conditions is still present.
condition detected and VCC is higher when V
threshold).
CC_ON
The application then operates normally until the
OVP/OTP input is pulled−up at point G. The controller then
enters latch−off mode in which all blocks are disabled. The
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38
NCP13994
The controller authorizes DRVs at point C as there are no
condition detected and VCC is higher when V
CC_ON
faults conditions present. The load current is reduced thus
the FB loop reduces the primary controller FB pin voltage.
The load diminished further and the FB skip threshold is
reached in point D. The controller turns−off all the blocks
that are not essential for the controller operation during
skip−mode – i.e. all blocks except FB block and VCC
management. This technique is used to minimize the device
consumption when there are no driver pulses during
skip−mode operation. The output voltage then drops
naturally and the FB loop reflects this change into the
primary FB pin voltage that increases accordingly. The
auxiliary winding is refilling VCC capacitor during each
skip burst thus the controller is supplied from the application
during the skip mode operation.
The controller FB skip−out threshold is reached in point
E; the controller enables all blocks and LLC DRVs to refill
the output capacitor. The controller did not activate the HV
startup current source because there is enough voltage
present on the VCC pin during skip mode. The OTP blank
periods is activated at the beginning of the skip burst to mask
possible OTP faults.
threshold). The application then enters skip mode again as
the load current is low.
Start−up, Normal Operation, Transition to Off−mode
Operation and Output Re−charge in Off−mode – Figure 38
Operating waveforms descriptions for this figure are the
same as for Figure 55 from point A until point C – Please
refer to Figure 55 for details regarding operation between
these time events.
The secondary controller activates off−mode operation by
pulling FB pin below V
level, thus the IC goes
FB_REM_OFF
into skip−mode for long time at point D. The controller
turns−off all the blocks that are not essential for controller
operation during skip−mode – i.e. all blocks except FB and
VCC management blocks. This technique is used to
minimize device consumption when there are no driver
pulses during skip−mode operation.
The V
drops naturally by IC consumption below
CC
V
threshold at point E – i.e. the off−mode is
CC_OFF
confirmed. The controller turns−off all the blocks that are
not essential for controller operation during off−mode – i.e.
all blocks including FB block and big portion of the VCC
management. This technique is used to minimize device
consumption when there are no drive pulses during
off−mode operation. The output voltage is then dropped
naturally due to secondary controller and resistive dividers
consumption. The primary controller is supplied from the
HV startup current source that operates in DSS mode.
The secondary controller interrupts off−mode operation
by releasing the opto−coupler and allowing the voltage on
FB pin to ramp−up by the internal pull−up current source at
point F. The controller activates the HV startup current
source and recharges the VCC capacitor to prepare enough
NOTE: The VCC capacitor needs to be chosen with a
value high enough to ensure that V will not drop
CC
below the V
level during skip mode. The
CC_OFF
device would enters into off−mode (refer to
Figure 38) when appropriate off−mode is enabled.
The line voltage drops in point F, but the bulk voltage is
dropping slowly as there is nearly no consumption from the
bulk capacitor during skip mode – only some refilling bursts
are provided by the controller. The application thus
continues in skip mode operation for several skip burst
cycles.
The bulk voltage level less than V threshold is detected
BO
V
CC
voltage for a new startup.
by the controller in point G during one of the skip burst
pulses. The controller thus disabled DRVs and enters DSS
mode of operation in which the OVP/OTP block is disabled
and the controller is waiting for BO_OK event. The PFC
The V voltage reaches V
the LLC converter starts (including soft−start).
The output voltage is ramped up while the FB loop is not
threshold at point Gand
CC
CC_ON
closed yet as the V
is still below regulation level. The
OUT
MODE provides the V
voltage in this case to
PFCM_REG1
output voltage then reaches regulation level and the FB pin
voltage drops abruptly on the primary – hitting the FB
skip−in threshold at point H. The LLC drivers are thus
disabled by the skip comparator. The FB then increases
naturally – calling for new skip burst (refer to skip mode
operation description in previous text).
allow the PFC stage to refill bulk capacitors.
The line voltage is increased at point H thus the controller
receives the BO_OK signal. The startup current source is
activated after BO_OK signal is received to charge the VCC
capacitor for a new restart. The analog blocks are enabled
(biased) including START_BLANK period at time when
BO_OK signal is received.
The secondary controller activates off−mode operation by
pulling−down FB pin and V
voltage naturally drops
CC
The V
level is reached in point I. The controller
CC_ON
below V
threshold. The primary controller enters
CC_OFF
restores operation via the regular startup sequence and
soft−start after all startup condition are fulfil (no fault or stop
off−mode operation again at point I.
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NCP13994
Figure 53. Application Start, Brown−out Off and Restart, OVP/OTP Latch and then Restart
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NCP13994
Figure 54. Application Start, Brown−out Off and Restart, Output Short Fault with Auto−recovery Restart
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NCP13994
Figure 55. Startup, Skip−mode Operation, Low Line Detection and Restart into Skip
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NCP13994
Figure 56. Start−up, Normal Operation, Transition to Off−Mode Operation and Output Re−charge in Off−mode
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NCP13994
ORDERING INFORMATION
Device
†
Package Marking
Package Type
Shipping
NCP13994AADR2G
NCP13994AA
SOIC−16 NB MISSING PINS 2 AND 13
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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44
NCP13994
PACKAGE DIMENSIONS
SOIC−16 NB MISSING PINS 2 AND 13
CASE 751DU
ISSUE O
NOTE 5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
D
A
2X
16
9
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS
OR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE. DIMEN
SIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
0.10 C D
F
NOTE 4
E
E1
NOTE 6
A1
L
L2
1
8
0.20 C
SEATING
PLANE
C
MILLIMETERS
B
NOTE 5
14X b
DETAIL A
2X 4 TIPS
DIM MIN
MAX
1.75
0.25
0.49
0.25
10.00
M
0.25
C A-B
D
A
A1
b
1.35
0.10
0.35
0.17
9.80
TOP VIEW
2X
c
0.10 C A-B
0.10 C
DETAIL A
D
D
E
6.00 BSC
3.90 BSC
1.27 BSC
0.10 C
E1
e
L
0.40
1.27
L2
0.203 BSC
e
END VIEW
A
SEATING
C
PLANE
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT
14X
1.52
16
1
9
7.00
8
14X
0.60
1.27
PITCH
DIMENSIONS: MILLIMETERS
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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