NCP13992AFDR2G [ONSEMI]
电流模式谐振控制器,带集成式高电压驱动器,高性能;型号: | NCP13992AFDR2G |
厂家: | ONSEMI |
描述: | 电流模式谐振控制器,带集成式高电压驱动器,高性能 驱动 控制器 驱动器 |
文件: | 总33页 (文件大小:663K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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Current Mode Resonant
Controller with Integrated
High-Voltage Drivers, High
Performance
16
1
SOIC−16 NB
(LESS PINS 2 AND 13)
D SUFFIX
CASE 751DU
NCP13992
MARKING DIAGRAM
The NCP13992 is a high performance current mode controller for
half bridge resonant converters. This controller implements 600 V
gate drivers, simplifying layout and reducing external component
count. The built−in Brown−Out input function eases implementation
of the controller in all applications. In applications where a PFC front
stage is needed, the NCP13992 features a dedicated output to drive the
PFC controller. This feature together with quiet skip mode technique
further improves light load efficiency of the whole application. The
NCP13992 provides a suite of protection features allowing safe
operation in any application. This includes: overload protection,
over−current protection to prevent hard switching cycles, brown−out
detection, open optocoupler detection, automatic dead−time adjust,
over−voltage (OVP) and over−temperature (OTP) protections.
16
NCP13992xy
AWLYWWG
1
NCP13992 = Specific Device Code
xy
A
WL
Y
WW
G
= Specific Device Option
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
PIN CONNECTIONS
• High−Frequency Operation from 20 kHz up to 750 kHz
• Current Mode Control Scheme
1
HV
16 VBOOT
15 HB
• Automatic Dead−time with Maximum Dead−time Clamp
• Dedicated Startup Sequence for Fast Resonant Tank Stabilization
• Light Load Operation Mode for Improved Efficiency
• Quiet Skip Operation Mode for Minimize Transformer Acoustic Noise
• Latched or Auto−Recovery Overload Protection
• Latched or Auto−Recovery Output Short Circuit Protection
• Latched Input for Severe Fault Conditions, e.g. OVP or OTP
• Out of Resonance Switching Protection
14
3
4
5
6
VBULK/PFCFB
SKIP
MUPPER
LLCFB
12 MLOWER
11
10
9
LLCCS
GND
OVP/OTP
FBFREEZE
VCC
7
8
PFCMODE
(Top View)
• Open Feedback Loop Protection
• Precise Brown−out Protection
• PFC Stage Operation Control According to Load Conditions
• Startup Current Source with Extremely Low Leakage Current
• Dynamic Self−Supply (DSS) Operation in Off−mode or Fault Modes
• Pin to Adjacent Pin / Open Pin Fail Safe
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
• These are Pb−Free Devices
Typical Applications
• Adapters and Offline Battery Chargers
• Flat Panel Display Power Converters
• Computing Power Supplies
• Industrial and Medical Power Sources
This document contains information on some products that are still under development.
onsemi reserves the right to change or discontinue these products without notice.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
August, 2022 − Rev. 13
NCP13992/D
NCP13992
Figure 1. Typical Application Example without PFC Stage − WLLC Design
Figure 2. Typical Application Example with PFC Stage
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2
NCP13992
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Pin Description
1
HV
High−voltage startup
current source input
Connects to rectified AC line or to bulk capacitor to perform functions of Start−
up Current Source and Dynamic Self−Supply
2
3
NC
Not connected
Increases the creepage distance
VBULK /
PFC FB
Bulk voltage monitoring input Receives divided bulk voltage to perform Brown−out protection.
4
5
SKIP
Skip threshold adjust
LLC feedback input
Sets the skip in threshold via a resistor connected to ground
LLC FB
Defines operating frequency based on given load conditions. Activates skip
mode operation under light load conditions.
6
LLC CS
LLC current sense input
Senses divided resonant capacitor voltage to perform on−time modulation, out
of resonant switching protection, over−current protection and secondary side
short circuit protection.
7
8
9
OTP / OVP
FB FREEZE
PFC MODE
Over−temperature and
Implements over−temperature and over−voltage protection on single pin.
over−voltage protection input
Minimum internal FB level
Adjusts minimum internal FB level that can be reached during light load oper-
ation.
PFC and external HV
switch control output
Provides supply voltage for PFC front stage controller and/or enables Vbulk
sensing network HV switch.
10
11
VCC
GND
Supplies the controller
Analog ground
The controller accepts up to 20 V on VCC pin
Common ground connection for adjust components, sensing networks and
DRV outputs.
12
13
14
15
16
MLOWER
NC
Low side driver output
Not connected
Drives the lower side MOSFET
Increases the creepage distance
Drives the higher side MOSFET
Connects to the half−bridge output.
The floating VCC supply for the upper stage
MUPPER
HB
High side driver output
Half−bridge connection
Bootstrap pin
VBOOT
Figure 3. Internal Circuit Architecture
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3
NCP13992
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 600
−0.3 to 5.5
Unit
V
HV Startup Current Source HV Pin Voltage (Pin 1)
VBULK/PFC FB Pin Voltage (Pin3)
SKIP Pin Voltage (Pin 4)
V
HV
BULK/PFC FB
V
V
V
SKIP
−0.3 to 5.5
V
LLC FB Pin Voltage (Pin 5)
V
−0.3 to 5.5
V
FB
CS
LLC CS Pin Voltage (Pin 6)
V
−5 to 5
V
PFC MODE Pin Output Voltage (Pin 9)
VCC Pin Voltage (Pin 10)
V
−0.3 to VCC+0.3
−0.3 to 20
V
PFC MODE
V
V
CC
DRV_MLOWER
Low Side Driver Output Voltage (Pin 12)
High Side Driver Output Voltage (Pin 14)
High Side Offset Voltage (Pin 15)
High Side Floating Supply Voltage (Pin 16)
High Side Floating Supply Voltage (Pin 15 and 16)
Allowable Output Slew Rate on HB Pin (Pin 15)
OVP/OTP Pin Voltage (Pin 7)
V
−0.3 to VCC + 0.3
V
V
V
– 0.3 to V
BOOT
+ 0.3
+0.3
V
DRV_MUPPER
HB
V
HB
V
−20 to V
Boot
V
Boot
V
BOOT
−0.3 to 620
−0.3 to 20.0
50
V
V
V
Boot–VHB
dV/dt
V/ns
V
max
V
−0.3 to 5.5
−0.3 to 5.5
−50 to 150
−55 to 150
130
OVP/OTP
P ON/OFF
FB FREEZE Pin Voltage (Pin 8)
Junction Temperature
V
V
T
J
°C
°C
°C/W
kV
Storage Temperature
T
STG
Thermal Resistance Junction−to−air
R
θ
JA
Human Body Model ESD Capability per JEDEC JESD22−A114F
(except HV Pin – Pin 1)
−
4.5
Machine Model ESD Capability per JEDEC JESD22−A115C
−
−
250
1
V
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78
ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
HV STARTUP CURRENT SOURCE
V
Minimum voltage for current source operation
(V = V −0.5 V, I drops to 95%)
1
1
−
−
−
−
60
60
V
V
HV_MIN1
CC
CC_ON
START2
V
Minimum voltage for current source operation
(V = V −0.5 V, I drops to 5 mA)
HV_MIN2
CC
CC_ON
START2
I
I
Current flowing out of V pin (V = 0 V)
1, 10
1, 10
1
0.2
6
0.5
9
0.8
13
10
mA
mA
mA
START1
CC
CC
Current flowing out of V pin (V = V −0.5 V)
CC_ON
START2
CC
CC
I
Off−state leakage current (V = 500 V, V = 15 V)
−
−
START_OFF
HV
CC
SUPPLY SECTION
V
Turn−on threshold level, V going up
10
V
CC_ON
CC
(NCP13992AA, AC, AD, AE, AG, AJ, AK, AM, AN, AR, AT)
(NCP13992AB, AF, AH, AL, AP, AS, AU, AV, AW, AZ, CA,
CB)
15.3
11.5
15.8
11.9
16.3
12.3
V
Minimum operating voltage after turn−on
10
10
10
9.0
5.8
9.5
6.6
10
7.2
V
V
V
CC_OFF
V
V
CC
CC
level at which the internal logic gets reset
CC_RESET
CC_INHIBIT
V
V
level for I
to I
transition
0.40
0.80
1.25
START1
START2
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4
NCP13992
ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
SUPPLY SECTION
I
Controller supply current in skip−mode, V = 15 V,
10, 11
mA
CC_SKIP−MODE
CC
OVP/OTP block debiased during skip mode
(NCP13992AA, AD, AE, AF, AH, AK, AL, AN, AR, AU)
(NCP13992AB)
500
550
600
700
780
850
850
980
950
1100
1100
1250
(NCP13992AC, AG, AJ, AT, AW)
(NCP13992AM, AS, AZ, CA, CB)
I
Controller supply current in latch−off mode,
10, 11
mA
CC_LATCH
V
= V
− 0.2 V
CC
CC_ON
(AA, AC, AE, AF, AG, AH, AJ, AK, AL, AN, AR, AT, AW, CA,
350
−
450
570
670
900
700
1100
1300
CB)
(NCP13992AB, AZ)
(NCP13992AD, AS)
I
Controller supply current in auto−recovery mode,
10, 11
10, 11
mA
CC_AUTOREC
V
= V
− 0.2 V (AA, AC, AE, AF, AG, AH, AJ, AK,
AL, AM, AN, AR, AT, AU, AW, CA, CB)
(NCP13992AB, AZ)
CC
CC_ON
400
−
580
670
860
700
1100
1300
(NCP13992AS)
−
I
Controller supply current in normal operation,
= 100 kHz, C = 1 nF, V = 15 V
4.0
5.4
7.0
mA
CC_OPERATION
f
sw
load
CC
BOOTSTRAP SECTION
V
Startup voltage on the floating section (Note 3)
Cutoff voltage on the floating section
16, 15
16, 15
16, 15
16, 15
7.5
7.0
30
9.0
8.2
75
10.0
9.1
V
V
BOOT_ON
V
BOOT_OFF
I
I
Upper driver consumption, no DRV pulses
130
2.00
mA
mA
BOOT1
Upper driver consumption, C
= 1 nF between Pins 13 &
1.30
1.65
BOOT2
load
15 f = 100 kHz, HB connected to GND
sw
HB DISCHARGER
I
HB sink current capability V = 30 V
15
15
15
7
1
−
9.6
4.1
−
12
8
mA
mA
V
DISCHARGE1
DISCHARGE2
HB
I
HB sink current capability V = V
HB
HB_MIN
V
HB voltage @ I
changes from 2 to 0 mA
10
HB_MIN
DISCHARGE
DRIVER OUTPUTS
t
Output voltage rise−time @ C = 1 nF, 10−90% of output
12, 14
12, 14
20
5
45
30
80
50
ns
ns
r
L
signal
t
Output voltage fall−time @ C = 1 nF, 10−90% of output
f
L
signal
R
Source resistance
Sink resistance
12, 14
12, 14
12, 14
4
1
−
16
5
32
11
−
W
W
A
OH
R
OL
DRVSOURCE
I
Output high short circuit pulsed current
0.5
V
DRV
= 0 V, PW v 10 ms
I
Output high short circuit pulsed current
= VCC, PW v 10 ms
12, 14
−
−
1
−
A
DRVSINK
V
DRV
I
Leakage current on high voltage pins to GND
14, 15, 16
−
5
mA
HV_LEAK
DEAD−TIME GENERATION
t
Maximum Dead−time value if no dV/dt falling/rising edge is
received (AA, AC, AE, AF, AG, AH, AJ, AK, AM, AN, AP, AT,
AU, AV, CA, CB)
12, 14
ns
DEAD_TIME_MAX
720
120
380
800
190
450
880
295
530
(NCP13992AB, AD, AL, AR, AS)
(NCP13992AW)
N
Number of DT_MAX events to enters IC into fault
(NCP13992AC)
12, 14, 16
−
DT_MAX
−
16
−
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NCP13992
ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
dV/dt DETECTOR
P
Positive slew rate on V
pin above which is dV/dt_P
BOOT
16
16
−
−
178
226
200
250
V/ms
V/ms
dV/dt_th_1
sensor triggered, VHB rising from 0 to 100 V linearly (Note 2)
P
Positive slew rate on V pin above which is dV/dt_P
sensor triggered, VHB rising from 100 to 200 V linearly
(Note 2)
dV/dt_th_2
BOOT
P
Positive slew rate on V
sensor triggered, VHB rising from 200 to 400 V linearly
(Note 2)
pin above which is dV/dt_P
BOOT
16
−
246
280
V/ms
dV/dt_th_3
N
N
N
Negative slew rate on V
pin above which is dV/dt_N
16
16
16
−
−
−
163
290
250
−
−
−
V/ms
V/ms
V/ms
dV/dt_th_1
dV/dt_th_2
dV/dt_th_3
BOOT
sensor triggered, VHB falling from 100 to 0 V linearly
Negative slew rate on V pin above which is dV/dt_N
BOOT
sensor triggered, VHB falling from 200 to 100 V linearly
Negative slew rate on V pin above which is dV/dt_N
BOOT
sensor triggered, VHB falling from 400 to 200 V linearly
PFC MODE OUTPUT AND P ON/OFF ADJUST
V
PFC MODE output voltage when application enters skip
mode (inject 1 mA into the PFC MODE output)
9
9
9
9
−
−
6.00
−
0.1
6.25
−
V
V
PFC_M_OFF
V
PFC MODE output voltage when V < V
P ON/OFF
5.75
PFC_M_BO
PFC_M_ON
PFC_M_LIM
FB
(sink 1 mA current from PFC MODE output)
V
PFC MODE output voltage when V > V
V
−
V
FB
P ON/OFF
CC
0.4
(sink 20 mA current from PFC MODE output)
I
PFC MODE output current limit (V
< 2 V)
0.7
1.2
1.85
mA
PFC MODE
OVP/OTP
V
V
OVP threshold voltage (V
OTP threshold voltage (V
going up)
7
7
7
2.35
0.76
90
2.50
0.80
95
2.65
0.84
100
V
V
OVP
OTP
OTP
OVP/OTP
going down)
OVP/OTP
I
OTP/OVP pin source current for external NTC – during
normal operation
mA
I
OTP/OVP pin source current for external NTC – during
startup
7
180
190
200
mA
OTP_BOOST
t
Internal filter for OVP comparator
Internal filter for OTP comparator
Blanking time for OTP input during startup
7
7
7
7
7
32
200
14
37
330
16
44
500
18
ms
ms
ms
V
OVP_FILTER
t
OTP_FILTER
t
BLANK_OTP
V
V
OVP/OTP pin clamping voltage @ I
OVP/OTP pin clamping voltage @ I
= 0 mA
= 1 mA
1.0
1.8
1.2
2.4
1.4
3.0
CLAMP_OVP/OTP_1
CLAMP_OVP/OTP_2
OVP/OTP
OVP/OTP
V
START−UP SEQUENCE PARAMETERS
Initial Mlower DRV on−time duration
t
12
14
4.7
2.32
18.64
9.3
4.9
2.5
19.50
10
5.4
2.69
21.59
11
ms
ms
1st_MLOWER_TON
(NCP13992AD)
(NCP13992AS)
(NCP13992AW)
t
Initial Mupper DRV on−time duration
1st_MUPPER_TON
(NCP13992AA, AC, AE, AG, AK, AM, AN, AW)
(NCP13992AB, AD, AH, AR, AS)
(NCP13992AP)
0.72
0.15
0.99
1.55
0.44
1.8
0.79
0.20
1.1
0.88
0.25
1.21
1.9
0.57
2.2
1.54
(NCP13992AF, AT, AU)
(NCP13992AJ, AL)
1.7
0.5
(NCP13992AV, AZ)
(NCP13992CA, CB)
2.0
1.26
1.4
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NCP13992
ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
START−UP SEQUENCE PARAMETERS
t
On−time period increment during soft−start
12, 14
17
75
55.9
111.8
20
80
22
88
64.8
129.6
ns
SS_INCREMENT
(NCP13992AJ)
(NCP13992AS, AV)
(NCP13992AZ)
60
120
K
Soft−Start increment division ratio
12, 14
12, 14
−
SS_INCREMENT
(NCP13992AA, AK, AP, AS, AW)
(NCP13992AB, AC, AD, AG, AH, AJ, AM, AL, AN, AR, CB)
(NCP13992AE, AF, AT, AU, AV, CA)
−
−
−
−
4
8
2
1
−
−
−
−
(NCP13992AZ)
t
Time duration to restart IC if start−up phase is not finished
(NCP13992AA, AC, AE, AF, AG, AH, AJ, AK, AM, AL, AN,
AP, AR, AT, AU, AV, AZ, CA, CB)
ms
WATCHDOG
0.45
1.80
0.50
2.00
0.55
2.20
(NCP13992AB)
FEEDBACK SECTION
R
Internal pull−up resistor on FB pin
5
5
5
5
15
18
25
kW
−
FB
FB
K
V
FB
to internal current set point division ratio
1.92
4.60
4.4
2.00
4.95
4.6
2.08
5.30
4.8
V
Internal voltage reference on the FB pin
V
FB_REF
V
Internal clamp on FB input of On−time comparator referred
to external FB pin voltage
V
FB_CLAMP
V
Skip comparator hysteresis
(NCP13992AA, AC, AD, AJ)
(NCP13992AB, AK)
5
148
295
1
174
95
174
350
25
215
150
222
410
45
260
170
mV
V
FB_SKIP_HYST
(AE, AF, AH, AM, AL, AP, AR, AS, AU, AV, AZ, CA, CB)
(NCP13992AG, AN, AT)
(NCP13992AW)
V
Feedback voltage thresholds to enter Light load mode
(NCP13992AA, AC, AG, AN, AT)
(NCP13992AM)
5
FB_LL_IN
0.468
0.550
0.658
1.195
0.292
0.233
0.360
0.263
0.508
0.605
0.713
1.250
0.332
0.273
0.400
0.303
0.548
0.660
0.768
1.305
0.372
0.313
0.440
0.343
(NCP13992AE)
(NCP13992AF, AU)
(NCP13992AP)
(NCP13992AS)
(NCP13992AW)
(NCP13992AZ)
V
Feedback voltage thresholds to exit Light load mode,
(NCP13992AA, AC, AG, AN, AT, AW)
(NCP13992AE)
5
V
FB_LL_OUT
0.595
1.045
1.675
2.415
0.292
0.955
0.635
1.100
1.750
2.490
0.332
1.010
0.675
1.155
1.825
2.565
0.372
1.065
(NCP13992AF, AP, AU)
(NCP13992AM)
(NCP13992AS)
(NCP13992AZ)
st
t
On−time duration of 1 Mlower pulse when FB cross
5, 12
ms
1st_MLOWER_SKIP
V
+ V
threshold (NCP13992AA, AE)
(NCP13992AB, AD, AR)
0.95
1.08
1.7
1.89
2.15
1.62
0.81
1.05
1.20
1.9
1.15
1.32
2.1
2.31
2.65
1.98
0.99
FB_SKIP_IN
FB_SKIP_HYST
(NCP13992AC, AG, AJ, AM, AN, AT, AW)
(NCP13992AF, AP, AU, AV, AZ, CA, CB)
(NCP13992AH, AL)
2.1
2.4
(NCP13992AK)
(NCP13992AS)
1.8
0.90
st
V
Internal FB level reduction during 1 Mupper pulse when
5, 6, 14
mV
1st_MUPPER_SKIP
FB cross V
+ V
threshold (Note 2)
FB_SKIP_IN
FB_SKIP_HYST
(NCP13992AA, AC, AE, AJ, AM)
(NCP13992AB, AD)
−
−
−
−
−
−
150
100
0
200
50
300
−
−
−
−
−
−
(NCP13992AF, AP, AK, AS, AU, AV, AZ)
(NCP13992AG, AN, AT, AW)
(NCP13992AH, AL, AR)
(NCP13992CA, CB)
SKIP INPUT
I
Internal Skip pin current source
4
48
50
52
mA
SKIP
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NCP13992
ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol
SKIP INPUT
Rating
Pin
Min
Typ
Max
Unit
C
Maximum loading capacitance for skip pin voltage filtering
(Note 2)
4
−
−
10
nF
SKIP_LOAD_MAX
QUIET−SKIP PARAMETERS (EXCEPT NCP13992AB, AD, AH, AJ, AK, AL, AR, AV, CA, CB)
t
The portion of previous MU on−time that is place for last ML
pulse in pattern (NCP13992AA, AC, AE, AG, AM, AN, AT)
(NCP13992AF, AP, AS, AU, AW, AZ)
%
%
LAST_ML_PATTERN
12
12
−
−
50
−
−
100
t
The portion of previous MU on−time that is place for last ML
pulse before the LL or skip mode is activated
(NCP13992AP, AZ)
LAST_ML_SKIP
−
−
−
25
50
100
−
−
−
(NCP13992AA, AC, AE, AG, AM, AN, AT, AW)
(NCP13992AF, AS, AU)
t
Skip burst off−time duration that is needed to increase num-
ber of skipped valleys between following patterns
(NCP13992AS)
12, 14
12, 14
ms
ms
GEAR_UP
−
−
5
−
−
0.75
t
Skip burst on−time duration that is needed to decrease
number of skipped valleys between following patterns
(NCP13992AA, AC, AE, AG, AN, AT, AW)
(NCP13992AF, AM, AP, AU, AZ)
GEAR_DOWN
−
−
−
15
40
0.5
−
−
−
(NCP13992AS)
t
Time duration to force valley count logic if valley is not de-
12, 14
12, 14
12, 14
ms
ms
−
VALLEY_WD
tected
(NCP13992AA, AC, AE, AF, AP, AU, AZ)
(NCP13992AG, AN, AT, AW)
(NCP13992AM)
4.5
9.3
20.8
2.35
5
5.5
10.2
23
11.3
25.4
2.85
(NCP13992AS)
2.5
t
Quiet Timer duration
(NCP13992AA, AC)
(NCP13992AE, AS)
−
−
−
−
−
5
−
−
−
−
−
QS_timer
0.125
2.5
(NCP13992AF, AP, AU)
(NCP13992AG, AM, AN, AT, AW)
(NCP13992AZ)
0.5
0.125
N
Number of patterns adjustment when bust period is shorter
than ¼ of QS_timer duration
QS_1/4
(NCP13992AA, AC, AE, AF, AN, AS, AT, AW)
(NCP13992AF, AM, AP, AU, AZ)
−
−
2
1
−
−
N
N
N
Number of patterns adjustment when bust period is longer
12, 14
12, 14
12, 14
12, 14
−
−
−
1
0
0
−
−
−
−
−
−
−
QS_2/4
QS_3/4
QS_4/4
QS_INF
than ¼ and shorter than 2/4 of QS_timer duration
Number of patterns adjustment when bust period is longer
than 2/4 and shorter than 3/4 of QS_timer duration
Number of patterns adjustment when bust period is longer
than 3/4 and shorter than 4/4 of QS_timer duration
N
Number of patterns adjustment when bust period is longer
than QS_timer duration
(NCP13992AA, AC, AG, AN, AT, AW)
(NCP13992AE, AM)
−
−
−
−1
−3
−2
−
−
−
(NCP13992AF, AP, AS, AU, AZ)
N
Initial number of patterns placed when LL or skip mode is
activated
12, 14
14
−
1
−
−
−
PATTERN_INIT
N
Number of MU pulses during which FB_LL_IN cmp is
blanked once VFB > VFB_LL_OUT
(NCP13992AA, AC, AE)
LL_blank
−
−
−
60
100
2
−
−
−
(NCP13992AF, AG, AM, AN, AP, AT, AU, AW, AZ)
(NCP13992AS)
FB FREEZE INPUT (EXCEPT NCP13992AD, AH, AJ, AL, AV, AZ)
I
FB Freeze pin current source
4
4
18
20
22
10
mA
FB_Freeze
FB_Freeze_LOAD_MAX
C
Maximum loading capacitance for FB Freeze pin voltage
filtering (Note 2)
−
−
nF
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8
NCP13992
ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
CURRENT SENSE INPUT SECTION
t
On−time comparator delay to Mupper driver turn off
5, 6
−
−
250
ns
pd_CS
V
= 2.5 V, V goes up from –2.5 V to 2.5 V with rising
FB
CS
edge of 100 ns
I
Current sense input leakage current for V
Current sense input offset voltage
=
CS
3 V
6
6
−
−
1
mA
CS_LEAKAGE
V
mV
CS_OFFSET
(NCP13992AA, AC, AF, AG, AJ, AM, AN, AR, AT, AU, AW)
(NCP13992AB, AD, AK, AL)
(NCP13992AE, AV, AZ)
160
110
60
200
20
200
150
100
250
50
240
190
140
300
80
(NCP13992AH)
(NCP13992AP, AS, CA, CB)
t
Leading edge blanking time of the on−time comparator
5, 6, 14
3, 6
ns
LEB
output
(AA, AB, AC, AE, AG, AJ, AK, AN, AT, CA, CB)
360
120
240
440
141
300
540
170
360
(NCP13992AD, AF, AH, AL, AM, AP, AR, AS, AU, AV, AZ)
(NCP13992AW)
LFFGAIN
Line Feed Forward current source transconductance
mA/V
(V
> V
)
VBULK/PFC_FB
BO
(NCP13992AA, AC, AD, AE, AF, AG, AH, AJ, AK, AM, AL,
AN, AP, AR, AS, AT, AU, AV, AW, CA, CB)
(NCP13992AB, AZ)
−
−
0
−
−
480
FAULTS AND AUTO−RECOVERY TIMER
Maximum on−time clamp
t
(NCP13992AA, AE)
(NCP13992AB, AD, AR)
12, 14
7.3
2.5
7.7
2.7
8.4
2.9
ms
TON_MAX
(NCP13992AC, AJ, AK, AM, AP, AW)
(NCP13992AF, AG, AN, AT, AU)
(NCP13992AH)
10.4
15.2
5.68
4.1
13.61
8.5
11.1
16.3
6.1
11.9
17.8
6.57
4.74
15.73
10.5
(NCP13992AL, AS)
4.4
(NCP13992AV, AZ)
(NCP13992CA, CB)
14.6
9.5
N
Number of TON_MAX events to confirm fault
12, 14
−
−
−
1
4
8
−
−
−
−
TON_MAX_COUNTER
(NCP13992AP, AV, AZ)
(NCP13992AL)
t
FB fault timer duration
(NCP13992AA, AE, AG, AJ, AM, AN, AP, AT, AW, CA, CB)
(AB, AC, AD, AF, AH, AK, AL, AR, AS, AU, AV, AZ)
−
ms
FB_FAULT_TIMER
160
80
200
100
240
120
V
FB voltage when FB fault is detected
5
4.5
4.7
4.9
V
FB_FAULT
N
Number of CS_fault cmp. pulses to confirm CS fault
(except NCP13992AB)
−
−
CS_FAULT_COUNTER
(AA, AC, AD, AE, AG, AJ, AK, AL, AN, AP, AR, AS, AV, AW,
AZ, CA, CB)
−
−
−
−
5
3
4
1
−
−
−
−
(NCP13992AF, AT, AU)
(NCP13992AH)
(NCP13992AM)
V
CS voltage when CS fault is detected
(except NCP13992AB, AN, AT, AU, AV, AW, CA, CB)
(NCP13992AK)
6
V
s
CS_FAULT
2.5
2.8
1.85
4.0
2.7
3.05
2.0
2.9
3.3
2.15
4.7
(NCP13992AM)
(NCP13992AL, AP, AR, AS, AZ)
4.35
t
Auto−recovery duration (common timer for all fault condition)
(NCP13992AM, AS)
−
0.8
1.6
3.2
1.0
2.0
4.0
1.2
2.4
4.8
A−REC_TIMER
(NCP13992CA, CB)
BROWN−OUT PROTECTION
V
Brown−out turn−off threshold
3
3
3
3
0.965
4.1
5
1.000
5.0
12
1.035
5.7
V
BO
BO
I
Brown−out hysteresis current, V
< V
mA
mV
mA
VBULK/PFC_FB
BO
V
Brown−Out comparator hysteresis
Brown−Out input bias current
25
BO_HYST
BO_BIAS
I
−
−
0.05
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9
NCP13992
ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, Vcc = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
ms
BROWN−OUT PROTECTION
t
BO filter duration
RAMP COMPENSATION
RC Ramp compensation gain
3
10
20
30
BO_FILTR
−
mV/ms
GAIN
(AA, AB, AC, AD, AE, AG, AJ, AN, AT, AW, CA, CB)
(NCP13992AF, AU)
58
87
67
95
127
27.7
82
159
116
180
227
49
108
215
167
237
348
73.9
(NCP13992AH, AM, AL)
(NCP13992AK, AP, AR, AV)
(NCP13992AS)
(NCP13992AZ)
t
Ramp compensation time shift
TEMPERATURE SHUTDOWN PROTECTION
Temperature shutdown T going up
−
−
−
0.4
−
ms
°C
RC_SHIFT
T
TSD
J
(NCP13992AA, AB, AD, AE, AS, CA, CB)
−
−
−
124
137
150
−
−
−
(AC, AF, AG, AH, AJ, AK, AL, AN, AP, AR, AT, AU, AV, AZ)
(NCP13992AM, AW)
T
Temperature shutdown hysteresis
−
−
30
−
°C
TSD_HYST
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design.
3. Minimal resistance connected in series with bootstrap diode is 3.3 W
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10
NCP13992
IC OPTIONS
Option
Cumulative
FB fault timer/
counter
OVP/OTP
bias during
skip
FB fault
source
FB fault
CS_FAULT
TON_MAX
OVP
OTP
NCP13992AA Auto−recovery Timer
NCP13992AB Auto−recovery Timer
NCP13992AC Auto−recovery Timer
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
Auto−recovery Auto−recovery
Latch
Auto−recovery
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
Auto−recovery
Latch
OFF
OFF
OFF
Auto−recovery Auto−recovery
Latch
Latch
Latch
Latch
Latch
NCP13992AD
Latch
Timer
NCP13992AE Auto−recovery Timer
NCP13992AF Auto−recovery Timer
NCP13992AG Auto−recovery Timer
NCP13992AH Auto−recovery Timer
NCP13992AJ Auto−recovery Timer
Auto−recovery Auto−recovery
Auto−recovery
Auto−recovery Auto−recovery Auto−recovery Auto−recovery
Auto−recovery
Auto−recovery
Auto−recovery
Latch
OFF
OFF
OFF
OFF
OFF
Latch
Latch
Latch
Latch
Auto−recovery Auto−recovery
Latch Latch
Auto−recovery Auto−recovery
NCP13992AK
Latch
Timer
NCP13992AM Auto−recovery Timer
NCP13992AL Auto−recovery Timer
NCP13992AN Auto−recovery Timer
Auto−recovery
Auto−recovery Auto−recovery
Latch
Latch
Latch
Latch
OFF
OFF
OFF
OFF
ON
Auto−recovery
Latch
OFF
NCP13992AP
Latch
Timer
Auto−recovery Auto−recovery Auto−recovery
NCP13992AR Auto−recovery Timer
NCP13992AS Auto−recovery Timer
NCP13992AT Auto−recovery Timer
NCP13992AU Auto−recovery Timer
Auto−recovery
Latch
OFF
OFF
OFF
Auto−recovery Auto−recovery
Latch
Latch
Latch
Auto−recovery
Auto−recovery
OFF
OFF
OFF
OFF
OFF
ON
Auto−recovery Auto−recovery Auto−recovery Auto−recovery
NCP13992AV
Latch
Timer
Latch
Auto−recovery Auto−recovery Auto−recovery
OFF Auto−recovery Auto−recovery
NCP13992AW Auto−recovery Timer
NCP13992AZ Auto−recovery Timer
NCP13992CA Auto−recovery Timer
NCP13992CB Auto−recovery Timer
Auto−recovery
Auto−recovery Auto−recovery Auto−recovery Auto−recovery
Auto−recovery
Auto−recovery
OFF
OFF
Latch
Latch
Auto−recovery
Auto−recovery
ON
PFC_MODE
Dead Time
Control
BO
Ramp Comp
Status
Dedicated
Soft_start_seq
Skip Status
OFF
OFF
ON
Status
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Option
Skip Mode
Dead Time Fault
OFF
NCP13992AA
NCP13992AB
NCP13992AC
NCP13992AD
NCP13992AE
NCP13992AF
NCP13992AG
NCP13992AH
NCP13992AJ
NCP13992AK
NCP13992AL
NCP13992AM
NCP13992AN
NCP13992AP
NCP13992AR
Quiet Skip
ZVS or DT_max
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Standard Skip ZVS or DT_max
Quiet Skip ZVS or DT_max
Standard Skip ZVS or DT_max
OFF
Auto−recovery
OFF
OFF
OFF
ON
Quiet Skip
Quiet Skip
Quiet Skip
ZVS or DT_max
ZVS or DT_max
ZVS or DT_max
OFF
OFF
ON
OFF
OFF
ON
Standard Skip ZVS or DT_max
Standard Skip ZVS or DT_max
Standard Skip ZVS or DT_max
Standard Skip ZVS or DT_max
OFF
OFF
OFF
OFF
ON
OFF
OFF
Quiet Skip
Quiet Skip
Quiet Skip
ZVS or DT_max
ZVS or DT_max
ZVS or DT_max
OFF
OFF
ON
OFF
OFF
OFF
Standard Skip ZVS or DT_max
OFF
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11
NCP13992
PFC_MODE
Skip Status
Dead Time
Control
BO
Status
Ramp Comp
Status
Dedicated
Soft_start_seq
Option
Skip Mode
Quiet Skip
Quiet Skip
Quiet Skip
Dead Time Fault
NCP13992AS
NCP13992AT
NCP13992AU
NCP13992AV
NCP13992AW
NCP13992AZ
NCP13992CA
NCP13992CB
OFF
ON
ZVS or DT_max
ZVS or DT_max
ZVS or DT_max
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
Without ramp shift
OFF
ON
ON
ON
OFF
ON
ON
ON
OFF
OFF
ON
Standard Skip ZVS or DT_max
Quiet Skip
Quiet Skip
DT_max only
ON
ZVS or DT_max
ON
Standard Skip ZVS or DT_max
Standard Skip ZVS or DT_max
ON
ORDERING INFORMATION
Device
†
Package Marking
NCP13992AA
NCP13992AB
NCP13992AC
NCP13992AD
NCP13992AE
NCP13992AF
NCP13992AG
NCP13992AH
NCP13992AJ
NCP13992AK
NCP13992AL
NCP13992AM
NCP13992AN
NCP13992AP
NCP13992AR
NCP13992AS
NCP13992AT
NCP13992AU
NCP13992AV
NCP13992AW
NCP13992AZ
NCP13992CA
NCP13992CB
Package
Shipping
NCP13992AADR2G
NCP13992ABDR2G
NCP13992ACDR2G
NCP13992ADDR2G
NCP13992AEDR2G
NCP13992AFDR2G
NCP13992AGDR2G
NCP13992AHDR2G
NCP13992AJDR2G
NCP13992AKDR2G
NCP13992ALDR2G
NCP13992AMDR2G
NCP13992ANDR2G*
NCP13992APDR2G*
NCP13992ARDR2G
NCP13992ASDR2G
NCP13992ATDR2G
NCP13992AUDR2G
NCP13992AVDR2G*
NCP13992AWDR2G
NCP13992AZDR2G
NCP13992CADR2G
NCP13992CBDR2G
SOIC−16, Less Pin 2 and 13 (Pb−free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*In Development. Available upon request.
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12
NCP13992
VCC Management with High−voltage Startup Current
Source
The NCP13992 controller features a HV startup current
source that allows fast startup time and extremely low
standby power consumption. Two startup current levels
over−temperature protection to prevent IC damage for any
failure mode that may occur in the application. The HV
startup current source is primarily enabled or disabled based
on V level. The startup HV current source can be also
CC
enabled by BO_OK rising edge, auto−recovery timer end
and TSD end event. The HV startup current source charges
the VCC capacitor before IC start−up.
(I
and I
) are provided by the system for safety in
start1
start2
case of short circuit between VCC and GND pins. In
addition, the HV startup current source features a dedicated
Figure 4. Internal Connection of the VCC Management Block
The NCP13992 controller disables the HV startup current
when the die temperature reaches 130°C. At this
temperature, I will be progressively to prevent the die
source once the VCC pin voltage level reaches V
CC_ON
start2
threshold – refer to Figure 4. The application then starts
operation and the auxiliary winding maintains the voltage
bias for the controller during normal and skip−mode
operating modes. The IC operates in so called Dynamic Self
Supply (DSS) mode when the bias from auxiliary winding
temperature from rising above 130°C.
Brown−out Protection − VBULK/PFC FB Input
Resonant tank of an LLC converter is always designed to
operate within a specific bulk voltage range. Operation
below minimum bulk voltage level would result in current
and temperature overstress of the converter power stage.
The NCP13992 controller features a VBULK/PFC FB input
in order to precisely adjust the bulk voltage turn−ON and
turn−OFF levels. This Brown−Out protection (BO) greatly
simplifies application level design.
is not sufficient to keep the V voltage above V
CC
CC_OFF
threshold (i.e. V voltage is cycling between V
and
CC
CC_ON
V
thresholds with no driver pulses on the output
CC_OFF
during positive V ramp). Please refer to Figure 23 through
CC
Figure 25 to find an illustration of the NCP13992 VCC
management system under all operating conditions/modes.
The HV startup current source features an independent
over–temperature protection system to limit I
current
start2
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13
NCP13992
Figure 5. Internal Connection of the Brown−out Protection Block
The internal circuitry shown in Figure 5 allows
V
bulk_OFF * VBO
R
upper + Rlower
@
(eq. 4)
monitoring the high−voltage input rail (V ).
A
bulk
VBO
high−impedance resistive divider made of R
and R
upper
lower
Note that the VBULK/PFC FB pin is pulled down by an
internal switch when the controller is in startup phase − i.e.
when the V voltage ramps up from V < V
resistors brings a portion of the V
rail to the
bulk
VBULK/PFC FB pin. The Current sink (I ) is active below
BO
CC
CC
CC_RESET
the bulk voltage turn−on level (V
). Therefore, the
bulk_ON
towards the V
level on the VCC pin. This feature
CC_ON
bulk voltage turn−on level is higher than defined by the
division ratio of the resistive divider. To the contrary, when
the internal BO_OK signal is high, i.e. the application is
assures that the VBULK/PFC FB pin voltage will not ramp
up before the IC operation starts. The I hysteresis current
sink is activated and BO discharge switch is disabled once
BO
running, the I sink is disabled. The bulk voltage turn−off
BO
the
V
CC
voltage crosses
V
CC_ON
threshold. The
threshold (V ) is then given by BO comparator
bulk_OFF
VBULK/PFC FB pin voltage then ramps up naturally
according to the BO divider information. The BO
comparator then authorizes or disables the LLC stage
operation based on the actual V
The low I hysteresis current of the NCP13992 brown
reference voltage directly on the resistor divider. The
advantage of this solution is that the V threshold
bulk_OFF
precision is not affected by I
tolerance.
hysteresis current sink
BO
level.
bulk
BO
The V
and V
levels can be calculated
bulk_ON
bulk_OFF
out protection system allows increasing the bulk voltage
divider resistance and thus reduces the application power
consumption during light load operation. On the other hand,
the high impedance divider can be noise sensitive due to
capacitive coupling to HV switching traces in the
using equations below:
The I is ON:
BO
(eq. 1)
V
BO ) VBOhyst
+
Rlower
Rlower ) Rupper
Rlower @ Rupper
Rlower ) Rupper
@ ǒ
Ǔ
Vbulk_ON
@
* IBO
application. This is why a filter (t
) is added after the
BO_FILTR
BO comparator in order to increase the system noise
immunity. Despite the internal filtering, it is also
recommended to keep a good layout for BO divider resistors
and use a small external filtering capacitor on the
VBULK/PFC pin if precise BO detection wants to be
achieved.
The bulk voltage HV divider can be also used by a PFC
front stage controller as a feedback sensing network (refer
again to Figure 5). The shared bulk voltage resistor divider
between PFC and LLC stage offers a way how to further
reduce power losses during no−load operation. The
NCP13992 features a PFC MODE pin that disconnects bias
The I is OFF:
BO
Rlower
Rlower ) Rupper
V
BO + Vbulk_OFF
@
(eq. 2)
One can extract R
term from equation 2 and use it in
lower
equation 1 to get needed R
value:
upper
V
bulk_ON@V
BO * VBO * VBOhyst
Vbulk_OFF
Rlower
+
(eq. 3)
VBO
IBO
@
ǒ
1 *
Ǔ
Vbulk_OFF
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14
NCP13992
of the PFC stage during light load or fault mode operation.
The controller is allowed to run when OVP/OTP input
voltage is within this working window. The controller stops
the operation, after filter time delay, when the OVP/OTP
input voltage is out of the no−fault window. The controller
then either latches−off or or starts an auto−recovery timer −
depending on the IC version − and triggered the protection
This technique further reduces the no−load power
consumption down again since the power losses of voltage
divider are not affected by the bulk voltage at all.
Please refer to Figure 23 through Figure 25 for an
illustration of NCP13992 Brown−out protection system in
all operating conditions/modes.
threshold (V
or V ).
OVP
OTP
The VBULK/PFC FB pin voltage is also used by Line
Feed Forward block (LFF). Please refer to ON−time
modulation and feedback loop block description for more
information about LFF function.
The internal current source I
implementation by using a single negative temperature
coefficient (NTC) thermistor. An active soft clamp
allows a simple OTP
OTP
composed from V
and R
components prevents the
clamp
clamp
OVP/OTP pin voltage from reaching the V
threshold
OVP
Over−voltage and Over−temperature Protection
when the pin is pulled up by the I
current. An external
OTP
The OVP/OTP pin is a dedicated input to allow for a
simple and cost effective implementation of two key
protection features that are needed in adapter applications:
over−voltage (OVP) and over−temperature (OTP)
protections. Both of these protections can be either latched
or auto−recovery– depending on the version of NCP13992.
The OVP/OTP pin has two voltage threshold levels of
pull*up current, higher than the pull*down capability of
the internal clamp (V ), has to be applied to
CLAMP_OVP/OTP
pull the OVP/OTP pin above V
threshold to activate the
OVP
OVP protection. The t
and t
filters
OVP_FILTER
OTP_FILTER
are implemented in the system to avoid any false triggering
of the protections due to application noise and/or poor
layout.
detection (V
and V ) that define a no−fault window.
OTP
OVP
Figure 6. Internal Connection of OVP/OTP Input
The OTP protection could be falsely triggered during
controller startup due to the external filtering capacitor
• V falls below V
threshold
CC
CC_OFF
• BO OK signal goes to low state (i.e. Brown−out
charging current. Thus the t
period has been
BLANK_OTP
condition occurs on the mains)
• Fault signal is activated (Auto−recovery timer starts
counting or Latch fault is present)
implemented in the system to overcome such behavior. The
OTP comparator output is ignored during t
BLANK_OTP
period. In order to speed up the charging of the external
filtering capacitor C connected to OVP/OTP pin,
• IC goes into the skip−mode operation (V
FB_SKIP_IN
OVP_OTP
threshold was reached)
the I
current has been doubled to I . The
OTP_BOOST
OTP
maximum value of filtering capacitor is 100 nF.
The OVP/OTP ON signal is set after the following events:
• the V voltage exceeds the V threshold during
IC option that keeps OVP/OTP block working during skip
mode is also available. The IC consumption is increased for
this version by OVP/OTP block bias.
CC
CC_ON
The latched OVP or OTP versions of NCP13992 enters
first start−up phase (after VCC pin voltage was below
threshold)
latched protection mode when V voltage cycles between
CC
V
CC_RESET
V
CC_ON
and V
thresholds and no pulses are provided
CC_OFF
• BO OK signal is received from BO block
by drivers. The controller VCC pin voltage has to be cycled
down below V threshold in order to restart
• Auto−recovery timer elapsed and a new restart occurs
CC_RESET
• IC returns to operation from skip−mode (V
+
operation. This would happen when the power supply is
unplugged from the mains.
FB_SKIP_IN
V
threshold was reached)
FB_SKIP_HYST
The I
current source is disabled when:
OTP
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15
NCP13992
st
PFC MODE Output
1 to control the external small signal HV MOSFET switch
that connects the bulk voltage divider to the VBULK/PFC
FB input
The NCP13992 has PFC MODE pin that can be used to
disable or enable PFC stage operation based on actual
application operating state – please refer to Figure 7. The
PFC MODE output pin can be used for two purposes:
nd
2
to control the PFC front stage controller operation via
PFC controller supply pin
Figure 7. Internal Connection of the PFC MODE Block
ON−time Modulation and Feedback Loop Block
There are two possible states of the PFC MODE output
that can be placed by the controller based on the application
operating conditions:
Frequency modulation of today’s commercially available
resonant mode controllers is based on the output voltage
regulator feedback only. The feedback voltage (or current)
of output regulator drives voltage (or current) controlled
oscillator (VCO or CCO) in the controller. This method
presents three main disadvantages:
a) The PFC MODE output pin is pulled−down by an internal
MOSFET switch before controller startup. This technique
ensures minimum VCC pin current consumption in order to
ramp V voltage in a short time from the HV startup
CC
st
nd
1
− The 2 order pole is present in small signal gain−phase
current source. This approach speeds up the startup and
restart time of an SMPS. The PFC MODE output pin is also
pulled−down in protection mode during which the HV
startup current source is operated in DSS mode. Application
power consumption is reduced in both above cases.
characteristics => the lower cross over frequency and worse
transient response is imposed by the system when voltage
mode control is used. There is no direct link to the actual
primary current – i.e. no line feed forward mechanism which
results in poor line transient response.
b) The pull−down switch is disabled and controller connects
VCC pin voltage to PFC MODE output with minimum
nd
2
– Precise VCO (or CCO) is needed to assure frequency
clamps
modulation with good reproducibility, f and f
dropout (V
).
min
max
PFC_M_ON
need to be adjusted for each design => need for an
adjustment pin(s).
The PFC MODE pin output current is limited when the
VCC to PFC MODE bypass switch is activated. The current
limitation avoids bypass switch damage during PFC VCC
decoupling capacitor charging process or short circuit. A
minimum value PFC VCC decoupling capacitance should
be used in order to speed up PFC stage startup after it is
enabled by the NCP13992 controller.
rd
3
– Dedicated overload protection system, requiring an
additional pin, is needed to assure application safety during
overload and/or secondary short circuit events.
The NCP13992 resolves all disadvantages mentioned
above by implementing a current mode control scheme that
ensures best transient response performance and provides
inherent cycle−by−cycle over−current protection feature in
the same time. The current mode control principle used in
this device can be seen in Figure 8.
Please refer to Figure 23 through Figure 25 for an
illustration of NCP13992 PFC operation control.
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NCP13992
Figure 8. Internal Connection of the NCP13992 Current Mode Control Scheme
The basic principle of current mode control scheme
detection – please refer to chapter dedicated to short circuit
implementation lies in the use of an ON−time comparator
that defines upper switch on−time by comparing voltage
ramp, derived from the current sense input voltage, to the
divided feedback pin voltage. The upper switch on−time is
then re−used for low side switch conduction period. The
switching frequency is thus defined by the actual primary
current and output load conditions. Digital processing with
10 ns minimum on−time resolution is implemented to
ensure high noise immunity. The ON−time comparator
protection.
The second input signal for the on−time comparator is
derived from the FB pin voltage. This internal FB pin signal
is also used for the following purposes: skip mode operation
detection, PFC MODE control and overload / open FB pin
fault detection. The detailed description of these functions
can be found in each dedicated chapters. The internal
pull−up resistor assures that the FB pin voltage increases
when the optocoupler LED becomes less biased – i.e. when
output load is increased. The higher FB pin voltage implies
a higher reference level for on−time comparator i.e. longer
Mupper switch on−time and thus also higher output power.
The FB pin features a precise voltage clamp which limits the
internal FB signal during overload and startup. The FB pin
signal passes through the FB processing block before it is
brought to the ON−time comparator input. The FB
output is blanked by the leading edge blanking (t
) after
LEB
the Mupper switch is turned−on. The ON−time comparator
LEB period helps to avoid false triggering of the on−time
modulation due to noise generated by the HB pin voltage
transition.
The voltage signal for current sense input is prepared
externally via natural primary current integration by the
resonant tank capacitor Cs. The resonant capacitor voltage
is divided down by capacitive divider (Ccs1, Ccs2, Rcs1,
Rcs2) before it is provided to the CS input. The capacitive
divider division ratio, which is fully externally adjustable,
defines the maximum primary current level that is reached
in case of maximum feedback voltage – i.e. the capacitive
divider division ration defines the maximum output power
of the converter for given bulk voltage. The CS is a bipolar
input pin which an input voltage swing is restricted to 5 V.
A fixed voltage offset is internally added to the CS pin signal
in order to assure enough voltage margin for operation the
feedback optocoupler − the FB optocoupler saturation
voltage is ~ 0.15 V (depending on type). However, the CS
pin useful signal for frequency modulation swings from 0 V,
so current mode regulation would not work under light load
conditions if no offset would be added to the CS pin before
it is stabilized to the level of the on−time comparator input.
The CS pin signal is also used for secondary side short circuit
processing block scales the FB signal down by a K ratio
FB
in order to limit the CS input dynamic voltage range. The
scaled FB signal is then further processed by subtraction of
a ramp compensation generator signal in order to ensure
stability of the current mode control scheme. The divided
internal FB signal is overridden by a Soft−start generator
output voltage during device starts−up.
The actual operating frequency of the converter is defined
based on the CS pin and FB pin input signals. The maximum
output power of the converter, under given input voltage, is
limited by maximum internal FB voltage clamp that is
reached when optocoupler provides no current. The
maximum output power limit is bulk voltage dependent due
to changing ratio between magnetizing and load primary
current components. Line Feed Forward (LFF) system is
implemented in the controller to compensate for maximum
output power clamp variation. The I
out from the Cs pin is BO/PFC FB pin voltage proportional
current that flows
LFF
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17
NCP13992
and creates voltage offset on the resistor connected to the Cs
only when BO pin voltage exceeds BO_OK threshold
voltage.
Please refer to Figure 9 and below description for better
understanding of the NCP13992 frequency modulation
system.
pin. The higher input voltage, the higher drop is created on
external resistor. The Mupper switch on−time is thus
reduced for given maximum internal FB voltage clamp
when input voltage increases. The I
current is provided
LFF
Figure 9. NCP13992 On−time Modulation Principle
Overload and Open FB Protections
The Mupper switch is activated by the controller after
dead−time (DT) period lapses in point A. The frequency
processing block increments the ON−time counter with
10 ns resolution until the internal CS signal crosses the
internal FB set point for the ON−time comparator in point B.
A DT period is then introduced by the controller to avoid any
shoot−through current through the power stage switches.
The DT period ends in point C and the controller activates
the Mlower switch. The ON−time processing block
decrements the ON_time counter down until it reaches zero.
The Mlower switch is then turned−OFF at point D and the
DT period is started. This approach results in perfect duty
cycle symmetry for Mlower and Mupper switches. The
Mupper switch on−time naturally increases and the
operating frequency drops when the FB pin voltage is
increased, i.e. when higher current is delivered by the
converter output – sequence E.
The resonant capacitor voltage and thus also CS pin
voltage can be out of balance in some cases – this is the case
during transition from full load to no−load operation when
skip mode is not used or adjusted correctly. The current
mode operation is not possible in such case because the
ON−time comparator output stays active for several
switching cycles. Thus a special logic has been implemented
in NCP13992 in order to repeat the last valid on−time until
the current mode operation recovers – i.e. until the CS pin
signal balance is restored by the system.
The overload protection and open FB pin detection are
implemented via FB pin voltage monitoring in this
controller. The FB fault comparator is triggered once the FB
pin voltage reaches its maximum level and the V
FB_FAULT
threshold is exceeded. The fault timer or counter (depending
on IC option) is then enabled – refer to Figure 10. The time
period to the FB fault event confirmation is defined by the
preselected t
parameter when the fault
FB_FAULT_TIMER
timer option is used. The FB fault counter, once selected as
a FB fault confirmation period source, defines the fault
confirmation period via Mupper DRV pulses counting. The
FB fault confirmation time is thus dependent on switching
frequency. The fault timer/counter is reset once the FB fault
condition diminishes. A digital noise filter has been added
after the FB fault comparator to overcome false triggering of
the FB fault timer/counter due to possible noise on the FB
input. The noise filter has a period of 2 ms for FB fault
timer/counter activation and 20 µs for reset/deactivation to
assure high noise immunity. A cumulative timer/counter IC
option is also available on request. The FB fault
timer/counter is not reset when the FB fault condition
diminishes in this case. The FB fault timer/counter is
disabled and memorizes the fault period information. The
cumulative FB fault timer/counter integrates all the FB fault
events over the IC operation time. The Fault timer/counter
can be reset via skip mode or VCC UVLO event.
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NCP13992
Figure 10. Internal FB Fault Management
The controller disables driver pulses and enters protection
primary current is naturally limited by the NCP13992
on−time modulation principle in this case. But the primary
current increases when the output terminals are shorted. The
NCP13992 controller will maintain zero voltage switching
operation in such case, however high currents will flow
through the power MOSFETS, transformer winding and
secondary side rectification. The NCP13992 implements a
dedicated secondary side short circuit protection system that
will shut down the controller much faster than the regular FB
fault event in order to limit the stress of the power stage
components. The CS pin signal is monitored by the
dedicated CS fault comparator − refer to Figure 8. The CS
fault counter is incremented each time the CS fault
comparator is triggered. The controller enters
auto−recovery or latched protection mode (depending on IC
option) in case the CS fault counter overflows refer to
Figure 11. The CS fault counter is then reset once the CS
fault comparator is inactive for at least 50 Mupper upcoming
pulses. This digital filtering improves CS fault protection
system noise immunity.
mode once the FB fault event is confirmed by the FB fault
timer or counter. Latched or auto−recovery operation is then
triggered – depends on selected IC option. The controller
adds an auto−recovery off−time period (t ) and
A−REC_TIMER
restarts the operation via soft start in case of auto−recovery
option. The application temperature runaway is thus
avoided in case of overload while the automatic restart is still
possible once the overload condition disappears. The IC
with latched FB fault option stays latched−off, supplied by
the HV startup current source working in DSS mode, until
the V
threshold is reached on the VCC pin – i.e.
CC_RESET
until user re−connects power supply mains.
Please refer to Figure 23 and Figure 24 for an illustration
of the NCP13992 FB fault detection block.
Secondary Short Circuit Detection
The protection system described previously, implemented
via FB pin voltage level detection, prevents continuous
overload operation and/or open FB pin conditions. The
Figure 11. NCP13992 CS Fault Principle
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NCP13992
Dedicated Startup Sequence and Soft−Start
Hard switching conditions can occur in a resonant SMPS
application when the resonant tank operation is started with
50% duty cycle symmetry – refer to Figure 12. This hard
switching appears because the resonant tank initial
conditions are not optimal for the clean startup.
Figure 12. Hard Switching Cycle Appears in the LLC Application
when Resonant Tank is Excited by 50% Duty Cycle during Startup
The initial resonant capacitor voltage level can differ
These facts show that a clean, hard switching free and
parasitic oscillation free, startup of an LLC converter is not
an easy task, and cannot be achieved by duty cycle
imbalance and/or simple resonant capacitor pre−charge to
Vbulk/2 level. These methods only work in specific startup
conditions.
This explains why the NCP13992 implements a
proprietary startup sequence − see Figure 13 and Figure 14.
The resonant capacitor is discharged down to 0 V before any
application restart − except when restarting from skip mode.
depending on how long delay was placed before application
operation restart. The resonant capacitor voltage is close to
zero level when application restarts after very long delay –
for example several seconds, when the resonant capacitor is
discharged by leakage to the power stage. However, the
resonant capacitor voltage value can be anywhere between
Vbulk and 0 V when the application restarts operation after
a short period of time – like during periodical SMPS
turn−on/off. Another factor that plays significant role during
resonant power supply startup is the actual load impedance
seen by the power stage during the first pulses of startup
sequence. This impedance is not only defined by resonant
tank components but also by the output loading conditions
and actual output voltage level. The load impedance of
resonant tank is low when the output is loaded and/or the
output voltage is low enough to made secondary rectifies
conducting during first switching cycles of startup phase.
The resonant frequency of the resonant tank is given by the
resonant capacitor capacitance and resonant inductance
−note that the magnetizing inductance does not participate
in resonance in this case. However, if the application
starts−up when the output capacitors is charged and there is
no load connected to the output, the secondary rectification
diodes is not conducting during each switching cycle of
startup sequence and thus the resonant frequency of resonant
tank is affected also by the magnetizing inductance. In this
case, the resonant frequency is much lower than in case of
startup into loaded/discharged output.
Figure 13. Initial Resonant Capacitor Discharge
before Dedicated Startup Sequence is Placed
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NCP13992
Figure 14. Dedicated Startup Sequence Detail
The resonant capacitor discharging process is simply
The startup period then depends on the previous condition.
Another blank Mlower switch period is placed by the
controller in case condition a) occurred. A normal Mlower
driver pulse, with DC of 50% to previous Mupper DRV
pulse, is placed in case condition b) is fulfilled.
implemented by activating an internal current limited switch
connected between the HB pin and IC ground – refer to
Figure 13. This technique assures that the resonant capacitor
energy is dissipated in the controller without ringing or
oscillations that could swing the resonant capacitor voltage
to a positive or negative level. The controller detects that the
discharge process is complete via HB pin voltage level
monitoring. The discharge switch is disabled once the HB
The dedicated startup sequence is placed after the
resonant capacitor is discharged (refer to Figure 13 and
Figure 14) in order to exclude any hard switching cycles
during the startup sequence. The first Mupper switch cycle
in startup phase is always non−ZVS cycle because there is
no energy in the resonant tank to prepare ZVS condition.
However, there is no energy in the resonant tank at this time,
there is also no possibility that the power stage MOSFET
body diodes conducts any current. Thus the hard
commutation of the body diode cannot occur in this case.
The IC will not start and provide regular driver output
pulses until it is placed into the target application, because
the startup sequence cannot be finished until HB pin signal
is detected by the system. The IC features a startup watchdog
pin voltage drops below the V
threshold.
HB_MIN
The dedicated startup sequence continues by activation of
the Mlower driver output for Tl1 period (refer to Figure 14).
This technique ensures that the bootstrap capacitor is fully
charged before the first high−side driver pulse is introduced
by the controller. The first Mupper switch on−time Tup1
period is fixed and depends on the application parameters.
This period can be adjusted internally – various IC options
are available. The Mupper switch is released after T
up1
period and it is not followed by the Mlower switch
activation. The controller waits for a new ZVS condition for
Mupper switch instead and measures actual resonant tank
conditions this way. The Mupper switch is then activated
again after the Mlower blank period is used for measurement
purposes. The second Mupper driver conduction period is
then dependent on the previously measured conditions:
1. The Mupper switch is activated for 3/2 of previous
Mupper conduction period in case the measured
timer (t ) which activates a dedicated startup
WATCHDOG
sequence periodically in case the IC is powered without
application (during bench testing) or in case the startup
sequence is not finished correctly. The IC will provide the
first Mlower and first Mupper DRV pulses with a
t
off−time in−between startup attempts.
WATCHDOG
Soft−start
The dedicated startup sequence is complete when
condition b) from previous chapter is fulfilled and the
controller continues operation with the soft−start sequence.
A fully digital non−linear soft−start sequence has been
implemented in NCP13992 using a soft−start counter and
D/A converter that are gradually incremented by the Mlower
driver pulses. A block diagram of the NCP13992 soft−start
system is shown in Figure 15.
time between previous Mupper turn−off event and
upper ZVS condition detection is twice higher than
the the previous Mupper pulse conduction period
2. The Mupper switch is activated for previous
Mupper conduction period in case the measured
time between previous Mupper turn−off event and
upper ZVS condition detection is twice lower than
the previous Mupper pulse conduction period
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NCP13992
Figure 15. Soft−start Block Internal Implementation
The soft−start block subsystems and operation are
described below:
4. The Maximum ON−time comparator compares the
actual ON−time counter value with the maximum on−time
value (t
) and activates the latch (or auto−recovery)
TON_MAX
1. The Soft−Start counter is a unidirectional counter that is
loaded with the last Mupper on−time value that is reached at
the dedicated startup sequence end (i.e. during condition b
occurrence explained in previous chapter). The on−time
period used in the initial period of the soft−start sequence is
affected by the first Mupper on−time period selection and
the dedicated startup sequence processing. The Soft−Start
counter counts up from this initial on time period to its
maximum value which corresponds to the IC maximum
on−time. The Soft−Start counter is incremented by the
protection mode once IC detect requested number of
TON_MAX events. The minimum operating frequency of
the controller is defined the same way. The Maximum
ON−time comparator reference is loaded by the Soft−Start
counter value on each switching cycle during soft−start. The
Maximum ON−time fault signal is ignored during
Soft−Start operation. The converter Mupper switch on−time
(and thus operating frequency) is thus defined by the
Soft−Start counter value indirectly – via Maximum
ON−time comparator. The Mupper switch on−time is
soft−start increment number (t ) during each
SS_INCREMENT
increased until the Soft−Start counter reaches t
TON_MAX
Mlower switch on−time period. The soft−start start
increment, selectable via IC option, thus affects the
soft−start time duration. The Mlower clock signal for the
Soft−Start counter can be divided down by the SS clock
period and Maximum on−time protection is activated, or
until ON−time comparator takes action and overrides the
Maximum ON−time comparator.
divider (K
) in case the soft−start period needs
5. The Soft−Start D/A converter generates a soft−start
voltage ramp for ON−time comparator input synchronously
with Soft−Start counter incrementing. The internal FB
signal for ON−time comparator input is artificially
pulled−down and then ramped−up gradually when soft−start
period is placed by the system – refer to Figure 16. The FB
loop is supposed to take over at certain point when
regulation loop is closed and output gets regulated so that
soft−start has no other effect on the on−time modulation.
The Soft−Start counter continues counting−up until it
reaches its maximum value which corresponds to the IC
maximum on−time value – i.e. the IC minimum operating
frequency. The Soft−Start period is terminated (i.e. counter
is loaded to its maximum) when the FB pin voltage drops
SS_INCREMENT
to be prolonged further – this can be also done via IC option
selection. The Soft−Start period is terminated (i.e. the
counter is loaded to its maximum) when the FB pin voltage
drops below V
level.
FB_SKIP_IN
2. The ON−time counter is a bidirectional counter that is
used as a main system counter for on−time modulation
during soft−start, normal operation or overload conditions.
The ON−time counter counts−up during Mupper switch
conduction period and then counts down to zero – defining
Mlower switch conduction period. This technique assures
perfect 50% duty cycle symmetry for both power switches
as afore mentioned. The ON−time counter count−up mode
can be switched to the count−down mode by either of two
st
below V
level. The D/A converter output evolve
FB_SKIP_IN
events: 1 when the ON−time counter value reaches the
nd
accordingly to the Soft−Start counter as it is loaded from its
output data bus.
maximum on−time value (t
Mupper on−time is terminated based on the current sense
) or 2 when the actual
TON_MAX
input information.
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NCP13992
Figure 16. Soft Start Behavior
The Controller Operation during Soft−start Sequence
Evolves as Follows:
and saturates at its maximum possible value which
corresponds to IC minimum operating frequency. The
maximum on−time fault detection system is enabled when
The Soft−Start counter is loaded by last Mupper on−time
value at the end of the dedicated startup sequence. The
ON−time counter is released and starts count−up from zero
until the value that is equal to the actual Soft−Start counter
state. The Mupper switch is active during the time when
ON−time counter counts−up. The Maximum ON−time
comparator then changes counting mode of the ON−time
comparator from count−up to count−down. A dead−time is
placed and the Mlower switch is activated till the ON−time
counter reaches zero value. The Soft−Start counter is
incremented by selected increment during corresponding
Mlower on−time period so that the following Mupper switch
on−time is prolonged automatically – the frequency thus
drops naturally. Because the operating frequency of the
controller drops and Mlower DRV signal is used as a clock
source for the Soft−start counter, the soft−start speed starts
to decrease on each (or on each N−th) Mlower driver pulse
Soft−Start counter value is equal to t
value.
TON_MAX
The previous on−time repetition feature, described above
in the ON−time modulation and feedback loop chapter, is
disabled in the beginning of soft start period. This is because
the ON−time comparator output stays high for several cycles
of soft start period – until the current mode regulation takes
over. The previous on−time repetition feature is enabled
once the current modulation starts to work fully, i.e. in the
time when the ON−time comparator output periodically
drops to low state within actual Mupper switch on−time
period. Typical startup waveform of the LLC application
driven by NCP13992 controller can be seen in Figure 17.
(where N is defined by K ) of switching cycle.
SS_INCREMENT
So we have non−linear soft−start that helps to speed up
output charging in the beginning of the soft−start operation
and reduces the output voltage slope when the output is close
to the regulation level. The output bus of the Soft−Start
counter addresses the D/A converter that defines the
ON−time comparator reference voltage. This reference
voltage thus also increases non−linearly from initial zero
level until the level at which the current mode regulation
starts to work. The on−time of the Mupper and Mlower
switch is then defined by the ON−time comparator action
instead of the Maximum ON−time comparator. The
soft−start then continues until the regulation loop is closed
and the on−time is fully controlled by the secondary
regulator. The Soft−Start counter then continues in counting
Figure 17. Application Startup with NCP13992 −
Primary Current − Green, Vout − Magenta
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NCP13992
Skip Mode Operation
preselected level. Zero voltage switching technique is still
present for the power switches to achieve high light load
efficiency. Quiet skip mode operation is initiated when load
drops further and FB voltage drops below another FB
threshold that is user adjustable on the skip pin. The
frequency of skip burst is regulated by internal digital
controller around preselected quiet skip frequency clamp in
order to reduce acoustic noise. The skip frequency then
drops to very low values during no−load conditions. Refer
to Figure 18, Figure 19 and Figure 20 for typical application
waveforms during light load and quiet skip mode operating
modes.
Then NCP13992 implements proprietary light load and
quiet skip mode operating techniques that improve light load
efficiency, reduce no−load power consumption and
significantly reduce acoustic noise. Controller uses 50%
duty cycle symmetry under full and medium load
conditions. Normal current mode frequency modulation
takes place during this operating mode – refer to on−time
processing section of this datasheet. The 50% duty cycle
symmetry operating mode is replaced by continues
operation with minimum switching patterns repeated after
controlled amount of off−time when load is decreased below
Figure 18. No−load Operation
Figure 19. Quiet Skip Mode Operation
Figure 20. Light−load Operation
The High Voltage Half−bridge Driver
resistor Rboot value is 3.3 W. Figure 21 shows the internal
The driver features a traditional bootstrap circuitry,
requiring an external high voltage diode with resistor in
series for the capacitor refueling path. Minimum series
architecture of the drivers section. The device incorporates
an upper UVLO circuitry that makes sure enough V is
GS
available for the upper side MOSFET.
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NCP13992
HV
Vboot
Cboot
Internal Mupper
Pulse
Trigger
Level
Shifter
S
Mupper
Q
Q
R
HB
dV/dt_P signal
dV/dt_N signal
dV/dt
detector
UVLO
Rboot
HB
discharger
HB disch. activation
Dboot
V
CC
aux
V
CC
Fault
Mlower
GND
Internal Mlower
Delay
+
Figure 21. The NCP13992 Internal DRVs Structure
The internal dV/dt sensor, connected to the VBOOT pin,
detects the HB pin voltage transitions in order to setup the
optimum DT period – please refer to Dead−Time chapter.
The internal HV discharge switch is connected to the HB pin
and discharges resonant capacitor before application
startup. The current through the switch is regulated to
I
level until the V
threshold voltage is
DISCHARGE
HB_MIN
reached on the HB pin. The discharge system assures always
the same startup conditions for application – regardless of
previous operating state.
As stated in the maximum ratings section, the floating
portion can go up to 620 VDC on the BOOT pin. This
voltage range makes the IC perfectly suitable for offline
applications featuring a 400 V PFC front stage.
Automatic Dead−time Adjust
The dead−time period between the Mupper and Mlower
drivers is always needed in half bridge topologies to prevent
any cross conduction through the power stage MOSFETs
that would result in excessive current, high EMI noise
generation or total destruction of the application. Fixed
dead−time period is often used in the resonant converters
because this approach is simple to implement. However, this
method does not ensure optimum operating conditions in
resonant topologies because the magnetizing current is
changing with line and load conditions. The optimum
dead−time, under a given operating conditions, is equal to
the time that is needed for bridge voltage to transition
between upper and lower states and vice versa – refer to
Figure 22.
Figure 22. Optimum Dead−time Period Adjust
The MOSFET body diode conduction time is minimized
when optimum dead−time period is used which results in
maximum efficiency of a resonant converter power stage.
There are several methods to determine the optimum
dead−time period or to approximate it (for example using
auxiliary winding on main transformer or modulating
dead−time period with operating frequency of the
converter). These approaches however require a dedicated
pin for nominal dead−time adjust or auxiliary winding
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NCP13992
voltage sensing. The NCP13992 uses a dedicated method
2. The controller is latched−off in case the ZSV
that senses the VBOOT pin voltage internally and adjusts the
optimum dead−time period with respect to the actual
operating conditions of the converter. The high−voltage
dV/dt detector, connected to the VBOOT pin, delivers two
internal digital signals that are indicating Mupper to Mlower
and Mlower to Mupper transitions that occur on the HB and
VBOOT pins after the corresponding MOSFET switch is
turned−off. The controller enables the opposite MOSFET in
the power stage once the corresponding dV/dt sensor output
provides information about HB (or VBOOT) pin transition
ends.
condition is not detected within selected
t
period
DEAD_TIME_MAX
3. The controller stops operation and restarts
operation after auto−recovery period in case the
ZSV condition has not been detected within the
selected t
period
DEAD_TIME_MAX
A DT fault counter option is available. Selected number
(N ) or DT fault events have to occur in order to
DT_MAX
confirm DT fault in this case.
A fixed DT option is also available for this device. The
internal dV/dt sensor signal is not used for this device option
The ZVS transition on the bridge pin (HB) could take a
longer time or even does not finish in some cases – for
example with extremely low bulk voltage or when some
critical failure occurs. This situation should not occur
normally in correctly designed application because several
other protections would prevent such a situation. The
NCP13992 implements maximum DT period clamp that
and the t
period is used as a regular DT
DEAD_TIME_MAX
period instead. The DT fault detection is disabled in this
case.
Temperature Shutdown
The NCP13992 includes a temperature shutdown
protection. The typical TSD hysteresis is 30°C. When the
temperature rises above the upper threshold, the controller
stops switching instantaneously, and goes into the off−mode
limits driver’s off−time period to the t
DEAD_TIME_MAX
value. The corresponding MOSFET driver is forced to
turn−on by the internal logic regardless of missing dV/dt
sensor signal. This situation does not occur during normal
operation and will be considered a fault state by the device.
There are several possibilities on how the controller
continues operation after this event occurrence – depending
on the IC option:
with extremely low power consumption. The V supply is
CC
maintained (by operating the HV start−up in DSS mode) in
order to memorize the TSD event information. When the
temperature falls below the lower threshold, the full restart
(including soft−start) is initiated by the controller. The HV
startup current source features an independent
over−temperature protection which limits its output current
in case the DIE temperature exceeds TSD to avoid damage
to the HV startup silicon structure.
1. The opposite MOSFET switch is forced to turn−on
when t
period elapses and no
DEAD_TIME_MAX
fault is generated
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26
NCP13992
APPLICATION INFORMATION
Controller Operation Sequencing of NCP13992 LLC
Controller
The paragraphs below describe controller operation
sequencing under several typical cases as well as transitions
between them.
for the feedback block. The VCC management controls the
HV startup in DSS mode in order to keep enough VCC level
to hold the latch−up state memorized while the application
remains plugged−in to the mains.
The power supply is removed from the mains at point H
and the VCC voltage drops down below V
level
CC_RESET
1. Application start, Brown−out off and restart,
OVP/OTP latch and then restart – Figure 23
Application is connected to the mains at point A thus the
HV input of the controller becomes biased. The HV startup
thus the low voltage controller is released from latch. A new
application start occurs when the user plugs the application
the mains again.
current source starts charged VCC capacitor until V
CC
2. Application start, Brown−out off and restart, output
short fault with auto−recovery restart – Figure 24
Operating waveforms descriptions for this figure is
similar to one for Figure 23 from point A till point G – with
reaches V
threshold.
CC_ON
The VCC pin voltage reached V
threshold in point
CC_ON
B. The BO, FB, OVP/OTP and PFC MODE blocks are
enabled. The VBULK/PFC FB pin starts to receive divided
bulk voltage as the external HV switch is activated by PFC
one difference. The skip mode operation (FB
<
V
) blocks the IC startup after first V event
FB_SKIP_IN
CC_ON
MODE output. The V blank is activated during each
CC
instead of BO_fault.
V
CC_ON
event to ensure that the internal logic ignores all
The LLC converter operation is stopped in point G
because the controller detects an overload condition (short
circuit event in this case as the Vout drops abruptly). The
controller disables all blocks except for the FB block and the
fault logic. The HV startup DSS operation is initiated in
order to keep enough VCC level for all internal blocks that
need to be biased. Internal auto−recovery timer counts down
fault inputs until the internal blocks are fully biased and
stabilized after a V event. The IC DRVs were not
CC_ON
enabled after first V blank period in this case as the
CC
voltage on VBULK/PFC FB is below V level. The IC
BO
keeps all internal blocks biased and operates in the DSS
(Dynamic Self−Supply) mode as long as the fault conditions
is still present.
the recovery delay period t
.
A−REC_TIMER
The BO_OK condition is received (voltage on
The auto−recovery restart delay period lapses at point H.
The HV startup current source is activated to recharge VCC
capacitor before a new restart.
VBULK/PFC FB reach V
level) at point C. The IC
BO
activates the startup current source to refill VCC capacitor
in order to assure sufficient energy for a new startup. The
The V
threshold is reached in point I and all the
CC_ON
VCC capacitor voltage reaches V
level again and the
CC_ON
internal blocks are biased. The V blank and OVP/OTP
CC
VCC blank period is started. The DRVs are enabled and the
blank period are started at the same time. The LLC converter
operation is enabled, including a dedicated startup and
soft−start period. The output short circuit is removed in
between thus the Vout ramped−up and the FB loop took over
during the LLC converter soft−start period.
application is started after V blank period lapses because
CC
there is no faults condition at that time.
Line and also bulk voltage drops at point D so the BO_OK
signal become low (voltage on VBULK/PFC FB drops
below V level). The LLC DRVs are disabled as well as
BO
3. Startup, skip−mode operation, low line detection
and restart into skip−mode – Figure 25
The application is plugged into the mains at point A thus
the HV input of the controller becomes biased. The HV
startup current source starts charging the VCC capacitor
OVP/OTP block bias. The PFC MODE output stay high to
keep the bulk voltage divider connected, so the BO block
still monitors the bulk voltage. The controller activates the
HV startup current source into DSS mode to keep enough
VCC voltage for operation of all blocks that are active while
the IC is waiting for BO_OK condition.
until V reaches the V
threshold.
CC
CC_ON
The VCC pin voltage reaches the V
threshold at
CC_ON
The line voltage and thus also bulk voltage increase at
point E so the Brown−out block provide the BO_OK signal
point B. The BO, FB, OVP/OTP and PFC MODE blocks are
enabled. The VBULK/PFC FB pin begins to receive divided
bulk voltage as the external HV switch is activated by the
once the V level is reached. The startup current source is
BO
activated after BO_OK signal is received to charge the VCC
capacitor for a new restart.
PFC MODE output. The V
blank period is activated
CC
during each V
events. This blank ensures that the
CC_ON
The V
level is reached in point F. The OVP/OTP
CC_ON
internal logic ignores all fault inputs until the internal blocks
are fully biased and stabilized after V event. The IC
block is biased and the VCC blank period is started at the
same time. The controller restores operation via the regular
startup sequence and soft−start after VCC blank period
lapses since there is no fault condition detected.
The application then operates normally until the
OVP/OTP input is pulled−up at point G. The controller then
enters latch−off mode in which all blocks are disabled except
CC_ON
DRVs are not enabled even after V blank period ends
CC
because the OVP fault condition is present. The OVP fault
condition disappears after some time so the HV startup
current source is enabled to prepare enough V for a new
CC
startup attempt. The new V blank and OTP blank periods
CC
www.onsemi.com
27
NCP13992
are placed after the V
event is detected. The controller
V
level during skip mode. The device would enters
CC_ON
CC_OFF
authorizes DRVs at point C as there are no faults conditions
into off−mode.
present after the V blank period elapses. The load current
is reduced thus the FB loop reduces the primary controller
FB pin voltage.
The line voltage drops in point F, but the bulk voltage is
dropping slowly as there is nearly no consumption from the
bulk capacitor during skip mode – only some refilling bursts
are provided by the controller. The application thus
continues in skip mode operation for several skip burst
cycles.
CC
The load diminished further and the FB skip threshold is
reached in point D. The controller turns−off all the blocks
that are not essential for the controller operation during
skip−mode – i.e. all blocks except FB block and VCC
management. This technique is used to minimize the device
consumption when there are no driver pulses during
skip−mode operation. The output voltage then drops
naturally and the FB loop reflects this change into the
primary FB pin voltage that increases accordingly. The
auxiliary winding is refilling VCC capacitor during each
skip burst thus the controller is supplied from the application
during the skip mode operation.
The controller FB skip−out threshold is reached in point
E; the controller enables all blocks and LLC DRVs to refill
the output capacitor. The controller did not activate the HV
startup current source because there is enough voltage
present on the VCC pin during skip mode. The OTP blank
periods is activated at the beginning of the skip burst to mask
possible OTP faults.
The bulk voltage level less than V threshold is detected
BO
by the controller in point G during one of the skip burst
pulses. The controller thus disabled DRVs and enters DSS
mode of operation in which the OVP/OTP block is disabled
and the controller is waiting for BO_OK event. The PFC
MODE provides the V
voltage in this case to
PFC_M_ON
allow the PFC stage to refill bulk capacitors.
The line voltage is increased at point H thus the controller
receives the BO_OK signal. The BO_OK signal is received
during the period in which the HV startup current source is
active and refills the VCC capacitor.
This V
threshold is reached by the VCC pin at point
CC_ON
I. The V blank period and OVP/OTP blank period are
CC
started at the same time. The full startup sequence is enabled
at the end of the V blank period as no fault is detected. The
CC
application then enters skip mode again as the load current
is low.
Note: The VCC capacitor needs to be chosen with a value
high enough to ensure that V will not drop below the
CC
www.onsemi.com
28
NCP13992
Figure 23. Application Start, Brown−out Off and Restart, OVP/OTP Latch and then Restart
www.onsemi.com
29
NCP13992
Figure 24. Application Start, Brown−out Off and Restart, Output Short Fault with Auto−recovery Restart
www.onsemi.com
30
NCP13992
Figure 25. Startup, Skip−mode Operation, Low Line Detection and Restart into Skip
www.onsemi.com
31
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 NB MISSING PINS 2 AND 13
CASE 751DU
ISSUE O
DATE 18 OCT 2013
SCALE 1:1
NOTE 5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
D
A
2X
16
9
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS
OR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE. DIMEN
SIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
0.10 C D
F
NOTE 4
E
E1
NOTE 6
A1
L
L2
C A-B D
1
8
0.20 C
SEATING
PLANE
C
MILLIMETERS
B
NOTE 5
14X b
DETAIL A
2X 4 TIPS
DIM MIN
MAX
1.75
0.25
0.49
0.25
10.00
M
0.25
A
A1
b
1.35
0.10
0.35
0.17
9.80
TOP VIEW
2X
c
0.10 C A-B
DETAIL A
D
D
E
6.00 BSC
0.10 C
E1
e
3.90 BSC
1.27 BSC
0.10 C
L
0.40
1.27
L2
0.203 BSC
e
END VIEW
A
SEATING
PLANE
C
GENERIC
SIDE VIEW
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT
16
14X
XXXXXXXXXX
AWLYWWG
1.52
1
16
1
9
XXXXX = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
7.00
WL
Y
WW
G
8
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
14X
0.60
1.27
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON77502F
SOIC−16 NB MISSING PINS 2 AND 13
PAGE 1 OF 1
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