NCP1060_16_技术文档

NCP1060, NCP1063

High-Voltage Switcher for

Low Power Offline SMPS

The NCP106X products integrate a fixed frequency current mode

controller with a 700 V MOSFET. Available in a PDIP−7, SOIC−10 or

SOIC−16 package, the NCP106X offer a high level of integration,

including soft−start, frequency−jittering, short−circuit protection,

skip−cycle, adjustable peak current set point, ramp compensation, and a

Dynamic Self−Supply (eliminating the need for an auxiliary winding).

Unlike other monolithic solutions, the NCP106X is quiet by nature:

during nominal load operation, the part switches at one of the available

frequencies (60 kHz or 100 kHz). When the output power demand

diminishes, the IC automatically enters frequency foldback mode and

provides excellent efficiency at light loads. When the power demand

reduces further, it enters into a skip mode to reduce the standby

consumption down to a no load condition.

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MARKING DIAGRAMS

7

PDIP−7

CASE 626A

AP SUFFIX

P106xfyyy

AWL

YYWWG

8

1

Protection features include: a timer to detect an overload or a

short−circuit event, Overvoltage Protection with auto−recovery and

AC input line voltage detection (A version).

The ON proprietary integrated Over Power Protection (OPP) lets

you harness the maximum delivered power without affecting your

standby performance simply via external resistors.

For improved standby performance, the connection of an auxiliary

winding stops the DSS operation and helps to reduce input power

consumption below 50 mW at high line.

NCP106x can be seamlessly used both in non−isolated and in

isolated topologies.

16

SOIC−16

CASE 751B−05

D SUFFIX

NCP1063fyyyG

AWLYWW

16

1

10

SOIC−10

1060fyyy

ALYWX

G

10

CASE 751BQ

AD or BD SUFFIX

1

x = Power Switch Circuit On−state Resistance

x = (0 = 34 W, 3 = 11.4 W)

f = Brown In (A = Yes, B = No)

yyy = Oscillator Frequency

Features

• Built−in 700 V MOSFET with R

11.4 W (NCP1063)

of 34 W (NCP1060) and

yyy = (060 = 60 kHz, 100 = 100 kHz)

DS(on)

A

= Assembly Location

L, WL = Wafer Lot

Y, YY = Year

• Large Creepage Distance Between High−voltage Pins

• Current−Mode Fixed Frequency Operation – 60 kHz or 100 kHz

(130 kHz on demand)

W, WW = Work Week

G or G = Pb−Free Package

• Adjustable Peak Current: see below table

• Fixed Ramp Compensation

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 28 of this data sheet.

• Direct Feedback Connection for Non−isolated Converter

• Internal and Adjustable Over Power Protection (OPP) Circuit

• Skip−Cycle Operation at Low Peak Currents Only

• Dynamic Self−Supply: No Need for an Auxiliary

Winding

• Frequency Foldback to Improve Efficiency at Light

Load

• Internal 4 ms Soft−Start

• These are Pb−Free Devices

• Auto−Recovery Output Short Circuit Protection with

Typical Applications

Timer−Based Detection

• Auto−Recovery Overvoltage Protection with Auxiliary

Winding Operation

• Frequency Jittering for Better EMI Signature

• No Load Input Consumption < 50 mW

• Auxiliary / Standby Isolated and Non−isolated Power

Supplies

• Power Meter SMPS

• Wide Vin Low Power Industrial SMPS

1

Publication Order Number:

April, 2016 − Rev. 3

NCP1060/D

NCP1060, NCP1063

PRODUCT INFORMATION & INDICATIVE MAXIMUM OUTPUT POWER

230 Vac + 15%

85 − 265 Vac

Adapter

3.3 W

Open Frame

8.3 W

Adapter

Open Frame

4.7 W

Product

R

I

IPK(0)

DS(on)

NCP1060 60 kHz

NCP1063 100 kHz

34 W

300 mA

780 mA

1.9 W

3.3 W

11.4 W

6.2 W

15.5 W

7.8 W

NOTE: Informative values only, with T

= 25°C, T

= 100°C, PDIP−7 package, Self supply via Auxiliary winding and circuit mounted

amb

case

on minimum copper area as recommended.

GND

DRAIN

GND

VCC

DRAIN

GND

DRAIN

N.C.

GND

VCC

LIM/OPP

FB

DRAIN

VCC

LIM/OPP

FB

LIM/OPP

N.C.

COMP

N.C.

FB

COMP

N.C.

PDIP−7

SOIC−16

SOIC−10

Figure 1. Pin Connections

Table 1. PIN FUNCTION DESCRIPTION

Pin No

PDIP 7

SOIC 10

SOIC 16

Pin Name

Function

Pin Description

1

2

1

2

1−4

5

GND

The IC Ground

V

CC

Powers the internal

circuitry

This pin is connected to an external capacitor. The V

includes an auto−recovery over voltage protection.

DD

3

6

LIM/OPP

Ipeak set / Over

power limitation

The current drown from the pin decreases Ipeak of the

primary winding. If resistive divider from the auxiliary

winding is connected to this pin it sets the OPP compen-

sation level (it diminishes the peak current.)

4

5

4

5

7

8

FB

Feedback signal

input

This is the inverting input of the trans conductance error

amplifier. It is normally connected to the switching power

supply output through a resistor divider.

Comp

Compensation

The error amplifier output is available on this pin. The

network connected between this pin and ground adjusts

the regulation loop bandwidth. Also, by connecting an

opto−coupler to this pin, the peak current set point is

adjusted accordingly to the output power demand.

6

9−12

This un−connected pin ensures adequate creepage dis-

tance

7,8

6−10

13−16

Drain

Drain connection

The internal drain MOSFET connection

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2

NCP1060, NCP1063

Table 2. TYPICAL APPLICATIONS

• If the output voltage is

above 9.0 V typ. between

V

CC(ON)

level and V

OVP

level − VCC supplied from

output via D2

• R2 limits maximal output

power

• Direct feedback, resistive

divider formed by R3, R4

sets output voltage

• VCC supplied from DSS

• Output voltage is below 9.0

V typ.

• LIM/OPP pin floating − no

limit output power

• Optocoupler feedback

Typical Non−isolated Application – Buck Converter

• If the output voltage is

above 9.0 V typ. between

V

CC(ON)

level and V

OVP

level − VCC supplied from

output via D2

• R2 limits maximal output

power

• Direct feedback, resistive

divider formed by R3, R4

sets output voltage

• ·VCC supplied from DSS

• ·Output voltage is below

9.0 V typ.

• ·LIM/OPP pin floating −

no limit output power

• ·Direct feedback, resistive

divider formed by R2, R3

sets output voltage

Typical Non−isolated Application – Buck−Boost Converter

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3

NCP1060, NCP1063

Table 2. TYPICAL APPLICATIONS

• VCC supplied from DSS

• Output voltage is below 9.0

V typ.

• LIM/OPP pin floating − no

limit output power

• Resistive divider formed

by R2, R3 sets output volt-

age

• If the output voltage is

above 9.0 V typ. between

V

CC(ON)

level and V

OVP

level − VCC supplied from

output via D4

• LIM/OPP pin floating − no

limit output power

• Resistive divider formed

by R2, R3 sets output volt-

age

Typical Non−isolated Application – Flyback Converter

• VCC supplied from auxil-

iary winding

• Resistive divider formed

by R2, R3 sets output pow-

er limit and over power

protection

• Optocoupler feedback, re-

sistive divider formed by

R6, R7 sets output voltage

Typical Isolated Application – Flyback Converter

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4

NCP1060, NCP1063

DRAIN

VCC

UVLO

Reset

V_dd

VCC

Management

ms Filter

80−

V_CCOVP

SCP

t_SCP

V_OVP

S

R

OFF UVLO

I_pflag

Q

Line

Detection

LineOK

t_recovery

UVLO

OFF

Jittering

OSC

LineOK

TSD

V_CC

V_COMP(REF)

R_COMP(up)

Sawtooth

S

Sawtooth

Foldback

I_COMPskip

Q

R

SKIP

Ramp

compensation

GND

è

SKIP= ”1”

Shut down some

blocks to reduce consumption

LEB

COMP

I_pflag

FB/COMP

Processing

I_COMPfault

I_COMPto CS setpoint

Reset

Soft−Start

I_FreezeI_pk(0)

I_LMDEC

I_FB

Reset SS as recoving from

SCP, TSD, VCC OVP or UVLO

FB

I_LMOP

(max )

(min)

0

I_LMOP

I

PKL

I_LMDEC

V_LMOP

LIM/OPP

Figure 2. Simplified Internal Circuit Architecture

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5

NCP1060, NCP1063

Table 3. MAXIMUM RATING TABLE (All voltages related to GND terminal)

Rating

Symbol

Value

−0.3 to 20

−0.3 to 10

−0.3 to 700

10

Unit

V

Power supply voltage, V pin, continuous voltage

V

CC

Voltage on all pins, except Drain and V pin

Vinmax

BVdss

V

CC

Drain voltage

V

Maximum Current into V pin

I

mA

CC

Drain Current Peak during Transformer Saturation (T = 150°C, Note 2):

I

DS(PK)

J

NCP1060

300

850

NCP1063

Drain Current Peak during Transformer Saturation (T = 125°C, Note 2):

J

NCP1060

335

950

NCP1063

Drain Current Peak during Transformer Saturation (T = 25°C, Note 2):

J

NCP1060

520

NCP1063

1500

Thermal Resistance Junction−to−Air – PDIP7 with 200 mm@ of 35−m copper area

Thermal Resistance Junction−to−Air – SOIC10 with 200 mm@ of 35−m copper area

Thermal Resistance Junction−to−Air – SOIC16 with 200 mm@ of 35−m copper area

Maximum Junction Temperature

R

T

115

°C/W

°C

θ

J−A

132

104

150

JMAX

Storage Temperature Range

−60 to +150

°C

Human Body Model ESD Capability (All pins except HV pin) per JEDEC JESD22−A114F

Charged−Device Model ESD Capability per JEDEC JESD22−C101E

HBM

CDM

2

1

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

2. Maximum drain current I

is obtained when the transformer saturates. It should not be mixed with short pulses that can be seen at turn

DS(PK)

on. Figure 3 below provides spike limits the device can tolerate.

Figure 3. Spike Limits

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NCP1060, NCP1063

Table 4. ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 14 V unless otherwise noted)

J

CC

Symbol

SUPPLY SECTION AND V MANAGEMENT

Rating

Min

Typ

Max

Unit

CC

V

increasing level at which the switcher starts operation

2 (5)

8.4

7.0

6.7

9.0

7.5

7.0

9.5

7.8

7.2

V

CC(on)

CC

V

decreasing level at which the HV current source restarts

CC(min)

V

decreasing level at which the switcher stops operation (UVLO)

V

CC(off)

I

Internal IC consumption, NCP1060 switching at 60 kHz, LIM/OPP = 0 A

Internal IC consumption, NCP1060 switching at 100 kHz, LIM/OPP = 0 A

Internal IC consumption, NCP1063 switching at 60 kHz, LIM/OPP = 0 A

Internal IC consumption, NCP1063 switching at 100 kHz, LIM/OPP = 0 A

−

0.92

0.97

0.99

1.07

1.05

1.10

1.12

1.22

mA

CC1

I

Internal IC consumption, COMP is 0 V (No switching on MOSFET)

2 (5)

−

340

−

mA

CCskip

POWER SWITCH CIRCUIT

R

Power Switch Circuit on−state resistance

NCP1060 (Id = 50 mA)

Tj = 25°C

7, 8

(6−10)

(13−16)

W

DS(on)

−

34

65

41

72

Tj = 125°C

NCP1063 (Id = 50 mA)

Tj = 25°C

Tj = 125°C

−

11.4

22

14.0

24

BV

Power Switch Circuit & Startup breakdown voltage

7, 8

(6−10)

(13−16)

700

−

V

DSS

(ID

= 120 mA, Tj = 25°C)

(off)

I

Power Switch & Startup breakdown voltage off−state leakage current

Tj = 125°C (Vds = 700 V)

7, 8

(6−10)

(13−16)

−

84

−

mA

ns

DSS(off)

Switching characteristics (R = 50 W, V set for I

= 0.7 x Ilim)

7, 8

(6−10)

(13−16)

L

DS

drain

t

r

Turn−on time (90% − 10%)

Turn−off time (10% − 90%)

−

20

10

−

t

f

t

Minimum on time

NCP1060

NCP1063

7, 8

(6−10)

(13−16)

on(min)

−

200

230

−

INTERNAL START−UP CURRENT SOURCE

I

High−voltage current source, V = V

– 200 mV

7, 8

(6−10)

(13−16)

5

−

8

12

−

mA

start1

CC

CC(on)

I

High−voltage current source, V = 0 V

7, 8

(6−10)

(13−16)

0.5

1.4

start2

CC

V

CC

Transient level for I

to I toggling point

start2

2 (5)

−

V

CCTH

start1

V

Minimum startup voltage, V = 0 V

7, 8

21

start(min)

CC

(6−10)

(13−16)

CURRENT COMPARATOR

I

Maximum internal current setpoint at 50% duty cycle

mA

IPK

FB = 2 V, LIM/OPP = 0 mA, Tj = 25°C

NCP1060

NCP1063

−

250

650

−

I

Maximum internal current setpoint at beginning of switching cycle

IPK(0)

FB = 2 V, LIM/OPP pin open Tj = 25°C

NCP1060

NCP1063

−

268

702

300

780

332

858

3. The final switch current is: I

/ (V /L + S ) x V /L + V /L x t

, with S the built−in slope compensation, Vin the input voltage,

prop a

IPK(0)

in

P

a

in

P

in

P

L

P

the primary inductor in a flyback, and t

the propagation delay.

prop

4. Oscillator frequency is measured with disabled jittering.

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7

NCP1060, NCP1063

Table 4. ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 14 V unless otherwise noted)

J

CC

Symbol

CURRENT COMPARATOR

Rating

Min

Typ

Max

Unit

I

Final switch current with a primary slope of 200 mA/ms,

= 60 kHz (Note 3), LIM/OPP pin open

NCP1060

NCP1063

mA

IPKSW

F

SW

−

330

740

−

I

Final switch current with a primary slope of 200 mA/ms,

= 100 kHz (Note 3), LIM/OPP pin open

mA

F

SW

NCP1060

NCP1063

−

320

710

−

I

Maximum internal current setpoint at beginning of switching cycle

LMDEC

FB = 2 V, LIM/OPP = −285 mA, Tj = 25°C

NCP1060

NCP1063

−

128

312

−

t

Soft−start duration (guaranteed by design)

−

4

−

ms

ns

SS

t

Propagation delay from current detection to drain OFF state

70

prop

t

Leading Edge Blanking Duration

NCP1060

NCP1063

LEB

−

130

160

−

INTERNAL OSCILLATOR

f

Oscillation frequency, 60 kHz version, Tj = 25°C (Note 4)

Oscillation frequency, 100 kHz version, Tj = 25°C (Note 4)

−

54

90

−

60

100

6

66

110

−

kHz

%

OSC

f

Frequency jittering in percentage of f

jitter

OSC

f

Jittering swing frequency

−

300

66

−

Hz

%

swing

D

Maximum duty−cycle

62

72

max

ERROR AMPLIFIER SECTION

Voltage Feedback Input (V

V

REF

= 2.5 V)

COMP

4 (7)

5 (8)

4 (7)

3.2

−

3.3

1

3.4

−

V

mA

mS

mA

V

I

FB

Input Bias Current (V = 3.3 V)

FB

G

Transconductance

2

M

I

OTA maximum current capability (V > V )

OTAen

150

1.3

OTAlim

FB

V

OTAen

FB voltage to disable OTA

0.7

1.7

COMPENSATION SECTION

COMP current for which Fault is detected

I

5 (8)

−

−40

−44

−80

−

mA

COMPfault

I

COMP current for which internal current set−point is 100% (I

)

IPK(0)

COMP100%

I

COMP current for which internal current setpoint is:

COMPfreeze

I

(NCP1060/3)

Freeze1 or 2

V

Equivalent pull−up voltage in linear regulation range

(Guaranteed by design)

5 (8)

3 (6)

−

2.7

−

V

kΩ

V

COMP(REF)

R

Equivalent feedback resistor in linear regulation range

(Guaranteed by design)

17.7

COMP(up)

V

LMOP

Voltage on LIM/OPP pin @ I

= −35 mA

= −250 mA, Tj = 25°C

1.40

1.28

1.50

1.35

1.60

1.42

LMOP

I

Maximum current from LIM/OPP pin

3 (6)

−330

−26

−420

−32

mA

V

LMOP

I

Current at which LIM/OPP starts to decrease I

Current at which LIM/OPP stops to decrease I

−20

LMOP(min)

LMOP(max)

PEAK

I

−285

−0.7

PEAK

I

Negative Active Clamp Voltage (I

= −2.5 mA)

LMOP(neg)

LMOP

3. The final switch current is: I

/ (V /L + S ) x V /L + V /L x t

, with S the built−in slope compensation, Vin the input voltage,

prop a

IPK(0)

in

P

a

in

P

in

P

L

P

the primary inductor in a flyback, and t

the propagation delay.

prop

4. Oscillator frequency is measured with disabled jittering.

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8

NCP1060, NCP1063

Table 4. ELECTRICAL CHARACTERISTICS

(For typical values T = 25°C, for min/max values T = −40°C to +125°C, V = 14 V unless otherwise noted)

J

CC

Symbol

COMPENSATION SECTION

Positive Active Clamp (Guaranteed by design)

FREQUENCY FOLDBACK & SKIP

Start of frequency foldback COMP pin current level

Rating

Min

Typ

Max

Unit

I

3 (6)

2.5

mA

LMOP(pos)

I

5 (8)

−

−68

−100

25

−

mA

COMPfold

I

End of frequency foldback COMP pin current level, f = f

COMPfold(end)

sw

min

f

The frequency below which skip−cycle occurs

The COMP pin current level to enter skip mode

21

−

29

−

kHz

mA

min

I

5 (8)

−120

110

COMPskip

I

Internal minimum current setpoint (I

= I

) in NCP1060

) in NCP1063

−

mA

Freeze1

COMP

COMPFreeze

−

270

−

Freeze2

RAMP COMPENSATION

S

The internal ramp compensation @ 60 kHz:

NCP1060

NCP1063

mA/ms

a(60)

−

8.4

15.6

−

S

a(100)

The internal ramp compensation @ 100 kHz:

NCP1060

NCP1063

−

14

26

−

PROTECTIONS

t

Fault validation further to error flag assertion

OFF phase in fault mode

−

35

−

48

400

18.0

80

−

ms

V

SCP

t

recovery

V

CC

voltage at which the switcher stops pulsing

2 (5)

−

17.0

−

18.8

−

OVP

t

The filter of V OVP comparator

ms

V

CC

V

The drain pin voltage above which allows MOSFET operate, which is

detected after TSD, UVLO, SCP, or V OVP mode. (A version only)

7,8

(6−10)

(13−16)

67

87

110

HV(EN)

CC

TEMPERATURE MANAGEMENT

TSD Temperature shutdown (Guaranteed by design)

TSD Hysteresis in shutdown (Guaranteed by design)

3. The final switch current is: I / (V /L + S ) x V /L + V /L x t

−

150

−

163

20

−

°C

hyst

, with S the built−in slope compensation, Vin the input voltage,

IPK(0)

in

P

a

in

P

in

P

prop

a

L

P

the primary inductor in a flyback, and t

the propagation delay.

prop

4. Oscillator frequency is measured with disabled jittering.

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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NCP1060, NCP1063

TYPICAL CHARACTERISTICS

9.15

9.10

9.05

9.00

8.95

7.52

7.50

7.48

7.46

7.44

7.42

7.40

7.38

7.36

8.90

8.85

7.34

7.32

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 4. V_CC(on)vs. Temperature

Figure 5. V_CC(min)vs. Temperature

7.00

6.98

6.96

6.94

6.92

800

700

600

500

400

300

200

6.90

6.88

100

0

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 6. V_CC(off)vs. Temperature

Figure 7. I_DSS(off)vs. Temperature

0.95

0.94

0.93

0.92

0.91

0.90

0.99

0.98

0.97

0.96

0.95

0.94

0.89

0.88

0.93

0.92

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 8. I_{CC1 60 kHz}vs. Temperature

Figure 9. I_{CC1 100 kHz}vs. Temperature

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NCP1060, NCP1063

TYPICAL CHARACTERISTICS

310

308

306

304

302

300

298

296

294

292

770

765

760

755

750

745

740

735

730

725

720

290

288

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 10. I_IPK(0)1060vs. Temperature

Figure 11. I_IPK(0)1063vs. Temperature

12

10

8

0.6

0.5

0.4

6

0.3

0.2

4

2

0

0.1

0

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 12. I_start1vs. Temperature

Figure 13. I_start2vs. Temperature

70

60

50

40

30

20

25

20

15

10

5

0

10

0

−40 −20

0

20

40

60

80

100

120

−40 −20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 14. R_DS(on)1060vs. Temperature

Figure 15. R_DS(on)1063vs. Temperature

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NCP1060, NCP1063

TYPICAL CHARACTERISTICS

60.0

59.5

100

99

98

97

96

95

94

59.0

58.5

58.0

57.5

57.0

56.5

93

92

56.0

55.5

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 16. f_OSC60vs. Temperature

Figure 17. f_OSC100vs. Temperature

109

108

107

106

105

104

274

272

270

268

266

264

262

260

103

102

101

100

258

256

−40 −20

0

20

40

60

80

100

120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 18. I_freeze1060vs. Temperature

Figure 19. I_freeze1063vs. Temperature

66.2

66.1

66.0

65.9

65.8

25.8

25.6

25.4

25.2

25.0

24.8

65.7

65.6

24.6

24.4

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 20. D_(max)vs. Temperature

Figure 21. f_minvs. Temperature

www.onsemi.com

12

NCP1060, NCP1063

TYPICAL CHARACTERISTICS

430

425

420

415

410

405

400

395

53

52

51

50

49

48

47

46

390

385

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 22. t_recoveryvs. Temperature

Figure 23. t_SCPvs. Temperature

18.2

18.1

92

91

90

89

88

87

86

18.0

17.9

17.8

17.7

17.6

17.5

17.4

85

84

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 24. V_OVPvs. Temperature

Figure 25. V_HV(EN)vs. Temperature

3.34

3.33

3.32

3.31

3.30

3.29

3.28

3.27

3.26

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

3.25

3.24

−40 −20

0

20

40

60

80

100 120

−40 −20

0

20

40

60

80

100 120

TEMPERATURE (°C)

Figure 26. V_REFvs. Temperature

Figure 27. V_OTAenvs. Temperature

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13

NCP1060, NCP1063

TYPICAL CHARACTERISTICS

1.075

1.05

2.5

2.0

1.5

1.0

NCP1063

NCP1060

1.025

1.0

0.975

0.5

0

0.95

0.925

−50 −25

0

25

50

75

100

125 150

−50

−25

0

25

50

75

100

125

T , JUNCTION TEMPERATURE (°C)

J

TEMPERATURE (°C)

Figure 28. Drain Current Peak during Transformer

Saturation vs. Junction Temperature

Figure 29. Breakdown Voltage vs. Temperature

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14

NCP1060, NCP1063

Application Information

Introduction

♦ V OVP is confirmed,

CC

The NCP106X offers a complete current−mode control

solution. The component integrates everything needed to

build a rugged and cost effective Switch−Mode Power

Supply (SMPS) featuring low standby power. The Quick

Selection Table, Table 5, details the differences between

♦ UVLO,

♦ TSD

• If the drain voltage is lower than the internal threshold

(V

), the internal power switch is inhibited. This

HV(EN)

avoids operating at too low ac input. This is also called

brown−in function in some fields. For applications not

using standard AC mains (24 Vdc industrial bus for

instance), the B version doesn’t incorporate this line

detection and let the device start as soon as voltage

references, mainly peak current setpoints, R

operating frequency.

value and

DS(on)

• Current−mode operation: the controller uses

current−mode control architecture.

• 700 V –_ Power MOSFET: Due to ON Semiconductor

Very High Voltage Integrated Circuit technology, the

circuit hosts a high−voltage power MOSFET featuring

supply reaches V

start(min).

• Frequency jittering: an internal low−frequency

modulation signal varies the pace at which the

oscillator frequency is modulated. This helps spreading

out energy in conducted noise analysis. To improve the

EMI signature at low power levels, the jittering remains

active in frequency foldback mode.

• Soft−Start: a 4 ms soft−start ensures a smooth startup

sequence, reducing output overshoots.

• Frequency foldback capability: a continuous flow of

pulses is not compatible with no−load/light−load

standby power requirements. To excel in this domain,

the controller observes the COMP pin current

a 34 W or 11.4 W R

– Tj = 25°C. This value lets

DS(on)

the designer build a power supply up to 7.8 W or

15.5 W operated on universal mains. An internal

current source delivers the startup current, necessary to

crank the power supply.

• Dynamic Self−Supply: Due to the internal high

voltage current source, this device could be used in the

application without the auxiliary winding to provide

supply voltage.

• Short circuit protection: by permanently monitoring

the COMP line activity, the IC is able to detect the

presence of a short−circuit, immediately reducing the

information and when it reaches a level of I

the oscillator then starts to reduce its switching

frequency as the feedback current continues to increase

(the power demand continues to reduce). It can go

down to 25 kHz (typical) reached for a feedback level

,

COMPfold

output power for a total system protection. A t

timer

SCP

is started as soon as the COMP current is below

threshold, I , which indicates the maximum

COMPfault

peak current. If at the end of this timer the fault is still

present, then the device enters a safe, auto−recovery

burst mode, affected by a fixed timer recurrence,

of I

(100 mA roughly). At this point, if the

COMPfold(end)

power continues to drop, the controller enters classical

skip−cycle mode.

t . Once the short has disappeared, the controller

recovery

• Skip: if SMPS naturally exhibits a good efficiency at

nominal load, it begins to be less efficient when the

output power demand diminishes. By skipping

resumes and goes back to normal operation.

• Built−in VCC Over Voltage Protection: when the

auxiliary winding is used to bias the V pin (no DSS),

CC

un−needed switching cycles, the NCP106X drastically

reduces the power wasted during light load conditions.

an internal comparator is connected to V pin. In case

CC

the voltage on the pin exceeds a level of V

(18 V

OVP

• Ipeak set: If current in range 26 mA and 285 mA is

drawn from the pin, the peak current is proportionally

reduced down to 40% of its original value. This feature

enables to designer to set up the peak current to the

value which is ideal for the application.

typically), the controller immediately stops switching

and waits a full timer period (t ) before

recovery

attempting to restart. If the fault is gone, the controller

resumes operation. If the fault is still there, e.g. a

broken opto−coupler, the controller protects the load

through a safe burst mode.

By routing a portion of the negative voltage present during

the on−time on the auxiliary winding to the LIM/OPP pin,

the user has a simple and non−dissipative means to alter the

maximum peak current setpoint as the bulk voltage

increases.

• Line detection: An internal comparator monitors the

drain voltage as recovering from one of the following

situations:

♦ Short Circuit Protection,

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15

NCP1060, NCP1063

Application Information

Startup Sequence

When the power supply is first powered from the mains

outlet, the internal current source (typically 8.0 mA) is

pulses are delivered by the output stage: the circuit is awake

and activates the power MOSFET if the bulk voltage is

biased and charges up the V capacitor from the drain pin.

above V

level (87 V typically) for A version and if

CC

HV(EN)

Once the voltage on this V capacitor reaches the V

bulk voltage is above V

(21 V dc) for B version.

CC

CC(on)

start(min)

level (typically 9.0 V), the current source turns off and

Figure 30 details the simplified internal circuitry.

Vbulk

I1

R

limit

Drain

5

I_start1

I_CC1

1

I2

−

+

C_VCC

V_CC(on)

V_CC(min)

VCC > 18V ?

à

OVP fault

8

V_OVP

Figure 30. The Internal Arrangement of the Start−up Circuitry

Being loaded by the circuit consumption, the voltage on

the V capacitor goes down. When V is below V

capacitor and the IC consumption. A 1.5 V ripple takes place

on the V pin whose average value equals (V

+

CC(on)

CC

CC(min)

CC

level (7.5 V typically), it activates the internal current source

to bring V toward V level and stops again: a cycle

V

DSS.

)/2. Figure 31 portrays a typical operation of the

CC(min)

CC

CC(on)

takes place whose low frequency depends on the V

CC

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16

NCP1060, NCP1063

10

9

8

7

6

5

4

3

2

1

0

9.0 V

7.5 V

V_CC

Device

Internal

Pulses

V_CCTH

0

1

2

3

4

5

6

7

8

9

10

TIME (ms)

Startup Duration

Figure 31. The Charge/Discharge Cycle Over a 1 mF V_CCCapacitor

As one can see, even if there is auxiliary winding to provide

t

duration (400 ms typically). Then a new start−up

recovery

energy for V , it happens that the device is still biased by

DSS during start−up time or some fault mode when the

attempt takes place to check whether the fault has

disappeared or not. The OVP paragraph gives more design

details on this particular section.

CC

voltage on auxiliary winding is not ready yet. The V

CC

capacitor shall be dimensioned to avoid V crosses V

CC

CC(off)

Fault Condition – Short−circuit on V_CC

In some fault situations, a short−circuit can purposely

level, which stops operation. The ΔV between V

CC(off)

and

CC(min)

V

is 0.5 V. There is no current source to charge V

CC

occur between V and GND. In high line conditions (V

CC

HV

capacitor when driver is on, i.e. drain voltage is close to zero.

= 370 V ) the current delivered by the startup device will

DC

Hence the V capacitor can be calculated using

CC

seriously increase the junction temperature. For instance,

I_CC1@ D_max

f_OSC@ DV

since I

equals 5 mA (the min corresponds to the highest

(eq. 1)

start1

C_VCC

w

T ), the device would dissipate 370 x 5 m = 1.85 W. To avoid

j

Take the 60 kHz device as an example. C

should be

this situation, the controller includes a novel circuitry made

VCC

above

of two startup levels, I

and I

. At power−up, as long

start1

start2

as V is below a 1.4 V level, the source delivers I

CC

start2

0.8 m @ 72%

54 kHz @ 0.5

+ 21 nF.

(around 500 mA typical), then, when V reaches 1.4 V, the

CC

source smoothly transitions to I

and delivers its nominal

start1

A margin that covers the temperature drift and the voltage

drop due to switching inside FET should be considered, and

thus a capacitor above 0.1 mF is appropriate.

value. As a result, in case of short−circuit between V and

CC

GND, the power dissipation will drop to 370 x 500 m =

185 mW. Figure 31 portrays this particular behavior.

The first startup period is calculated by the formula C x V

= I x t, which implies a 1 m x 1.4 / 500 m = 2.8 ms startup time

for the first sequence. The second sequence is obtained by

The V capacitor has only a supply role and its value

CC

does not impact other parameters such as fault duration or

the frequency sweep period for instance. As one can see on

Figure 30, an internal OVP comparator, protects the

toggling the source to 8 mA with a delta V of V

–

CC(on)

switcher against lethal V runaways. This situation can

CC

V

CCTH

= 9.0 – 1.4 = 7.6 V, which finally leads to a second

occur if the feedback loop optocoupler fails, for instance,

and you would like to protect the converter against an over

voltage event. In that case, the over voltage protection

(OVP) circuit and immediately stops the output pulses for

startup time of 1 m x 7.6 / 8 m = 0.95 ms. The total startup

time becomes 2.8 m + 0.95 m = 3.75 ms. Please note that this

calculation is approximated by the presence of the knee in

the vicinity of the transition.

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17

NCP1060, NCP1063

Fault Condition – Output Short−circuit

asserted, Ipflag, indicating that the system has reached its

maximum current limit set point. The assertion of this flag

triggers a fault counter t (48 ms typically). If at counter

As soon as V

reaches V , drive pulses are

CC(on)

CC

internally enabled. If everything is correct, the auxiliary

SCP

winding increases the voltage on the V pin as the output

completion, I

remains asserted, all driving pulses are

CC

pflag

voltage rises. During the start−sequence, the controller

smoothly ramps up the peak drain current to maximum

stopped and the part stays off in t

duration (about

recovery

400 ms). A new attempt to re−start occurs and will last

48 ms providing the fault is still present. If the fault still

affects the output, a safe burst mode is entered, affected by

a low duty−cycle operation (11%). When the fault

disappears, the power supply quickly resumes operation.

Figure 32 depicts this particular mode:

setting, i.e. I , which is reached after a typical period of

IPK

4 ms. When the output voltage is not regulated, the current

coming through COMP pin is below I

level (40 mA

COMPfault

typically), which is not only during the startup period but

also anytime an overload occurs, an internal error flag is

V

CC(on)

V

CC

V

CC(min)

IpFlag

Open loop FB

V

COMP

48 ms typ.

Fault

Timer

400 ms typ.

DRV

internal

Figure 32. In case of short−circuit or overload, the NCP106X protects itself and the power supply via a low

frequency burst mode. The V_CCis maintained by the current source and self−supplies the controller.

Auto−recovery Over Voltage Protection

IC against high voltage spikes, which can damage the IC,

and to filter out the Vcc line to avoid undesired OVP

The particular NCP106X arrangement offers a simple

way to prevent output voltage runaway when the

optocoupler fails. As Figure 33 shows, a comparator

activation. R

should be carefully selected to avoid

limit

triggering the OVP as we discussed, but also to avoid

monitors the V pin. If the auxiliary pushes too much

disturbing the V in low / light load conditions.

CC

voltage into the C

considers an OVP situation and stops the internal drivers.

When an OVP occurs, all switching pulses are permanently

capacitor, then the controller

Self−supplying controllers in extremely low standby

applications often puzzles the designer. Actually, if a SMPS

operated at nominal load can deliver an auxiliary voltage of

VCC

disabled. After t

delay, it resumes the internal drivers.

an arbitrary 16 V (V ), this voltage can drop below 10 V

recovery

nom

If the failure symptom still exists, e.g. feedback

opto−coupler fails, the device keeps the auto−recovery OVP

(V ) when entering standby. This is because the

recurrence of the switching pulses expands so much that the

stby

low frequency re−fueling rate of the V capacitor is not

enough to keep a proper auxiliary voltage.

mode. It is recommended insertion of a resistor (R_limit

)

CC

between the auxiliary dc level and the V pin to protect the

CC

www.onsemi.com

18

NCP1060, NCP1063

Drain

V

_{CC (on)}= 9.0 V

I_{start 1}

V_CC

V_{CC (min )}= 7.5 V

D1

R_limit

Shut down

Internal DRV

C_VCC

C_AUX

N_AUX

ms

80

filter

V_OVP

GND

Figure 33. A more detailed view of the NCP106X offers better insight on how to properly wire an auxiliary winding

V_OVP

V _CC(on)

V _CC(min)

V_CC

I_COMP

48 ms typ.

Fault level

TIMER

400 ms typ.

DRV

internal

Figure 34. describes the main signal variations when the part operates in auto−recovery OVP:

Soft−start

The NCP106X features a 4 ms soft−start which reduces

the power−on stress but also contributes to lower the output

overshoot. Figure 35 shows a typical operating waveform.

The NCP106X features a novel patented structure which

offers a better soft−start ramp, almost ignoring the start−up

pedestal inherent to traditional current−mode supplies.

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19

NCP1060, NCP1063

V_CC

V_CCON

0V (fresh PON)

Drain current

Max Ip

4 ms

Figure 35. The 4 ms Soft−start Sequence

Jittering

Frequency jittering is a method used to soften the EMI

signature by spreading the energy in the vicinity of the main

switching component. The NCP106X offers a 6%

deviation of the nominal switching frequency. The sweep

sawtooth is internally generated and modulates the clock up

and down with a fixed frequency of 300 Hz. Figure 36 shows

the relationship between the jitter ramp and the frequency

deviation. It is not possible to externally disable the jitter.

Jitter ramp

63.6 kHz

60 kHz

Internal

sawtooth

56.4 kHz

adjustable

Figure 36. Modulation Effects on the Clock Signal by the Jittering Sawtooth

Line Detection (for A version only)

An internal comparator monitors the drain voltage as

recovering from one of the following situations:

• UVLO

• TSD

If the drain voltage is lower than the internal threshold

• Short Circuit Protection,

V

HV(EN)

(87 Vdc typically), the internal power switch is

• V OVP is confirmed,

CC

inhibited. This avoids operating at too low ac input.

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20

NCP1060, NCP1063

Frequency Foldback

The reduction of no−load standby power associated with

the need for improving the efficiency, requires to change the

traditional fixed−frequency type of operation. This device

implements a switching frequency foldback when the

Below this value, the peak current setpoint is frozen to 30%

of the I . The only way to further reduce the transmitted

PK(0)

power is to diminish the operating frequency down to F

min

(25 kHz typically). This value is reached at a COMP current

level of I (100 mA typically). Below this point,

COMP current passes above a certain level, I

, set

COMPfold

COMPfold(end)

around 68 mA. At this point, the oscillator enters frequency

foldback and reduces its switching frequency.

The internal peak current set−point is following the

if the output power continues to decrease, the part enters skip

cycle for the best noise−free performance in no−load

conditions. Figure 37 and Figure 38 depict the adopted

scheme for the part.

COMP current information until its level reaches I

.

Freeze

110

100

90

80

70

60

50

40

30

20

10

0

NCP1060

NCP1063

50

60

70

80

90

100

I_COMP[mA]

Figure 37. By observing the current on the COMP pin, the controller reduces its

switching frequency for an improved performance at light load.

900

NCP1060

NCP1063

800

700

600

500

400

300

200

100

0

40

50

60

70

80

90

100

110

I_COMP[mA]

Figure 38. Ipk set−point is frozen at lower power demand.

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21

NCP1060, NCP1063

350

300

250

200

150

100

50

NCP1060

NCP1063

0

40

50

60

70

80

90

100

110

I_COMP[mA]

Figure 39. Ipk set−point is frozen at lower power demand (I_LMOP≥ 285 mA)

Feedback and Skip

Figure 40 depicts the relationship between COMP pin

voltage and current. The COMP pin operates linearly as the

this linear operating range, the dynamic resistance is

17.7 kW typically (R ) and the effective pull up

COMP(up)

voltage is 2.7 V typically (V

). When I

is

COMP(REF)

COMP

absolute value of COMP current (I ) is above 40 mA. In

COMP

decreases, the COMP voltage will increase to 3.2 V.

3.5

3

2.5

2

1.5

1

0.5

0

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

I_COMP[μA]

Figure 40. COMP Pin Voltage vs. Current

Figure 41 depicts the skip mode block diagram. When the

COMP current information reaches I , the internal

internal skip comparator is minimized to lower the ripple of

the auxiliary voltage for V pin and V of power supply

COMPskip

CC

OUT

clock setting the flip−flop is blanked and the internal

consumption of the controller is decreased. The hysteresis of

during skip mode. It easies the design of V over load

range.

CC

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22

NCP1060, NCP1063

Jittering

OSC

S

R

DRV stage

Q

Foldback

V_COMP(REF)

R_COMP(UP)

I_COMPskip

SKIP

CS comparator

COMP

Figure 41. Skip Cycle Schematic

Ilimit and OPP Function

The function makes the integrated circuit more flexible. The current drawn out of LIM/OPP pin defines the current set point.

900

NCP1060

NCP1063

800

700

600

500

400

300

200

100

0

50

100

150

200

250

300

350

I_LMOP[mA]

Figure 42. Ipk set−point dependence on I_LMOPcurrent

There are several known ways to implement Over Power

Protection (OPP), all suffering from particular problems.

These problems range from the added consumption burden

on the converter or the skip−cycle disturbance brought by

the current−sense offset. A way to reduce the power

capability at high line is to capitalize on the negative voltage

swing present on the auxiliary diode anode. During the

R

and R

(Figure 43) define current drawn from

OPPU

OPPL

LIM/OPP and the negative voltage on auxiliary winding.

The negative voltage is tied up with bulk voltage, so the

higher the bulk voltage is, the deeper is the negative voltage

on auxiliary winding, the higher current is drawn from

LIM/OPP pin and the lower the peak current is. During the

internal MOSFET off period, voltage on auxiliary winding

is positive, but the IC ignores the LIM/OPP current. The

positive LIM/OPP current has no influence on proper IC

function.

power switch on−time, this point dips to –NV , N being the

in

turns ratio between the primary winding and the auxiliary

winding. The negative plateau on auxiliary winding will

have an amplitude dependant on the input voltage. Resistors

www.onsemi.com

23

NCP1060, NCP1063

D4

OSC

VCC

Aux

winding

S

R

C2

MOSFET

Q

Vramp + Vsense

I_COMP

I_COMPto CS setpoint

R_OPPU

I_LMDEC

I_FreezeI_pk(0)

mA

250

25

0

I_LMOP

LIM/OPP

I_LMOP

I

PKL

I_LMDEC

R_OPPL

Figure 43. The OPP Circuitry Affects the Maximum Peak Current Set Point

Ramp Compensation and Ipk Set−point

NCP1060

NCP1063

60 kHz 100 kHz

14 mA/ms 15.6 mA/ms 26 mA/ms

In order to allow the NCP106X to operate in CCM with a

duty cycle above 50%, a fixed slope compensation is

internally applied to the current−mode control.

Here we got a table of the ramp compensation, the initial

current set point, and the final current set−point of different

versions of switcher.

f

60 kHz

100 kHz

sw

S

8.4 mA/ms

a

I

250 mA

650 mA

pk(Duty

=50%)

I

300 mA

780 mA

pk(0)

Figure 44 depicts the variation of I set−point vs. the

PK

power switcher duty ratio, which is caused by the internal

ramp compensation.

900

800

700

600

500

400

300

200

100

0

NCP1060

NCP1063

0%

10%

20%

30%

40%

50%

60%

70%

Dutty Ratio [%]

Figure 44. I_PKset−point varies with power switch on time, which is caused by the ramp compensation.

FB Pin Function

positive current is defined by internal R

resistor

COMP(up)

The FB pin is used in non isolated SMPS application only.

Portion of the output voltage is connected into the pin. The

and V

voltage. If FB path loop is broken (i.e. the FB

COMP(ref)

pin is disconnected), an internal current I (1 mA typ.) will

FB

voltage is compared with internal V

(3.3 V) using

pull up the FB pin and the IC stops switching to avoid

uncontrolled output voltage increasing.

In isolated topology, the FB pin should be connected to

GND pin. In this configuration no current flows from OTA

to COMP pin (OTA is disabled) so the OTA has no influence

on regulation at all.

REF

Operation Transconductance Amplifier (Figure 45). The

OTAs output is connected to COMP pin. The OTA output is

accessible through the COMP pin and is used for the loop

compensation, usually an RC network. The current

capability of OTA is limited to −150 mA typically. The

www.onsemi.com

24

NCP1060, NCP1063

V_{COMP (REF )}

V max = 265 Vac or 375 Vdc

in

V

= 12 V

= 5 W

out

R_{COMP (up)}

P

I_COMP

Operating mode is CCM

COMP

η = 0.8

1. The lateral MOSFET body−diode shall never be

forward biased, either during start−up (because of

a large leakage inductance) or in normal operation

as shown in Figure 46. This condition sets the

maximum voltage that can be reflected during toff.

As a result, the Flyback voltage which is reflected

on the drain at the switch opening cannot be larger

than the input voltage. When selecting

I_FB

I_OTAlim

OTA out = 0 A

if FB = 0 V

FB

OTA

V_REF

components, you thus must adopt a turn ratio

which adheres to the following equation:

ǒ

Ǔ

N @ V_out) V_ft V_in,min

(eq. 2)

Figure 45. FB Pin Connection

Design Procedure

The design of an SMPS around a monolithic device does

not differ from that of a standard circuit using a controller

and a MOSFET. However, one needs to be aware of certain

characteristics specific of monolithic devices. Let us follow

the steps:

2. In our case, since we operate from a 127 V DC rail

while delivering 12 V, we can select a reflected

voltage of 120 V dc maximum. Therefore, the turn

ratio Np:Ns must be smaller than

V_reflect

120

V_out) V_f

+

+ 9.6 or Np : Ns t 9.6.

12 ) 0.5

Here we choose N = 8 in this case. We will see later

on how it affects the calculation.

V min = 90 Vac or 127 Vdc once rectified, assuming a low

bulk ripple

in

350

250

150

50.0

> 0 !!

−50.0

1.004M

1.011M

1.018M

1.025M

1.032M

Figure 46. The Drain−Source Wave Shall Always be Positive

www.onsemi.com

25

NCP1060, NCP1063

DI_L

I_Lavg

where K +

and defines the amount of ripple we want in CCM (see

Figure 47).

• Small K: deep CCM, implying a large primary

inductance, a low bandwidth and a large leakage

inductance.

• Large K: approaching DCM where the RMS losses are

worse, but smaller inductance, leading to a better

leakage inductance.

From Equation 6, a K factor of 1 (50% ripple), gives an

inductance of:

2

(

)

127 @ 0.44

L +

+ 10.04 mH

60k @ 1 @ 5

V_in@ d

L @ f_sw

127 @ 0.44

10.04m @ 60k

DI_L+

+

+ 92.8 mA peak to peak

Figure 47. Primary Inductance Current

Evolution in CCM

The peak current can be evaluated to be:

I_avg

d

DI_L

2

3. Lateral MOSFETs have a poorly doped

body−diode which naturally limits their ability to

sustain the avalanche. A traditional RCD clamping

network shall thus be installed to protect the

MOSFET. In some low power applications, a

simple capacitor can also be used since

49.2 m 92.8 m

I_peak

+

)

+

)

+ 158 mA

0.44

2

On I , I

can also be calculated:

L

Lavg

DI

92.8m

2

I_Lavg+ I_peak

*

^L+ 158m *

+ 111.6 mA

2

6. Based on the above numbers, we can now evaluate

the conduction losses:

L_f

C_tot

ǒ

Ǔ

V_drain,max+ V_in) N @ V_out) V_f) I_peak

@

Ǹ

(eq. 3)

2

DI_L

I_peak²* I_peak@ DI_L)

_{d @}ǒ

Ǹ

Ǔ

I_d,rms

+

where L is the leakage inductance, C the total

f

tot

3

capacitance at the drain node (which is increased by

the capacitor you will wire between drain and

0.0928²

3

2

_{0.44 @}ǒ_{0.158 * 0.158 @ 0.0928 )}

Ǔ

Ǹ

source), N the N :N turn ratio, V the output

P

S

out

voltage, V the secondary diode forward drop and

f

+ 57 mA

finally, I

the maximum peak current. Worse case

peak

If we take the maximum R

junction temperature, i.e. 34 W, then conduction

for a 125°C

occurs when the SMPS is very close to regulation,

e.g. the V target is almost reached and I is still

DS(on)

out

peak

losses worse case are:

P_cond+ I_d,rms²@ R_DS(on)+ 110 mW

pushed to the maximum. For this design, we have

selected our maximum voltage around 650 V (at V

= 375 Vdc). This voltage is given by the RCD clamp

installed from the drain to the bulk voltage. We will

see how to calculate it later on.

in

7. Off−time and on−time switching losses can be

estimated based on the following calculations:

4. Calculate the maximum operating duty−cycle for

this flyback converter operated in CCM:

ǒ

Ǔ

I_peak@ V_bulk) V_clamp@ t_off

(eq. 6)

P_off

+

2T_SW

ǒ

Ǔ

N @ V_out@ V_f

(

)

0.158 @ 127 ) 100 @ 2 @ 10n

d_max

+

ǒ

Ǔ

N @ V_out@ V_f) V_in,min

2 @ 16.7 m

(eq. 4)

1

+ 15.5 mW

+ 0.44

V_in,min

Where, assume the V

voltage.

is equal to 2 times of reflected

1 )

clamp

N@(V_out@V_f)

5. To obtain the primary inductance, we have the

choice between two equations:

ǒ

Ǔ²

V_in@ d

f_sw@ K @ P_in

(eq. 5)

L +

www.onsemi.com

26

NCP1060, NCP1063

9. If the NCP106X operates at DSS mode, then the

ǒ

Ǔ

I_valley@ V_bulk) N @ (V_out) V_f) @ t_on

(eq. 7)

P_on

+

losses caused by DSS mode should be counted as

losses of this device on the following calculation:

6 @ T_SW

0.0464 @ (127 ) 100) @ 10 n

6 @ 16.7 m

P_DSS+ I_CC1@ V_in.max+ 0.8m @ 375 + 300 mW

(eq. 8)

+ 2.1 mW

MOSFET Protection

It is noted that the overlap of voltage and current seen on

MOSFET during turning on and off duration is dependent on

the snubber and parasitic capacitance seen from drain pin.

As in any Flyback design, it is important to limit the drain

excursion to a safe value, e.g. below the MOSFET BVdss

which is 700 V. Figure 48 a−b−c present possible

implementations:

Therefore the t and t in Equation 7 and Equation 8 have

off

on

to be modified after measuring on the bench.

8. The theoretical total power is then

117 + 15.5 + 2.1 = 127.6 mW

Figure 48. a, b, c : Different Options to Clamp the Leakage Spike

Figure 48a: the simple capacitor limits the voltage

according to the lateral MOSFET body−diode shall never be

forward biased, either during start−up (because of a large

leakage inductance) or in normal operation as shown by

Figure 46. This condition sets the maximum voltage that can

a MUR160 represents a good choice. One major drawback

of the RCD network lies in its dependency upon the peak

current. Worse case occurs when I

and V are maximum

peak

in

and V is close to reach the steady−state value.

out

Figure 48c: this option is probably the most expensive of

all three but it offers the best protection degree. If you need

a very precise clamping level, you must implement a zener

diode or a TVS. There are little technology differences

behind a standard zener diode and a TVS. However, the die

area is far bigger for a transient suppressor than that of zener.

A 5 W zener diode like the 1N5388B will accept 180 W peak

power if it lasts less than 8.3 ms. If the peak current in the

worse case (e.g. when the PWM circuit maximum current

limit works) multiplied by the nominal zener voltage

exceeds these 180 W, then the diode will be destroyed when

the supply experiences overloads. A transient suppressor

like the P6KE200 still dissipates 5 W of continuous power

but is able to accept surges up to 600 W @ 1 ms. Select the

zener or TVS clamping level between 40 to 80 volts above the

reflected output voltage when the supply is heavily loaded.

As a good design practice, it is recommended to

implement one of this protection to make sure Drain pin

voltage doesn’t go above 650 V (to have some margin

between Drain pin voltage and BVdss) during most stringent

operating conditions (high Vin and peak power).

be reflected during t . As a result, the flyback voltage

off

which is reflected on the drain at the switch opening cannot

be larger than the input voltage. When selecting

components, you must adopt a turn ratio which adheres to

the following Equation 3. This option is only valid for low

power applications, e.g. below 5 W, otherwise chances exist

to destroy the MOSFET. After evaluating the leakage

inductance, you can compute C with (Equation 4). Typical

values are between 100 pF and up to 470 pF. Large

capacitors increase capacitive losses...

Figure 48b: the most standard circuitry is called the RCD

network. You calculate R

following formulae:

and C

using the

clamp

ǒ

_{) V )}Ǔ

2 @ V_clamp@ V_clamp) N @ (V_out

f

R_clamp

C_clamp

+

(eq. 9)

L_leak@ I_leak²@ f_sw

V_clamp

V_ripple@ f_sw@ R_clamp

V

clamp

is usually selected 50−80 V above the reflected

value N x (V + V ). The diode needs to be a fast one and

out

f

www.onsemi.com

27

NCP1060, NCP1063

Power Dissipation and Heatsinking

T_Jmax* T_ambmax

The NCP106X welcomes two dissipating terms, the DSS

P_max

+

(eq. 10)

current−source (when active) and the MOSFET. Thus, P

R_qJA

tot

= P

+ P

. It is mandatory to properly manage the

DSS

MOSFET

which gives around 870 mW for an ambient of 50°C and a

maximum junction of 150°C. If the surface is not large

heat generated by losses. If no precaution is taken, risks exist

to trigger the internal thermal shutdown (TSD). To help

dissipating the heat, the PCB designer must foresee large

copper areas around the package. Take the PDIP−7 package

as an example, when surrounded by a surface approximately

enough, the R

is growing and the maximum power the

θJA

device can evacuate decreases. Figure 49 gives a possible

layout to help drop the thermal resistance.

2

200 mm of 35 mm copper, the maximum power the device

can thus evacuate is:

Figure 49. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient

Bill of material:

C1

Bulk capacitor, input DC voltage is connected to the capacitor

C2, R1, D1

C3

Clamping elements

Vcc capacitor

OK1

Optocoupler

R2

Resistor to setting I

current

PEAK

Table 5. ORDERING INFORMATION

Device

Frequency

60 kHz

R

Brown In

Yes

Package Type

Shipping

DS(on)

NCP1060AP060G

NCP1060AP100G

NCP1060AD060R2G

NCP1060AD100R2G

NCP1060BD060R2G

NCP1060BD100R2G

NCP1063AP060G

NCP1063AP100G

NCP1063AD060R2G

NCP1063AD100R2G

34

50 Units / Rail

PDIP−7

(Pb−Free)

100 kHz

60 kHz

34

Yes

50 Units / Rail

Yes

2500 / Tape & Reel

50 Units / Rail

100 kHz

60 kHz

34

Yes

SOIC−10

(Pb−Free)

34

No

100 kHz

60 kHz

34

No

11.4

Yes

PDIP−7

(Pb−Free)

100 kHz

60 kHz

Yes

50 Units / Rail

Yes

2500 / Tape & Reel

SOIC−16

(Pb−Free)

100 kHz

Yes

www.onsemi.com

28

NCP1060, NCP1063

PACKAGE DIMENSIONS

PDIP−7 (PDIP−8 LESS PIN 6)

CASE 626A

ISSUE B

NOTES:

D

A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

E

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-

AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.

4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH

OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE

NOT TO EXCEED 0.10 INCH.

5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM

PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR

TO DATUM C.

H

8

5

4

E1

1

6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE

LEADS UNCONSTRAINED.

7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE

LEADS, WHERE THE LEADS EXIT THE BODY.

8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE

CORNERS).

NOTE 8

c

b2

B

END VIEW

WITH LEADS CONSTRAINED

NOTE 5

TOP VIEW

INCHES

DIM MIN MAX

−−−−

A1 0.015

MILLIMETERS

A2

MIN

−−−

0.38

2.92

0.35

MAX

5.33

−−−

4.95

0.56

e/2

A

0.210

−−−−

A

NOTE 3

A2 0.115 0.195

L

b

b2

C

0.014 0.022

0.060 TYP

0.008 0.014

0.355 0.400

1.52 TYP

0.20

9.02

0.13

7.62

6.10

0.36

10.16

−−−

8.26

7.11

D

SEATING

PLANE

D1 0.005

0.300 0.325

E1 0.240 0.280

−−−−

A1

D1

E

C

M

e

eB

L

0.100 BSC

−−−− 0.430

0.115 0.150

−−−− 10°

2.54 BSC

−−−

2.92

−−−

10.92

3.81

10 °

e

eB

8X

b

END VIEW

M

NOTE 6

M

B

0.010

C A

SIDE VIEW

www.onsemi.com

29

NCP1060, NCP1063

PACKAGE DIMENSIONS

SOIC−10 NB

CASE 751BQ

ISSUE B

2X

NOTES:

0.10

C

A-B

0.10

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’

AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15mm

PER SIDE. DIMENSIONS D AND E ARE DE-

TERMINED AT DATUM F.

D

H

A

2X

C

A-B

F

10

6

E

1

5. DIMENSIONS A AND B ARE TO BE DETERM-

INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

5

L2

A3

SEATING

PLANE

L

C

0.20

C

10X b

DETAIL A

B

2X 5 TIPS

M

MILLIMETERS

0.25

C A-B D

DIM MIN

MAX

1.75

0.25

0.51

5.00

4.00

TOP VIEW

A

A1

A3

b

1.25

0.10

0.17

0.31

4.80

3.80

10X

h

X 45

_

0.10

C

0.10

C

D

E

M

e

1.00 BSC

H

5.80

6.20

h

L

L2

M

0.37 REF

A

0.40

0.80

DETAIL A

e

SIDE VIEW

A1

SEATING

PLANE

0.25 BSC

C

0

8

_

END VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

1.00

PITCH

10X

0.58

6.50

1

10X

1.18

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

30

NCP1060, NCP1063

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

−A−

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16

9

8

−B−

P 8 PL

M

S

B

0.25 (0.010)

1

MILLIMETERS

INCHES

MIN

0.386

DIM MIN

MAX

0.393

0.157

0.068

0.019

0.049

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00

G

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

F

R X 45

K

_

G

J

1.27 BSC

0.050 BSC

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

K

M

P

R

C

7

0

_

−T−

SEATING

PLANE

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

J

M

D

16 PL

M

S

A

0.25 (0.010)

T B

SOLDERING FOOTPRINT

8X

6.40

16X

1.12

1

16

16X

0.58

1.27

PITCH

8

9

DIMENSIONS: MILLIMETERS

ON Semiconductor and the

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed

at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation

or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets

and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each

customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,

or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which

the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or

unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable

copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

NCP1060/D

www.onsemi.com

31


型号：	NCP1060_16
厂家：	ONSEMI
描述：	High-Voltage Switcher for Low Power Offline SMPS
文件：	总31页 (文件大小：390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCP1060_16 [ONSEMI]

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