NCL30486A2DR2G [ONSEMI]
Smart-Dimmable CC/CV PSR Controller;型号: | NCL30486A2DR2G |
厂家: | ONSEMI |
描述: | Smart-Dimmable CC/CV PSR Controller |
文件: | 总29页 (文件大小:365K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dimmable Power Factor
Corrected LED Driver
NCL30486
The NCL30486 is a power factor corrected flyback controller
targeting isolated constant current LED drivers. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to tightly regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, its biasing and for an
optocoupler.
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9
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact space
efficient designs and supports analog and digital dimming with two
dedicated dimming inputs control ideal for Smart LED Lighting
applications.
1
SOIC−9
CASE 751BP
MARKING
DIAGRAM
Features
• High Voltage Startup
9
L30486XX
ALYWX
G
• Quasi−resonant Peak Current−mode Control Operation
• Primary Side Feedback
• CC / CV Accurate Control V up to 320 V rms
in
1
• Tight LED Constant Current Regulation of 2% Typical
• Digital Power Factor Correction
L30486
XX
A
= Specific Device Code
= Version
= Assembly Location
= Wafer Lot
= Assembly Start Week
= Pb−Free Package
• Analog and Digital Dimming
• Cycle by Cycle Peak Current Limit
L
YW
G
• Wide Operating V Range
CC
• −40 to + 125°C
• Robust Protection Features
PIN CONNECTIONS
♦ Brown−Out
♦ OVP on V
CC
ADIM
COMP
ZCD
HV
1
10
♦ Constant Voltage / LED Open Circuit Protection
♦ Winding Short Circuit Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Thermal Shutdown
2
PDIM
VCC
DRV
3
4
5
8
7
6
♦ Line over Voltage Protection
CS
• This is a Pb−Free Device
Typical Applications
GND
• Integral LED Bulbs
• LED Power Driver Supplies
• LED Light Engines
ORDERING INFORMATION
See detailed ordering and shipping information on page 27 of
this data sheet.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
May, 2021 − Rev. 2
NCL30486/D
NCL30486
.
.
Aux
.
VADIM
NCL30486
1
2
3
4
5
10
9
8
7
6
PWM signal
Figure 1. Typical Application Schematic for NCL30486
PIN FUNCTION DESCRIPTION NCL30486
Pin N5
1
Pin Name
Function
Pin Description
ADIM
Analog dimming
This pin is used for analog control of the output current. Applying a voltage varying
between V and V will dim the output current from 0% to 100%.
DIM(EN)
DIM100
2
3
COMP
ZCD
OTA output for CV loop
Zero crossing Detection
This pin receives a compensation network to stabilize the constant voltage loop
This pin connects to the auxiliary winding and is used to detect the core reset event.
This pin also senses the auxiliary winding voltage for accurate output voltage control
V
sensing
aux
4
5
6
7
8
CS
Current sense
−
This pin monitors the primary peak current.
The controller ground
GND
DRV
VCC
PDIM
Driver output
Supplies the controller
PWM dimming
The driver’s output to an external MOSFET
This pin is connected to an external auxiliary voltage.
This pin is used for PWM dimming control. An optocoupler can be connected directly
to the pin if the PWM control signal is from the secondary side
9
NC
HV
creepage
10
High Voltage sensing
This pin connects after the diode bridge to provide the startup current and internal
high voltage sensing function.
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2
NCL30486
INTERNAL CIRCUIT ARCHITECTURE
STOP
L_OVP
VCC
COMP
Aux_SCP
Fast_OVP
Enable
Standby
VCV
OFF
Fault
Management
VCC Management
UVLO
Constant Voltage
Control
Slow_OVP
Fast_OVP
Thermal
Shutdown
VCC
OVP
HV
Startup
VCC_OVP
CS_short
HVdiv Slow_OVP
V
VREFX
dimCV_mode
HV
BO_NOK
L_OVP
Brown −Out
Line OVP
Zero crossing detection Logic
(ZCD blanking, Time−Out, …)
ZCD
Valley Selection
Frequency foldback
Aux . Winding Short Circuit Prot
.
Aux_SCP
VHVdiv
Q_drv
Q_drv
VHVdiv
Line
feed−forward
S
R
Q
Q
VDIMA
V
Standby
HVdiv dc_DIM
DRV
Driver
and
Clamp
Enable
STOP
CS
VREFX
Leading
Edge
Blanking
Power factor and
Constant −current control
CS_reset
Ipk_max
Maximum
on−time
Max. Peak
Current Limit
STOP
Winding
Output diode
SCP
/
WOD_SCP
CS_short
ADIM
PDIM
Analog
Dimming
VDIMA
dimCV_mode
Enable
CS Short
Protection
GND
PWM
Dimming
dc_DIM
dimCV_mode
Figure 2. Internal Circuit Architecture NCL30486
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3
NCL30486
MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
V
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3 to 30
Internally limited
V
mA
CC(MAX)
CC(MAX)
I
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
mA
DRV(MAX)
DRV(MAX)
DRV
I
−300, +500
V
Maximum voltage on HV pin
Maximum current for HV pin (dc current self−limited if operated within the allowed range)
−0.3, +700
V
mA
HV(MAX)
HV(MAX)
I
20
V
Maximum voltage on low power pins (except pins DRV and VCC)
Current range for low power pins (except pins DRV and VCC)
−0.3, 5.5 (Note 2)
−2, +5
V
mA
MAX
MAX
I
R
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
210
°C/W
°C
θ
J−A
T
150
J(MAX)
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model except HV pin (Note 3)
ESD Capability, HBM model HV pin
ESD Capability, CDM model (Note 3)
4
1.5
1
kV
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V otherwise.
DRV
DRV(high)
CC
DRV(high) DRV CC
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages
can be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.
Charged Device Model 1000 V per JEDEC Standard JESD22−C101D.
4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, V = 0 V)
CS
J
CC
ZCD
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE SECTION
High voltage current source
High voltage current source
V
V
= V
– 200 mV
I
3.9
−
5.1
300
0.8
17
6.2
−
mA
mA
CC
CC(on)
HV(start2)
I
HV(start1)
= 0 V
CC
V
CC
level for I
to I
transition
V
CC(TH)
−
−
V
HV(start1)
HV(start2)
Minimum startup voltage
HV source leakage current
V
V
= 0 V
V
−
−
V
CC
HV(MIN)
HV(leak)
= 450 V
I
−
4.5
−
10
−
mA
HV
Maximum input voltage (rms) for correct operation of
the PFC loop
V
320
V rms
HV(OL)
SUPPLY SECTION
Supply Voltage
V
Startup Threshold
V
CC
V
CC
V
CC
increasing
decreasing
decreasing
V
V
16
9.3
7.6
4
18
20
10.7
−
CC(on)
CC(off)
Minimum Operating Voltage
10.2
−
Hysteresis V
– V
V
CC(on)
CC(off)
CC(HYS)
CC(reset)
Internal logic reset
V
5
6
Over Voltage Protection
VCC OVP threshold
V
25
26.5
28
V
CC(OVP)
V
V
noise filter (Note 5)
CC(reset)
t
−
−
5
20
−
−
ms
CC(off)
VCC(off)
noise filter (Note 5)
t
VCC(reset)
Supply Current
mA
Device Disabled/Fault
V
> V
I
I
I
I
1.2
–
1.35
3.0
3.5
1.7
1.6
3.5
CC
sw
CC(off)
CC1
CC2
CC3
CC4
Device Enabled/No output load on pin 5
F
= 65 kHz
Device Switching (F = 65 kHz)
C
V
= 470 pF, F = 65 kHz
−
4.0
sw
sw
DRV
sw
Device switching (F = 700 Hz)
v 0.9 V
−
1.88
COMP
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NCL30486
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, V = 0 V)
CS
J
CC
ZCD
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)
J
J
CC
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
CURRENT SENSE
Maximum Internal current limit
V
1.33
283
−
1.40
345
100
1.47
407
150
V
ILIM
LEB
ILIM
Leading Edge Blanking Duration for V
t
ns
ns
ILIM
Propagation delay from current detection to gate
off−state
t
Maximum on−time (option 1)
Maximum on−time (option 2)
t
t
29
16
39
20
49
24
ms
ms
V
on(MAX)
on(MAX)
Threshold for immediate fault protection activation
(140% of V
V
1.9
2.0
2.1
CS(stop)
)
ILIM
Leading Edge Blanking Duration for V
t
−
170
500
60
−
ns
mA
CS(stop)
BCS
Current source for CS to GND short detection
I
400
20
600
90
CS(short)
Current sense threshold for CS to GND short
detection
V
CS
rising
V
mV
CS(low)
GATE DRIVE
Drive Resistance
DRV Sink
DRV Source
W
R
SNK
R
SRC
−
−
13
30
−
−
Drive current capability
DRV Sink (Note GBD)
DRV Source (Note GBD)
mA
I
−
−
500
300
−
−
SNK
SRC
I
Rise Time (10% to 90%)
Fall Time (90 %to 10%)
DRV Low Voltage
C
C
= 470 pF
= 470 pF
t
–
–
8
30
20
–
−
−
−
ns
ns
V
DRV
DRV
CC
r
t
f
V
C
= V +0.2 V
CC(off)
V
DRV(low)
= 470 pF, R
= 33 kW
DRV
DRV
DRV High Voltage
V
= V
DRV
V
10
12
14
V
CC
CC(MAX)
DRV(high)
C
= 470 pF, R
= 33 kW
DRV
ZERO VOLTAGE DETECTION CIRCUIT
Upper ZCD threshold voltage
V
V
rising
falling
V
−
35
−
90
55
0.7
−
150
−
mV
mV
V
ZCD
ZCD(rising)
V
ZCD(falling)
Lower ZCD threshold voltage
ZCD
Threshold to force V
ZCD hysteresis
maximum during startup
V
−
REFX
ZCD(start)
ZCD(HYS)
ZCD(DEM)
V
15
−
−
mV
ns
Propagation Delay from valley detection to DRV high
(no t
V
ZCD
decreasing
t
−
150
)
LEB4
Additional delay from valley lockout output to DRV
latch set (prog option)
t
125
250
375
ns
LEB4
Equivalent time constant for ZCD input (GBD)
Blanking delay after on−time (option 1)
Blanking delay after on−time (option 2)
Blanking Delay at light load (option 1)
Blanking Delay at light load (option 2)
Timeout after last DEMAG transition
Pulling−down resistor
t
−
1.1
0.75
0.6
0.45
5
20
1.5
1.0
0.8
0.6
6.5
200
170
−
1.9
1.25
1.0
0.75
8
ns
ms
ms
ms
ms
ms
kW
mA
PAR
V
V
V
V
> 0.35 V
> 0.35 V
< 0.25 V
< 0.25 V
t
t
t
t
REFX
REFX
REFX
REFX
ZCD(blank1)
ZCD(blank1)
ZCD(blank2)
ZCD(blank2)
t
TIMO
V
ZCD
= V
R
−
−
ZCD(falling)
ZCD(pd)
ZCDdim
ZCD pin current source for forcing CV mode when
minimum dimming
V
ADIM
= 0.5 V
I
145
195
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NCL30486
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, V = 0 V)
CS
J
CC
ZCD
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)
J
J
CC
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
CONSTANT CURRENT CONTROL
Reference Voltage
T = 25°C − 85°C
V
V
327.9 334.2 341.2
mV
mV
mV
mV
mV
mV
mV
j
REF/3
Reference Voltage
T = −40°C to 125°C
j
324
30
334.2
346
REF/3
10% Reference Voltage
10% Reference Voltage
5% Reference Voltage
5% Reference Voltage
T = 25°C − 85°C
j
V
V
V
V
33.33 36.66
REF10/3
REF10/3
REF05/3
REF05/3
T = −40°C to 125°C
j
27.33 33.33 39.33
T = 25°C − 85°C
j
14.17
13.34
20
17
17
50
19.17
20
T = −40°C to 125°C
j
Current sense lower threshold for detection of the
leakage inductance reset time
V
CS
falling
V
100
CS(low)
Blanking time for leakage inductance reset detection
t
−
120
−
ns
CS(low)
POWER FACTOR CORRECTION
Clamping value for V
T = 0°C to 125°C
V
REF(PFC)CLP
2.06
−
2.2
240
230
2.34
−
V
REF(PFC)
J
Line range detector for PFC loop
Line range detector for PFC loop
CONSTANT VOLTAGE SECTION
V
HV
HV
increases
decreases
V
Vdc
Vdc
HL(PFC)
V
V
−
−
LL(PFC)
Internal voltage reference for constant voltage
regulation
V
3.41
3.52
3.63
V
REF(CV)
CV Error amplifier Gain
G
40
−
50
60
60
−
mS
mA
V
EA
Error amplifier current capability
COMP pin lower clamp voltage
COMP pin higher clamp voltage
COMP pin higher clamp voltage
V
= V
(no dimming)
I
EA
REFX
REF
V
−
0.6
−
CV(clampL)
CV(clampH)
CV(clampH)
T = 0°C to 125°C
J
V
4.05
4.01
4.12
4.12
4.25
4.25
V
T = −40°C to 125°C
J
V
V
Internal ZCD voltage below which the CV OTA is
boosted
V
* 85%
V
2.796 2.975 3.154
V
REF(CV)
boost(CV)
Threshold for releasing the CV boost
V
V
* 90%
* 80%
V
2.96
3.15
2.8
3.34
V
V
REF(CV)
boost(CV)RST
Internal ZCD voltage below which the CV OTA is
boosted (opt.2)
V
2.632
2.968
REF(CV)
boost(CV)2
Error amplifier current capability during boost phase
I
−
140
−
mA
V
EAboost
st
ZCD OVP 1 level (slow OVP) option 1
V
V
V
V
* 115%
* 120%
* 105%
* 110%
V
V
3.783 4.025 4.267
REF(CV)
REF(CV)
REF(CV)
REF(CV)
OVP1
st
ZCD OVP 1 level (slow OVP) option 2
3.948
4.2
3.675
3.85
1.5
4.452
V
OVP1
ZCD voltage at which slow OVP is exit (option 1)
ZCD voltage at which slow OVP is exit (option 2)
Switching period during slow OVP
ZCD fast OVP option 2
V
−
−
−
−
−
−
−
−
V
OVP1rst
OVP1rst
V
V
T
ms
V
sw(OVP1)
V
V
* 130% + 150 mV
* 125% + 150 mV
V
V
4.7
ref(CV)
OVP2
OVP2
ZCD fast OVP option 1
4.253 4.525 4.797
V
ref(CV)
Number of switching cycles before fast OVP
confirmation
T
−
−
−
4
−
−
−
OVP2_CNT
Duration for disabling DRV pulses during ZCD fast
OVP
T
4
s
recovery
COMP pin internal pullup resistor (prog option)
R
15
kW
pullup
LINE FEED FORWARD
V
to I
conversion ratio
K
0.189
76
0.21
95
0.231 mA/V
HV
CS(offset)
LFF
Offset current maximum value
V
> (450 V or 500 V)
I
114
45
mA
mA
HV
offset(MAX)
Line feed−forward current
DRV high, V = 200 V
I
35
40
HV
FF
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NCL30486
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, V = 0 V)
CS
J
CC
ZCD
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)
J
J
CC
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
VALLEY LOCKOUT SECTION
Threshold for line range detection V increasing
V
V
increases
decreases
V
HL
228
240
252
V
HV
> 80% V
HV
st
nd
(1 to 2 valley transition for V
)
REFX
REF
st
rd
(prog. option: 1 to 3 valley transition)
Threshold for line range detection V decreasing
V
LL
218
15
230
25
242
35
V
HV
REFX
HV
nd
st
(2 to 1 valley transition for V
> 80% V
)
REF
rd
st
(prog. option: 3 to 1 valley transition)
Blanking time for line range detection
Valley thresholds
t
ms
V
HL(blank)
st
nd
nd
rd
1
to 2 valley transition at LL and 2 to 3 valley
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
decreases
increases
decreases
increases
decreases
increases
decreases
increases
V
V
V
V
V
V
V
V
−
−
−
−
−
−
−
−
0.80
0.90
0.65
0.75
0.50
0.60
0.35
0.45
−
−
−
−
−
−
−
−
VLY1−2/2−3
VLY2−1/3−2
VLY2−3/3−4
VLY3−2/4−3
VLY3−4/4−5
VLY4−3/5−4
VLY4−5/5−6
VLY5−4/6−5
rd
th
HL, V
decr. (prog. option: 3 to 4 valley HL)
REF
nd
st
rd
nd
2
to 1 valley transition at LL and 3 to 2 valley
th
rd
HL, V
incr. (prog. option: 4 to 3 valley HL)
REF
nd
rd
rd
th
2
to 3 valley transition at LL and 3 to 4 valley
th
th
HL, V
decr. (prog. option: 4 to 5 valley HL)
REF
rd
nd
th
rd
3
to 2 valley transition at LL and 4 to 3 valley
th
th
HL, V
incr. (prog. option: 5 to 4 valley HL)
REF
rd
th
th
th
th
th
3
to 4 valley transition at LL and 4 to 5 valley
th
HL, V
decr. (prog. option: 5 to 6 valley HL)
REF
th
th
th
4
to 3 valley transition at LL and 5 to 4 valley
th
th
HL, V
incr. (prog. option: 6 to 5 valley HL)
REF
th
th
th
th
th
th
4
to 5 valley transition at LL and 5 to 6 valley
th
HL, V
decr. (prog. option: 6 to 7 valley HL)
REF
th
th
th
5
to 4 valley transition at LL and 6 to 5 valley
th
th
HL, V
incr. (prog. option: 7 to 6 valley HL)
REF
V
REF
V
REF
value at which the FF mode is activated
value at which the FF mode is removed
V
V
decreases
increases
V
V
−
−
0.25
0.35
−
−
V
V
REF
FFstart
REF
FFstop
FREQUENCY FOLDBACK
Added dead time
V
REFX
V
REFX
V
REFX
V
REFX
= 0.25 V
= 0.08 V
< 3 mV
t
0.8
−
1.0
40
1.2
−
ms
ms
ms
ms
FF1LL
Added dead time
t
FFchg
Dead−time clamp ( option 1)
t
−
675
250
−
FFend1
FFend2
Dead−time clamp ( option 2)
< 11.2 mV
t
−
−
DIMMING SECTION
DIM pin voltage for zero output current (OFF voltage)
ADIM pin voltage for 1% reference voltage
Minimum dimming level (option 1)
Minimum dimming level (option 2)
Minimum dimming level (option 3)
Minimum dimming level (option 4)
ADIM pin voltage for maximum output current
V
0.475
0.5
0.7
0
0.525
V
V
ADIM(EN)
V
0.668
0.732
ADIM(MIN)
K
−
−
−
−
−
−
−
%
%
%
%
V
DIM(MIN)1
DIM(MIN)2
DIM(MIN)3
DIM(MIN)4
K
1
K
K
5
−
8
−
V
3.0
3.1
ADIM100
(V
= 1 V)
REFX
Dimming range
V
−
−
2.3
6.8
10
70
153
1080
3
−
−
V
V
ADIM(range)
Clamping voltage for DIM pin
V
ADIM(CLP)
Dimming pin pull−up current source
Current Comparator threshold for PDIM
Current Comparator threshold for PDIM
Cascode current limit for PDIM
PDIM pin voltage
I
8
12
80
175
−
mA
mA
mA
mA
V
ADIM(pullup)1
I
I
rising
falling
I
I
60
131
−
PDIM
PDIM(THR)
PDIM
PDIM(THD)
I
PDIM(LIM)
V
PDIM
−
−
Maximum period of the PWM dimming signal
Minimum on−time for PWM signal applied on PDIM
−
6
−
ms
ms
−
8
−
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7
NCL30486
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, V = 0 V)
CS
J
CC
ZCD
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)
J
J
CC
Parameter
Test Condition
Symbol
Min
Typ
Max
Unit
FAULT PROTECTION
Thermal Shutdown (Note 5)
Device switching (F
around 65 kHz)
T
130
150
20
170
°C
SW
SHDN
Thermal Shutdown Hysteresis
T
−
–
°C
SHDN(HYS)
Threshold voltage for output short circuit or aux.
winding short circuit detection
V
0.6
0.65
0.7
V
ZCD(short)
Short circuit detection Timer
V
ZCD
< V
t
OVLD
70
3
90
4
110
5
ms
s
ZCD(short)
Auto−recovery Timer
t
recovery
Line OVP threshold
V
V
increasing
decreasing
V
457
430
15
469
443
25
485
465
35
Vdc
Vdc
ms
HV
HV(OVP)
HV pin voltage at which Line OVP is reset
Blanking time for line OVP reset
V
HV(OVP)RST
HV
T
LOVP(blank)
BROWN−OUT AND LINE SENSING
Brown−Out ON level (IC start pulsing)
Brown−Out ON level (IC start pulsing) option 2
Brown−Out OFF level (IC stops pulsing)
Brown−Out OFF level (IC stops pulsing) option 2
V
V
V
V
V
increasing
increasing
decreasing
decreasing
V
101.5
129.7
92
108
138
98
114.5
146.3
104
137
−
Vdc
Vdc
Vdc
Vdc
V
HV
HV
HV
HV
HV
HVBO(on)
V
HVBO(on)2
V
HVBO(off)
V
121
−
129
55
HVBO(off)2
HV pin voltage above which the sampling of ZCD is
enabled low line
decreasing, low line
decreasing, highline
increasing
V
sampENLL
HV pin voltage above which the sampling of ZCD is
enabled highline
V
V
V
−
105
−
V
HV
sampENHL
ZCD sampling enable comparator hysteresis
BO comparators delay
V
−
−
5
−
−
V
HV
sampHYS
BO(delay)
BO(blank)
t
t
30
25
ms
ms
Brown−Out blanking time
15
35
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by design.
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8
NCL30486
TYPICAL CHARACTERISTICS
5,4
5,3
5,2
5,1
5
309
304
299
294
289
284
4,9
4,8
4,7
4,6
4,5
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. IHV(start2) vs. Temperature
Figure 4. IHV(start1) vs. Temperature
361
359
357
355
353
351
349
18,34
18,29
18,24
18,19
18,14
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. VHV(OL) vs. Temperature
Figure 6. VCC(on) vs. Temperature
10,25
10,23
10,21
10,19
10,17
10,15
10,13
10,11
26,96
26,91
26,86
26,81
26,76
26,71
26,66
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. VCC(off) vs. Temperature
Figure 8. VCC(OVP) vs. Temperature
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NCL30486
TYPICAL CHARACTERISTICS (continued)
1,7
1,69
1,68
1,67
1,66
1,65
1,64
1,63
1,62
1,41
1,39
1,37
1,35
1,33
1,31
1,29
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. ICC1 vs. Temperature
Figure 10. ICC4 vs. Temperature
1.404
1.402
1.400
1.398
1.396
54
53,5
53
52,5
52
1.394
1.392
1.390
1.388
1.386
51,5
51
50,5
50
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. VILIM vs. Temperature
Figure 12. VCS(low)F vs. Temperature
2,06
2,04
2,02
2
20,24
20,19
20,14
20,09
20,04
19,99
19,94
19,89
19,84
1,98
1,96
1,94
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. VCS(stop) vs. Temperature
Figure 14. ton(MAX)2 vs. Temperature
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10
NCL30486
TYPICAL CHARACTERISTICS (continued)
359
354
349
344
339
334
180
179
178
177
176
175
174
173
172
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. tLEB vs. Temperature
Figure 16. tBCS vs. Temperature
120
110
100
90
10,5
9,5
8,5
7,5
6,5
5,5
4,5
3,5
80
70
60
50
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. tILIM vs. Temperature
Figure 18. RSNK vs. Temperature
34
32
30
28
26
24
22
20
15,5
13,5
11,5
9,5
7,5
5,5
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. RSRC vs. Temperature
Figure 20. tr vs. Temperature
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11
NCL30486
TYPICAL CHARACTERISTICS (continued)
21,5
20,5
19,5
18,5
17,5
16,5
15,5
14,5
13,5
12,5
83
82,5
82
81,5
81
80,5
80
79,5
79
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. tf vs. Temperature
Figure 22. VZCD(rising) vs. Temperature
0,672
0,67
54,5
53,5
52,5
51,5
50,5
49,5
0,668
0,666
0,664
0,662
0,66
0,658
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. VZCD(falling) vs. Temperature
Figure 24. VZCD(short) vs. Temperature
116
111
106
101
96
1,605
1,595
1,585
1,575
1,565
1,555
91
86
81
76
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. tZCD(dem) vs. Temperature
Figure 26. tZCD(blank1)OPN1 vs. Temperature
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12
NCL30486
TYPICAL CHARACTERISTICS (continued)
0,861
0,856
0,851
0,846
0,841
0,836
1,072
1,067
1,062
1,057
1,052
1,047
1,042
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. tZCD(blank1)OPN2 vs. Temperature
Figure 28. tZCD(blank2)OPN1 vs. Temperature
0,584
0,579
0,574
0,569
0,564
6,92
6,87
6,82
6,77
6,72
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29. tZCD(blank2)OPN2 vs. Temperature
Figure 30. tTIMO vs. Temperature
336,8
336,3
335,8
335,3
334,8
334,3
333,8
333,3
332,8
332,3
331,8
34,6
34,1
33,6
33,1
32,6
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 31. VREF/3 vs. Temperature
Figure 32. VREF10/3 vs. Temperature
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13
NCL30486
TYPICAL CHARACTERISTICS (continued)
3,545
3,535
3,525
3,515
3,505
3,495
3,485
3,475
17,7
17,5
17,3
17,1
16,9
16,7
16,5
16,3
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 33. VREF5/3 vs. Temperature
Figure 34. VREF(CV) vs. Temperature
4,15
4,14
4,13
4,12
4,11
4,1
4,075
4,065
4,055
4,045
4,035
4,025
4,015
4,005
3,995
4,09
4,08
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 35. VCV(clampH) vs. Temperature
Figure 36. VOVP1 vs. Temperature
0,2095
0,2085
0,2075
0,2065
0,2055
0,2045
0,2035
0,2025
0,2015
0,2005
4,54
4,53
4,52
4,51
4,5
4,49
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 37. VOVP2 vs. Temperature
Figure 38. KLFF vs. Temperature
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NCL30486
TYPICAL CHARACTERISTICS (continued)
104
103
102
101
100
99
41,7
41,5
41,3
41,1
40,9
40,7
40,5
40,3
40,1
98
97
96
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 39. Ioffset(MAX) vs. Temperature
Figure 40. IFF vs. Temperature
1,0395
1,0385
1,0375
1,0365
1,0355
1,0345
1,0335
1,0325
1,0315
1,0305
2,208
2,203
2,198
2,193
2,188
2,183
2,178
2,173
2,168
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 41. tFF1LL vs. Temperature
Figure 42. VREF(PFC)CLP vs. Temperature
0,708
0,706
0,704
0,702
0,7
0,5055
0,5045
0,5035
0,5025
0,5015
0,5005
0,4995
0,4985
0,4975
0,698
0,696
0,694
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 43. VADIM(EN) vs. Temperature
Figure 44. VADIM(MIN) vs. Temperature
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NCL30486
TYPICAL CHARACTERISTICS (continued)
71,6
71,1
70,6
70,1
69,6
153,2
152,7
152,2
151,7
151,2
150,7
150,2
149,7
149,2
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 45. IPDIM(THR) vs. Temperature
Figure 46. IPDIM(THD) vs. Temperature
3,013
3,008
3,003
2,998
2,993
2,988
2,983
2,978
1,086
1,081
1,076
1,071
1,066
1,061
1,056
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 47. IPDIM(LIM) vs. Temperature
Figure 48. VPDIM vs. Temperature
108,9
108,7
108,5
108,3
108,1
107,9
107,7
107,5
107,3
107,1
106,9
3,011
3,006
3,001
2,996
2,991
2,986
2,981
2,976
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 49. VADIM100 vs. Temperature
Figure 50. VHVBO(on)ONP1 vs. Temperature
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NCL30486
TYPICAL CHARACTERISTICS (continued)
99,6
99,4
99,2
99
472
471
470
469
468
467
466
465
464
98,8
98,6
98,4
98,2
98
97,8
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 51. VHVBO(off)ONP1 vs. Temperature
Figure 52. VHV(OVP) vs. Temperature
446
445
444
443
442
441
440
439
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 53. VHV(OVP)RST vs. Temperature
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17
NCL30486
Application Information
if V reaches 1.5 x V
(after a reduced LEB of t ).
BCS
CS
ILIM
The NCL30486 implements a current−mode architecture
operating in quasi−resonant mode. Thanks to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current and voltage of the fly−back converter
without using any opto−coupler or measuring directly the
secondary side current or voltage. The controller provides
near unity power factor correction
This additional comparator is enabled only during the
main LEB duration t , for noise immunity reason.
LEB
• Output Under Voltage Protection: If a too low voltage is
applied on ZCD pin for 90 ms time interval, the
controllers assume that the output or the ZCD pin is
shorted to ground and shutdown. After waiting 4 seconds,
the IC restarts switching.
• Analog Dimming: the ADIM pin is dedicated to analog
dimming. There are several options for the minimum
dimming level. Pulling the pin voltage lower than
• Quasi−Resonance
Current−Mode
Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30486 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to an internal algorithm
control, the controller locks−out in a selected valley and
remains locked until the input voltage or the output
current set point significantly changes.
V
disables the controller.
ADIM(EN)
• PWM dimming: the PDIM pin is dedicated to PWM
dimming. The controller measures the duty ratio of a
signal applied to the pin and reduces the output current
accordingly. If this pin is left open, the controller delivers
the maximum output current. If the pin is pulled down, the
controller is disabled.
• Thermal Shutdown: an internal circuitry disables the gate
drive when the junction temperature exceeds 150°C
(typically). The circuit resumes operation once the
temperature drops below approximately 100°C.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to take into
account the effect of the leakage inductance of the
transformer and allows an accurate control of the
secondary side current regardless of the input voltage and
output load variation.
• Primary Side Constant Voltage Regulation: By
monitoring the auxiliary winding voltage, it is possible to
regulate accurately the output voltage. The output voltage
regulation is typically within 2%.
• Load Transient Compensation: Since PFC has low loop
bandwidth, abrupt changes in the load may cause
excessive over or under−shoot. The slow Over Voltage
Protection contains the output voltage when it tends to
become excessive. In addition, the NCL30486 speeds up
the constant voltage regulation loop when the output
voltage goes below 80% or 85% of its regulation level.
• Power Factor Correction: A proprietary concept allows
achieving high power factor correction and low THD
while keeping accurate constant current and constant
voltage control.
POWER FACTOR AND CONSTANT CURRENT
CONTROL
The NCL30486 embeds an analog/digital block to control
the power factor and regulate the output current by
monitoring the ZCD, CS and HV pin voltages (signals
V
, V
, V ). This circuit generates the current
HV_DIV CS
ZCD
setpoint signal and compares it to the current sense signal to
turn the MOSFET off. The HV pin provides the sinusoidal
reference necessary for shaping the input current. The
obtained current reference is further modulated so that when
averaged over a half line period, it is equal to the output
current reference (V
). The modulation and averaging
REFX
process is made internally by a digital circuit. If the HV pin
properly conveys the sinusoidal shape, power factor will be
close to 1. Also, the Total Harmonic Distortion (THD) will
be low especially if the output voltage ripple is small.
• Line Feed−forward: allows compensating the variation of
the output current caused by the propagation delay.
• V Over Voltage Protection: if the V pin voltage
VREF
(eq. 1)
IOUT
+
CC
CC
2NspRsense
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting pulsing.
Where:
• Fast Over Voltage Protection: If the voltage of ZCD pin
exceeds 130% of its regulation level, the controller shuts
down and waits 4 s before trying to restart.
• Brown−Out: the controller includes a brown−out circuit
which safely stops the controller in case the input voltage
is too low. The device will automatically restart if the line
recovers.
• N is the secondary to primary transformer turns ratio:
sp
N
• R
• V
= N / N
S P
sp
is the current sense resistor
sense
is the output current reference: V
= V
if
REFX
REFX
REF
no dimming
The output current reference (V
) is V
unless the
REFX
REF
constant voltage mode is activated or ADIM pin voltage is
below V or a PWM signal with a duty−cycle below
• Cycle−by−cycle peak current limit: when the current
ADIM(100)
sense voltage exceeds the internal threshold V
, the
ILIM
95% is applied on PDIM.
MOSFET is turned off for the rest of the switching cycle.
• Winding Short−Circuit Protection: an additional
comparator senses the CS signal and stops the controller
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18
NCL30486
PRIMARY SIDE CONSTANT VOLTAGE CONTROL
The auxiliary winding voltage is sampled internally
through the ZCD pin.
A type 2 compensator is needed at the CV OTA output to
stabilize the loop. The COMP pin voltage modify the the
output current internal reference in order to regulate the
output voltage.
A precise internal voltage reference V
voltage target for the CV loop.
sets the
REF(CV)
When V
When V
≥ 4 V, V
= V
.
COMP
COMP
REFX
< 0.9 V, V
REF
The sampled voltage is applied to the negative input of the
constant voltage (CV) operational transconductance
= 0 V.
REFX
amplifier (OTA) and compared to V
.
REFCV
Gm
R
ZCD
ZCDU
V
ZCDsamp
ZCD & signal
sampling
COMP
.
R1
C1
R
OTA
ZCDL
VREF(CV)
C2
Aux.
Figure 54. Constant Voltage Feedback Circuit
Secondary Side Regulation Compatible
The NCL30486 is able to support secondary−side
regulation as well. The controller features an option to
The NCL30486 features a high voltage startup circuit that
allows charging VCC capacitor very fast.
When the power supply is first connected to the mains
outlet, the internal current source is biased and charges up
provide a pullup resistor R
on COMP pin instead of the
pullup
CV OTA output. This allows connecting directly an
optocoupler collector and properly biases it. The internal
the V capacitor. When the voltage on this V capacitor
CC
CC
reaches the V
level, the current source turns off. At this
CC(on)
voltage biasing R
is around 5 V.
time, the controller is only supplied by the V capacitor,
pullup
CC
In secondary side regulation, the slow and fast OVP on
ZCD pin are still active thus providing an additional over
voltage protection. In this case, the ZCD pin resistors should
and the auxiliary supply should take over before V
CC
collapses below V
.
CC(off)
The HV startup circuitry is made of two startup current
levels, I and I . This helps to protect the
be calculated to trigger V
interest.
at the output voltage of
OVP2
HV(start1)
HV(start1)
controller against short−circuit between V and GND. At
CC
power−up, as long as V is below V
, the source
CC
CC(TH)
delivers I
(around 300 mA typical). Then, when
HV(start1)
CV OTA Boost
V
CC
reaches V
, the source smoothly transitions to
CC(TH)
VDD
I
and delivers its nominal value. As a result, in case
HV(start2)
Rpullup
of short−circuit between V and GND occurring at high
CC
line (V = 305 V rms), the maximum power dissipation will
be 431 x 300 m = 130 mW instead of 1.5 W if there was only
one startup current level.
COMP
in
−
+
To speed−up the output voltage rise, the following is
implemented:
VREF(CV)
• The digital OTA output is increased until V
REF(PFC)
. Again, this is to speed−up the
signal reaches V
REFX
control signal rise to their steady state value.
Figure 55. COMP Pin Configuration for Secondary
Side Regulation
• At the beginning of each operating phase of a V cycle,
CC
the digital OTA output is set to 0. Actually, the digital
OTA output is set to 0 in the case of a cold start−up or in
the case of a start−up sequence following an operation
STARTUP PHASE (HV STARTUP)
It is generally requested that the LED driver starts to emit
light in less than 1 s and possibly within 300 ms. It is
challenging since the start−up consists of the time to charge
interruption due to a fault. On the other hand, if the V
CC
hiccups just because the system fails to start−up in one
cycle, the digital OTA output is not reset to ease the
the V capacitor and that necessary to charge the output
V
CC
CC
capacitor until sufficient current flows into the LED string.
This second phase can be particularly long in dimming cases
where the secondary current is a portion of the nominal one.
second (or more) attempt.
www.onsemi.com
19
NCL30486
The application note ANDXXXX gives more details about
strategies to decrease the power dissipation of the HV
startup circuit.
• If the load is shorted, the circuit will operate in hiccup
mode with VCC oscillating between V and V
CC(off)
CC(on)
until the output under voltage protection (UVP) trips.
UVP is triggered if the ZCD pin voltage does not exceed
Cycle−by−Cycle Current Limit
When the current sense voltage exceeds the internal
V
within a 90 ms operation of time. This
ZCD(short)
indicates that the ZCD pin is shorted to ground or that an
excessive load prevents the output voltage from rising.
threshold V , the MOSFET is turned off for the rest of the
ILIM
switching cycle.
HV Startup Power Dissipation
Winding and Output Diode Short−Circuit Protection
In parallel to the cycle−by−cycle sensing of the CS pin,
At high line (305 V rms and above) the power dissipated
by the HV startup in case of fault or when the controller is
disabled with PDIM becomes high. Indeed, in case of fault,
the NCL30486 is directly supplied by the HV rail. When the
controller is disabled with PDIM, the optocoupler collector
current is also supplied by the controller, since the
NCL30486 allows directly connecting the optocoupler
transistor to PDIM pin. Thus, the HV startup circuit also
supplies the optocoupler transistor in case of faults. The
current flowing through the HV startup will heat the
controller. It is highly recommended adding enough copper
another comparator with a reduced LEB (t ) and a
BCS
threshold of (V
= 140% x V
) monitors the CS pin
CS(stop)
ILIM
to detect a winding or an output diode short circuit. The
controller shuts down if it detects 4 consecutives pulses
during which the CS pin voltage exceeds V
CS(stop).
The controller goes into auto−recovery mode.
PWM Dimming
The NCL30486 has a dedicated pin for PWM dimming.
The controller directly measures the duty ratio of a PWM
signal applied to PDIM.
Two counters with a high frequency clock are used for this
purpose. A first counter measure the high state duration of
around the controller to decrease the R
of the controller.
qJA
2
Adding a minimum pad area of 215 mm of 35 mm copper
(1 oz) drops the R to around 120°C/W (no air flow, R
qJA
qJA
measured at ADIM pin)
The PCB layout shown in Figure 56 is a layout example
to achieve low R
the PWM signal (t
) and the second counter measures
on_PDIM
its period (T
). A divider computes (t
/
sw_PDIM
on_PDIM
.
T
) and the result is directly the output current
qJA
sw_PDIM
setpoint (V
set point). A filter is added after the digital
REFX
divider to remove the ripple of the signal. A cascode
configuration on PDIM pin allows decreasing the fall time
of the signal.
Thanks to this circuit, the LED current is controlled in an
analog way, even if a PWM signal is used for dimming. This
allows having a good PF during dimming.
Figure 56. PCD Layout Example
www.onsemi.com
20
NCL30486
VDIM_sec
IPDIM
IPDIM(THD)
IPDIM(THR)
VPDIM_int
Ton
Tsw
Figure 57. PDIM Internal Waveforms
Analog Dimming
The pin ADIM pin allows implementing analog dimming
of the LED light.
Practically, the controller extracts the duty−cycle by
measuring the current inside PDIM pin which is directly the
opto coupler collector current.
If the power supply designer applies an analog signal
If PDIM pin is left open, the controller delivers 100% of
varying from V
to V
to the DIM pin, the
I
. If the pin is pulled down for longer than 25 ms, the
out
DIM(EN)
DIM100
output current will increase or decrease proportionally to the
voltage applied. For V = V , the power supply
controller is disabled.
If the PWM dimming signal is removed during dimming,
the controller delivers 100% of I
The NCL30486 set 100% of output current when the
DIM
DIM100
delivers the maximum output current (V
= 1 V).
.
REFX
out
If a voltage lower than V
is applied to ADIM
ADIM(MIN)
pin, the output current is clamped to the selected dimming
clamp value (see Dimming clamp section below)
duty−cycle of the signal applied on PDIM is above 93%.
www.onsemi.com
21
NCL30486
If a voltage lower than V
is applied to the DIM
NOTE:
ADIM(EN)
pin, the DRV pulses are disabled for controllers without the
dimming CV mode option.
The DIM pin is pulled up internally by a small current
source or resistor. Thus, if the pin is left open, the controller
is able to start.
• Interaction between ADIM and PDIM: if ADIM and
PDIM are both used at the same time, the resulting
dimming set point if a multiplication of V
and the
ADIM
duty−ratio of PDIM signal.
• During dimming, when the “Enable” signal is OK, the
controller starts pulsing after 1 time−out pulse, even if a
higher valley number is selected by V
. This is to
REFX
avoid too long startup time while dimming at low output
current value.
VREF
100% VREF
8% V
REF
5% V
REF
1% VREF
VADIM(EN)
VADIM100
VADIM
VADIM(MIN)
Figure 58. ADIM Pin Dimming Curves
Dimming Clamp
There are 4 options for the dimming clamp:
For smart dimming applications, need to bias the
secondary−side MCU. This can be achieved by clamping
• No dimming clamp
• 1%
• 5%
• 8%
V
REFX
when the dimming setpoint is small.
V
REFX
(%)
100%
8%
5%
1%
0.01 0.05
1.0
0.08
Scaled dimming voltage or
dimming duty−ratio
Figure 59. Dimming Clamp Options
www.onsemi.com
22
NCL30486
Dimming Curves
By default, there is a linear relationship between the
voltage applied on ADIM pin and V setpoint. In the
An internal memory allows selecting a root square
relationship between dimming and V
.
REFX
REFX
same way, there is a linear relationship between the
The square like curve is based on CIE 1931 lightness
formula.
duty−ratio of the signal applied on PDIM and V
REFX
setpoint.
Output Current vs. Dimming
100
90
80
70
60
50
40
30
20
10
0
linear
CIE 1931
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Scaled Dimming Voltage or Dimming Duty Ratio
Figure 60. Dimming Curves
Valley Lockout
is varied during dimming. This limits the frequency
excursion.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line.
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
There is an option to have the valley thresholds
The NCL30486 changes valley as V
the input voltage increases and as the output current setpoint
decreases and as
incremented by 1 at high line for better I control at
REFX
out
305 V rms.
Table 1. VALLEY SELECTION
V
Voltage for Valley Change
HV_DIV
V
REFX
value at which the Controller
V
REFX
Value at Which the Controller
0
−−LL−−
2.3 V
−−HL−−
5 V
Changes Valley (I
Decreasing)
Changes Valley(I
Increasing)
out
out
st
nd rd
100%
100%
80%
1
2
3
4
5
6
(3 )
80%
65%
50%
35%
nd
rd th
2
(4 )
65%
50%
35%
rd
th th
3
(5 )
th
th th
4
(6 )
th
th th
5
(7 )
25%
0%
25%
0%
FF mode
FF mode
0
−−LL−−
2.3 V
−−HL−−
5 V
Internal V
Voltage for Valley Change
HV_DIV
www.onsemi.com
23
NCL30486
Zero Crossing Detection Block
The Time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations.
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the ZCD pin voltage crosses
below the 55 mV internal threshold.
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
the valleys. To avoid such a situation, Optimus Prime
features a Time−Out circuit that generates pulses if the
voltage on ZCD pin stays below the 55 mV threshold for
6.5 ms.
At startup, the output voltage reflected on the auxiliary
winding is low. Because of the ZCD resistor bridge setting
the constant voltage regulation target, the voltage on the
ZCD pin is very low and the ZCD comparator might be
unable to detect the valleys. In this condition, setting the
DRV latch with the 6.5 ms time−out leads to a continuous
conduction mode operation (CCM) at the beginning of the
soft−start. This CCM operation only last a few cycles until
the voltage on ZCD pin becomes high enough and trips the
ZCD comparator.
VZCD
VZCD(th)
low
3
high
14
12
I
decreases or V
in
out
high
increases
ZCD comp
high
low
15
low
TimeOut
16
17
2nd , 3 rd
high
VVIN
increases
Clock
low
Figure 61. Valley Detection and Time−out Chronograms
If the ZCD pin or the auxiliary winding happen to be
shorted the time−out function would normally make the
controller keep switching and hence lead to improper
regulation of the LED current.
The Under Voltage Protection (UVP) is implemented to
avoid these scenarios: a secondary timer starts counting
Slow OVP
If ZCD voltage exceeds V
switching cycles, the controller stops switching during
1.4 ms. The PFC loop is not reset. After 1.4 ms, the
controller initiates a new DRV pulse to refresh ZCD
for 4 consecutive
OVP1
sampling voltage. If V
is still too high (V
> 110%
ZCD
ZCD
when the ZCD voltage is below the V
threshold. If
V
), the controller continues to switch with a 1.4 ms
ZCD(short)
REF(CV)
this timer reaches 90 ms, the controller detects a fault and
enters the auto−recovery fault mode.
period. The controller resumes its normal operation when
< 110% V
V
ZCD
.
REF(CV)
During slow OVP, the peak current setpoint is COMP pin
voltage scaled down by a fixed ratio.
ZCD Over Voltage Protection
Because of the power factor correction, it is necessary to
set the crossover frequency of the CV loop very low (target
10 Hz, depending on power stage phase shift). Because the
loop is slow, the output voltage can reach high value during
startup or during an output load step. It is necessary to limit
the output voltage excursion. For this, the NCL30486
features a slow OVP and a fast OVP on ZCD pin.
Fast OVP
If ZCD voltage exceeds V
for 4 consecutive switching cycles (slow OVP not triggered)
or for 2 switching cycles if the slow OVP has already been
triggered, the controller detects a fault and starts the
auto−recovery fault mode (cf: Fault Management Section)
(130% of V
)
ZCD(OVP2)
REF(CV)
www.onsemi.com
24
NCL30486
Line Feedforward
HV
v DD
v VS
CS
RLFF
I CS(offset)
K LFF
R sense
Q_drv
+
25 ms
BO_NOK
Blanking
−
1 V / 0.9 V
Figure 62. Line Feed−Forward and Brown−out Schematic
The line voltage is sensed by the HV pin and converted
into a current. By adding an external resistor in series
between the sense resistor and the CS pin, a voltage offset
proportional to the line voltage is added to the CS signal. The
offset is applied only during the MOSFET on−time in order
to not influence the detection of the leakage inductance
reset.
below V
for 25 ms typical. Exiting a brown−out
HVBO(off)
condition overrides the hiccup on V (V does not wait
to reach V
mode.
An option with higher brown−out levels is also available
(see ordering table and electricals parameters)
CC
CC
) and the IC immediately goes into startup
CC(off)
Line OVP
The offset is always applied even at light load in order to
improve the current regulation at low output load.
In order to protect the power supply in case of too high
input voltage, the NCL30486 features a line over voltage
protection. When the voltage on HV pin exceeds V
Brown−out
HV(OVP)
In order to protect the supply against a very low input
voltage, the controller features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
the controller stops switching; V hiccups.
CC
When V becomes lower than V
for more
HV
HV(OVP)RST
than 25 ms, the controller initiates a clean startup sequence
if a voltage higher than V
is applied to the HV pin
and re−starts switching.
HVBO(on)
and shuts−down if the HV pin voltage decreases and stays
www.onsemi.com
25
NCL30486
VHV
VHV(OVP)
VHV(OVP)RST
t LOVP(blank)
VCC
VCC(on)
VCC(off)
VDRV
Iout
Figure 63. Line OVP Chronograms
Protections
The circuit incorporates a large variety of protections to
make the LED driver very rugged.
Among them, we can list:
• Winding or Output Diode Short Circuit protection
The circuit detects this failure when 4 consecutive DRV
pulses occur within which the CS pin voltage exceeds
• Fault of the GND connection
(V
= 140% x V
). In this case, the controller
CS(stop)
ILIM
If the GND pin is properly connected, the supply current
enters auto−recovery mode (4−s operation interruption
drawn from the positive terminal of the V capacitor,
between active bursts).
CC
flows out of the GND pin to return to the negative terminal
• V Over Voltage Protection
CC
of the V capacitor. If the GND pin is not connected, the
CC
The circuit stops generating pulses if the V exceeds
CC
circuit ESD diodes offer another return path. The
accidental non connection of the GND pin can hence be
detected by detecting that one of this ESD diode is
conducting. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 ms, the circuit
stops generating DRV pin.
V
and enters auto−recovery mode. This feature
CC(OVP)
protects the circuit if output LEDs happen to be
disconnected.
• ZCD fast OVP
If ZCD voltage exceeds V
for 4 consecutive
ZCD(OVP2)
switching cycles (slow OVP not triggered) or for 2
switching cycles if the slow OVP has already been
triggered, the controller detects a fault and enters
auto−recovery mode (4 s operation interruption between
active bursts).
• Output short circuit situation (Output Under Voltage
Protection)
Overload is detected by monitoring the ZCD pin voltage:
if it remains below V
for 90 ms, an output short
ZCD(short)
circuit is detected and the circuit stops generating pulses
for 4 s. When this 4 s delay has elapsed, the circuit
attempts to restart.
• Die Over Temperature (TSD)
The circuit stops operating if the junction temperature
(T ) exceeds 150°C typically. The controller remains off
until T goes below nearly 130°C.
J
• ZCD pin incorrect connection:
J
♦ If the ZCD pin grounded, the circuit will detect an
output short circuit situation when 90 ms delay has
elapsed.
• Brown−Out Protection (BO)
The circuit prevents operation when the line voltage is too
low to avoid an excessive stress of the LED driver.
Operation resumes as soon as the line voltage is high
♦ A 200 kW resistor pulls down the ZCD pin so that
the output short circuit detection trips if the ZCD pin
is not connected (floating).
enough and V is higher than V
.
CC
CC(on)
www.onsemi.com
26
NCL30486
250W to take into account possible parametric deviations.
• CS pin short to ground
Also, along the circuit operation, the CS pin could happen
to be grounded. If it is grounded, the MOSFET
conduction time is limited by the 20 ms maximum
on−time. If such an event occurs, a new pin impedance
test is made.
The CS pin is checked at start−up (cold start−up or after
a brown−out event). A current source (I
) is applied
cs(short)
to the pin and no DRV pulse is generated until the CS pin
exceeds V . I and V are 500 mA and
cs(low) cs(short)
cs(low)
60 mV typically (V rising). The typical minimum
CS
• Line overvoltage protection
impedance to be placed on the CS pin for operation is then
120 W. In practice, it is recommended to place more than
(see Line OVP section)
ORDERING TABLE OPTION
Valley
Transition
from LL to HL
Line Range
Detector
Maximum Dead−time
V
REF
Max. On−time
ZCD Blanking
Standby Mode
st
st
OPN #
NCL30486_ _
1.4 ms 200 mV 333 mV
1
to
1
to
On
Off
On
Off
250 ms 687 ms
20 ms
33 ms
1 ms
1.5 ms
nd
rd
2
3
NCL30486A1
NCL30486A2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Frozen Peak Current
During Standby Mode
Dimming
Line OVP
V
Brown−out Levels
On: 108 V On: 138 V
Dimming Clamp
Curve
CS(SBY)
OPN #
NCL30486_ _
On
Off
380 mV 330 mV 280 mV
0%
1%
5%
8%
Linear Square
Off: 98 V
Off: 129 V
NCL30486A1
NCL30486A2
x
x
NA
NA
x
x
x
x
x
x
ORDERING INFORMATION
Device
†
Marking
L30486A1
L30486A2
Package type
Shipping
NCL30486A1
SOIC9 – P7 COMP VHV PBFH
2500 / Tape & Reel
(Pb−Free)
NCL30486A2
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
27
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−9 NB
CASE 751BP
ISSUE A
9
1
DATE 21 NOV 2011
SCALE 1:1
2X
NOTES:
0.10
C A-B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DE-
TERMINED AT DATUM F.
D
H
A
2X
0.20
C
4 TIPS
0.10 C A-B
F
10
6
E
1
5. DIMENSIONS A AND B ARE TO BE DETERM-
INED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
5
L2
A3
L
SEATING
PLANE
C
0.20
C
9X b
DETAIL A
B
5 TIPS
M
MILLIMETERS
0.25
C A-B D
DIM MIN
MAX
1.75
0.25
0.25
0.51
5.00
4.00
TOP VIEW
A
A1
A3
b
D
E
1.25
0.10
0.17
0.31
4.80
3.80
9X
h
X 45
_
0.10
C
0.10
C
M
e
1.00 BSC
H
h
5.80
0.37 REF
6.20
A
L
L2
M
0.40
0
1.27
0.25 BSC
DETAIL A
e
SIDE VIEW
A1
SEATING
PLANE
C
8
_
_
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
9
1.00
PITCH
9X
0.58
XXXXX
ALYWX
G
1
XXXXX = Specific Device Code
6.50
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
1
9X
1.18
DIMENSION: MILLIMETERS
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52301E
SOIC−9 NB
PAGE 1 OF 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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相关型号:
NCL31000MNITWG
Intelligent LED Driver, Visible Light Communication capable, with Precision Dimming, Diagnostics and Power Metrology
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