NCD83591MNTXG [ONSEMI]
A 3-phase, 60V gate driver for motor control applications;
| 型号： | NCD83591MNTXG |
| 厂家： | 
ONSEMI |
| 描述： | A 3-phase, 60V gate driver for motor control applications |
| 文件： | 总10页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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3-Phase Gate Driver, 60ꢀV
NCD83591
1
QFN28 4x4, 0.4P
CASE 485GF
Overview
The NCD83591 is an easy to use, multi−purpose 3−phase
gate−driver optimized for low BOM cost. The wide operating voltage
range make this device ideal for industrial and commercial
applications from 5 V (min) up to 60 V (max).
MARKING DIAGRAM
83591
AWLYWW
Features
• Operation from 5 V to 60 V Supply Voltage with Tolerance from 4 V
to 70 V
83591 = Specific Device Code
• Constant Current Drive of Power FET, Configurable from 5 mA to
250 mA (16 Settings by Input Level to VDRV Pin)
• Internally Generated Gate Drive Supply Voltages
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
WW = Work Week
• Tolerant to −12 V DC for High Side Gate and Source Output Pins
• Gate Sensing for Cross Conduction Protection and Optimized Dead
Time
ORDERING INFORMATION
• Embedded High GBW General Purpose Amplifier (Intended for
Current Sensing and Externally Configurable)
• Embedded Charge Pump Function Allowing DC Static Drive
• Strong Hold−off Current Preventing Self−turn−on
†
Device
NCD83591MNTXG
Package
Shipping
QFN28
(Pb−Free)
4000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Internal Gate Pull−down to GND during Loss of VDD (Core) Power
• Under Voltage Lock Out on VM, VGL, and VGH−VM
• 5 V/3.3 V Compatible 6 Input Control Plus Enable
• Up to 30 kHz Motor PWM with Individual Six Gate Control Mode
• 4 kV HBM and 1 kV CDM ESD Protection
• This is a Pb−Free Device
Applications
• Power Tools
• Industrial Actuators and Cobots
• Automated Guided Robots
• Light Mobility (E−Bikes, E−scooters, Hoverboards)
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
May, 2022 − Rev. 0
NCD83591/D
NCD83591
APPLICATION CIRCUIT
1 mF
220 nF
470 nF
1 mF
VGL CP1
CP2 VM VGH
VGH HS Float
Reg
Charge Pump
VM
Idrv[3:0]
18 V
VM
VM
14 V Reg
Cpower
VDD
Gate
Sensing
GH1
SH1
GH2
GH3
3 V Reg
100 nF −
1 mF
PD
PGND
Rdrv2
Rdrv1
Vsense
VDRV
(Igate Idrv[3:0]
Trim)
Idrv[3:0]
1
SH2
SH3
3
Motor
VM
VDD
VGL
Under
Voltage
Detect
VGL
2
Idrv[3:0]
Digital
Logic
VM−VGH
IH1
IL1
IH2
IL2
IH3
IL3
GL1
GL2
GL3
Gate
Sensing
PD
PGND
Idrv[3:0]
PGND
X3
EN
MCU
VDD
Ramp1
AMPP
AMPM
+
Ramp2
−
Rsns
LV8359A
GND
AMPO
Ramp1
VREF
Ramp2
Figure 1. Typical Application Diagram
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2
NCD83591
PIN ASSIGNMENT
VDD
IH1
IL1
1
2
3
4
5
6
7
21
20 GL1
SH1
19
18
17
GH2
SH2
GL2
IH2
IL2
(Top view)
IH3
IL3
16 GH3
SH3
15
Figure 2. NCD83591 Pinout
PIN ASSIGNMENTS & PIN DESCRIPTION
Pin #
Name
VDD
IH1
Description
1
Internal 3 V regulator bypass pin
Active high control for GH1
Active low control for GL1
Active high control for GH2
Active low control for GL2
Active high control for GH3
Active low control for GL3
Active high control to enable driver outputs
Configurable AMP output
Configurable AMP negative input
Configurable AMP positive input
General ground
2
3
IL1
4
IH2
5
IL2
6
IH3
7
IL3
8
EN
9
AMPO
AMPM
AMPP
GND
PGND
GL3
SH3
GH3
GL2
SH2
GH2
GL1
10
11
12
13
14
15
16
17
18
19
20
Power stage ground
Gate driver output for phase 3 low side external FET
Connection for motor phase 3
Gate driver output for phase 3 high side external FET
Gate driver output for phase 2 low side external FET
Connection for motor phase 2
Gate driver output for phase 2 high side external FET
Gate driver output for phase 1 low side external FET
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3
NCD83591
PIN ASSIGNMENTS & PIN DESCRIPTION (continued)
Pin #
Name
SH1
GH1
VGL
VGH
VM
Description
21
Connection for motor phase 1
22
Gate driver output for phase 1 high side external FET
Internal 14 V regulator bypass pin
Output of charge pump and storage capacitor pin
Motor voltage
23
24
25
26
CP2
CP1
VDRV
Pumping node of charge pump
27
Switching node of charge pump
28
Voltage used to control driver currents
ABSOLUTE MAXIMUM RATINGS (Voltages are referenced to GND unless otherwise noted)
Parameter Pins
Ratings
−0.3 to 70
Unit
V
Motor Supply Voltage
Gate Low Voltage
Gate High Voltage
VM
VGL
−0.3 to 20
V
VGH
−0.3 to 90
V
Gate High Voltage Relative to VM
High Side Output
VGH − VM
GH[1−3]
GH[1−3] − SH[1−3]
SH[1−3]
−0.3 to 20
V
−12 to VGH + 0.3
−0.3 to 20
V
Voltage between High Side Output and Motor Phase
Motor Phase
V
−12 to VGH + 0.3
−0.3 to VGL + 0.3
−0.3 to 3.65
V
Low−side Output
GL[1−3] (relative to PGND)
V
Logic Power Supply
VDD
V
Digital Inputs
IH[1−3], IL[1−3], EN
−0.3 to 6
V
Analog Inputs/Outputs
AMPM, AMPP, AMPO, VDRV
−0.3 to VDD + 0.3
−0.3 to VGL + 0.3
VM − 1 to VGH + 1
−0.1 to 0.1
V
Charge Pump − Switching Node
Charge Pump − Pumping Node
Charge Pump − Pumping Node Peak Input Current
Storage Temperature
CP1
CP2
CP2
V
V
A
−55 to 150
°C
°C
Junction Temperature
−40 to 150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
ESD RATINGS
Parameter
Ratings
4000
Unit
V
Human Body Model (HBM)
Charged Device Model (CDM)
1000
V
THERMAL INFORMATION
Parameter
Theta−JA
Pins
Ratings
62.5
Unit
°C/W
°C/W
°C/W
Junction Ambient Thermal Resistance
Psi−JB
Junction to Board Characterization Parameter
Junction to Top Characterization Parameter
23.0
Psi−JT
4.2
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4
NCD83591
ELECTRICAL CHARACTERISTICS
(Valid at a junction temperature range from −40°C to 150°C, for VM supply Voltage 8.0 V ≤ VM ≤ 60 V unless otherwise specified. Typical
values at 25°C and VM = 24 V unless specified otherwise.)
Parameter
Symbol
Conditions
Normal mode
Min
Typ
Max
Unit
VM Supply Voltage Range
5
24
60
(Note 1)
V
Full logic functionality, driver stage off
4
−
70
V
VM Supply Current
VM Supply Current
EN = H (outputs not toggling),
AMP used
−
4.6
5.7
mA
EN = H (outputs not toggling), AMP
disabled by tieing AMPP = VDD and
AMPM = GND
−
4.1
5.2
mA
INTERNAL REGULATOR (VDD)
VDD Output Voltage
3.2
3.4
3.6
1
V
VDD External Load Current
−
−
mA
GATE VOLTAGES (CP1, VGH, VGL )
VGL Output Voltage
I
I
< 15 mA, VM > 15 V
< 15 mA, VM < 15 V
13
14
−
15
−
V
V
VGL
VGL Output Voltage
VM − 0.43
VGL
VGL Current Limit
−
−
23
125
30
−
mA
kHz
V
Charge Pump Frequency
Charge Pump Output Voltage
GATE DRIVERS (GH[1−3], GL[1−3])
VGH − VM, I
< 7.5 mA
VGL − 1.2 VGL − 0.75
−
VGH
GL[n], GH[n] Discharge
Current to PGND
IDIS
ICHG
“L” level
−
2 x ICHG
−
mA
GL[n], GH[n] Charge Current
“H” level, VDRVcode = 15
“H” level, VDRVcode = 14
“H” level, VDRVcode = 13
“H” level, VDRVcode = 12
“H” level, VDRVcode = 11
“H” level, VDRVcode = 10
“H” level, VDRVcode = 9
“H” level, VDRVcode = 8
“H” level, VDRVcode = 7
“H” level, VDRVcode = 6
“H” level, VDRVcode = 5
“H” level, VDRVcode = 4
“H” level, VDRVcode = 3
“H” level, VDRVcode = 2
“H” level, VDRVcode = 1
“H” level, VDRVcode = 0
GL[1−3], GH[1−3] − SH[1−3]
Hysteresis
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
10
15
20
25
30
40
50
60
75
100
125
150
175
200
250
1
Gate Sense Low Threshold
VGSL
1
V
Cross Conduction Protection
Time
t
See Figure 3
No Load on GL[1−3] or GH[1−3]
200
ns
xcp
Input to Output Propagation
Delay
t
See Figure 3
No Load on GL[1−3] or GH[1−3]
−
−
100
ns
prop
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5
NCD83591
ELECTRICAL CHARACTERISTICS (continued)
(Valid at a junction temperature range from −40°C to 150°C, for VM supply Voltage 8.0 V ≤ VM ≤ 60 V unless otherwise specified. Typical
values at 25°C and VM = 24 V unless specified otherwise.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
GATE DRIVERS (GH[1−3], GL[1−3])
Pull−down Current (GH*, GL*)
IPD
VM = 5 V
500
900
1300
mA
VDD = 0 V
GH* = GL* = 2 V
Applied per Table 1
CONFIGURABLE AMP (AMPP, AMPM, AMPO)
AMPP, AMPM Input Current
AMPP_CUR INPUT = 0~VDD
AMPM_CUR INPUT = 0~VDD
−
−
−
−
1
−1
−1
0.1
10
mA
mA
1
VDD − 0.15
−
AMPO Full Scale Range_1
UGBW_1
FS1
RL = 10 kW
V
RL = 10 kW to GND, CL = 60 pF
At FS1
MHz
Open Loop Gain_1
AMPO Full Scale Range_2
UGBW_2
At FS1
90
0.05
8
−
−
−
−
VDD − 0.1
−
dB
V
FS2
RL = 10 kW
RL = 10 kW to GND, CL = 60 pF
At FS2
MHz
Open Loop Gain_2
Slew Rate
At FS2
75
10
−
−
−
−
dB
V/ms
mV
Unity Gain, RL = 10 kW, CL = 60 pF
RL = 10 kW
−
Input Offset Voltage
0.55
(Note 3)
4.0
Common Mode Input Voltage
0
−
VDD − 1.2
V
DIGITAL INPUTS (IH[1−3], IL[1−3], EN)
Input Frequency
−
2.1
0
−
−
−
−
30
5.5
0.7
100
kHz
V
High−level Input Voltage
Low−level Input Voltage
Pull−down Current
VIH (Note 2)
VIL (Note 2)
V
30
mA
PROTECTION LEVELS
VM Under−voltage Lock Out
VGL Under−voltage Lock Out
VGH Under−voltage Lock Out
VM
4.3
−
4.5
0.2
4.1
0.2
3.2
0.2
200
4.7
−
V
V
UV
Hysteresis
VGL
3.9
−
4.3
−
V
UV
Hysteresis
VGH – VM
Hysteresis
V
VGH
3.0
−
3.45
−
V
UV
V
Under−voltage Lock Out
De−glitch Filter
UVFILT
VDD
VM
VGL
VGH
,
−
−
ms
,
UV
UV
UV
VDD POR Lock Out
1.55
2.26
0.15
2.75
V
V
UV
Hysteresis
−
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Power dissipation and temp must be accounted for when connecting to voltages > 12 V.
2. Digital inputs are 5 V tolerant.
3. Typical value is a 1 sigma number.
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6
NCD83591
DETAILED FUNCTIONAL DESCRIPTON
Chip Activation, System States and Shutdown
Table 1 shows the operation modes and associated pin
states.
Table 1. OPERATION MODES
Driver Outputs
(Note 2)
Digital Inputs
IL*
(Note 1)
POR
(Note 4)
UV_VM
(Note 3)
UV_VGL
(Note 2, 3)
UV_VGH
(Note 3)
CP1
(Note 2)
EN
X
IH*
X
X
X
X
X
L
GH*
L−PD
L−PD
L−PD
L−PD
L−PD
L
GL*
L−PD
L−PD
L−PD
L−PD
L−PD
H
State
POR
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
H
L
X
X
X
X
X
L
L
UV
X
L
UV
X
L
Charge
Disable
Drive
X
Active
Active
Active
Active
Active
Active
L
L
H
H
H
H
Freewheel
Freewheel
Drive
L
L
H
L
L
L
L
H
H
L
L
L
H
H
L
1. IL* inputs are active low.
2. Active means outputs are following the behavior of normal operation. L−PD means that pull down currents (IPD) may be active if 3 V core
supply is not sufficient to drive L.
3. H = Under Voltage condition (supply voltage is less than detection levels & filter timer has expired).
4. H = Reset state (VDD voltage is less than detection level).
System Power Supplies (VM, VDD, VGL, VGH)
IL[1−3], IH[1−3] and EN. All pins are 5 V/3.3 V compatible.
All pins have pull−down currents, so when left floating will
be pulled low and cause the outputs to follow the appropriate
row in Table 1.
Internal Core Regulator (VDD)
The internal regulator is supplied by VM and regulates to
3.4 V at VDD. VDD needs to be bypassed to GND for
stability. It is not intended for any external loads (other than
Rdrv1/Rdrv2), but can support a load up to 1 mA, if
necessary.
Motor Control (IL[1−3] IH[1−3]) Drive 3 Mode
Drive 3 mode can be achieved by shorting the
corresponding IL and IH pins and driving the pin
combination with a single microcontroller output.
Gate Voltage Regulator (VGL)
The gate voltage regulator is supplied by VM and
regulates to 14 V at VGL.
Gate Drive (GH[1−3], GL[1−3], SH[1−3])
The gate drive circuit of the NCD83591 includes 3
half−bridge drivers which control six external N−Channel
FETs. The high side gate drivers GH[1−3] switch their gate
connection either to VGH or the respective phase
connection SH[1−3]. The low−side gate drivers GL[1−3] are
switched from VGL to PGND.
VGL provides the drive voltage for the low−side drivers
GL[1−3] directly and for the high side drivers GH[1−3]
through the charge pump circuitry. The output is current
limited. The output at VGL must be bypassed with a
capacitor to GND which should be at least 10 times the
maximum gate capacitance of the power FETs.
Gate Drive Source/Sink Current Selection
Charge Pump (VGH)
An on−chip charge pump provides the gate voltage for the
high−side drivers.
The gate drive currents are programmable to 16 different
values as defined in the Electrical Characteristics Table. The
VDRVcode is achieved by configuring Rdrv1 and Rdrv2
with standard 5% resistors as described in the Application
Diagram with the values that match the desired gate drive
currents from Table 2.
Motor Control Inputs (IL[1−3], IH[1−3], EN)
Once the NCD83591 is in Drive or Freewheel mode,
a microcontroller can facilitate motor control via the inputs
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7
NCD83591
Gate Sensing and Cross Conduction Protection
Table 2. VDRVcode DESCRIPTION
The gate sensing and cross conduction protection features
of the NCD83591 eliminate the need for any minimum dead
time control by the gate driver, or even any dead times
programmed into the MCU. Corresponding IH[n] and IL[n]
pins can be pulsed at the same time and can even be shorted
together for motor control methods that do not require
tri−stating the power stage (drive 3 mode).
The cross conduction protection feature requires one side
of a given phase to be proven to be in an “off” state before
the other side is allowed to be turned on to prevent any cross
conduction or shoot−through current in the power stage. The
diagram in Figure 3 demonstrates this behavior.
In addition, if a given side is currently in an “off” state and
something external pulls it to an “on” state, the part forces
the opposite side to an “off” state to again prevent
shoot−through currents. Sensing a FET is in an “off” state is
done through the gate sensing circuit.
The MCU can still force a controlled dead time if desired.
This is considered a Drive 6 configuration where each IL[n]
and IH[n] pin is driven independently, and the MCU forces
a dead time between when low and high sides are active.
However, the cross conduction protection will still take
precedence if this MCU programmed dead time becomes
too short.
VDRVcode
Rdrv1
82k
68k
51k
47k
33k
47k
27k
24k
36k
20k
24k
18k
13k
12k
6.8k
0
Rdrv2
12k
15k
16k
20k
18k
33k
24k
27k
51k
36k
56k
56k
56k
82k
91k
Open
ICHG
5
IDIS
10
15
14
13
12
11
10
9
10
20
15
30
20
40
25
50
30
60
40
80
8
50
100
120
150
200
250
300
350
400
500
7
60
6
75
5
100
125
150
175
200
250
4
3
2
1
0
Selected Isrc currents will typically be between 1 mA/nC
and 2 mA/nC of FET total gate charge (Qg) to achieve a
power stage switching net (SH[1−3]) transition times of
about 50 ns. General procedure to selecting a drive current
is to start low and increase until ringing on the gate nets or
switching nets becomes noticeable, but is still acceptable.
The gate sensing provides yet another feature of the part
in which a much stronger sinking driver is activated about
50 ns after a gate is sensed to be low. This results in a low
hold−off driver resistance to further prevent self turn−on
when the SH[n] net is transitioning fast.
IL[n] (act now)
IH[n]
tprop
tprop
GL[n]
VGSL
VGSL
GH[n]−SH[n]
txcp
txcp
Figure 3. Gate Sensing and Dead Time Diagram
Configurable Amp (AMPP, AMPN, AMPO)
any configuration that follows the constraints outlined in the
Electrical Characteristics table.
If the configurable amp is not intended to be used, about
0.5 mA of current can be saved by tieing AMPP = VDD and
AMPM = GND.
An externally configurable high performance general
purpose amplifier is included. It is intended for current
sensing as per the Application Diagram, but can be used in
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8
NCD83591
PACKAGE DIMENSIONS
QFN28 4x4, 0.4P
CASE 485GF
ISSUE O
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
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9
NCD83591
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products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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