NC7SP57L6X [ONSEMI]
TinyLogic ULP通用可配置2输入逻辑门;
| 型号： | NC7SP57L6X |
| 厂家： | 
ONSEMI |
| 描述： | TinyLogic ULP通用可配置2输入逻辑门 栅 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Is Now
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www.onsemi.com
onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
TinyLogic ULP-A Universal
Configurable Logic Gates
NC7SP57, NC7SP58
The NC7SP57 and NC7SP58 are universal configurable logic gates
in tiny footprint packages. The devices are designed to operate
=
for V
0.9 V to 3.6 V.
CC
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Features
MARKING
DIAGRAM
• Designed for 0.9 V to 3.6 V V Operation
CC
• 3.4 ns t at 3.3 V (Typ)
PD
SIP6 1.45X1.0
MicroPak
CASE 127EB
• Inputs/Outputs Over−Voltage Tolerant up to 3.6 V
CCKK
XYZ
• I
Supports Partial Power Down Protection
• Source/Sink 2.6 mA at 3.3 V
OFF
Pin 1
• Available in SC−88 and MicroPak™ Packages
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
CC
KK
XY
Z
= Specific Device Code
= 2−Digit Lot Run Traceability Code
= 2−Digit Date Code
= Assembly Plant Code
MARKING
DIAGRAM
1
2
3
6
5
4
I2
V
I1
GND
I0
I1
GND
I0
1
2
3
6
5
4
I2
V
CC
CC
SC−88
DF SUFFIX
CASE 419B−02
XXXMG
G
Y
Y
XXX = Specific Device Code
SC−88
MicroPak
M
= Date Code
G
= Pb−Free Package
Figure 1. Pinout Diagrams (Top Views)
PIN ASSIGNMENT
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 9 of this data sheet.
Pin
1
SC−88
MicroPak
I1
GND
I0
I1
GND
I0
2
3
4
Y
Y
5
V
CC
V
CC
6
I2
I2
© Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
February, 2021 − Rev. 1
NC7SP58/D
NC7SP57, NC7SP58
FUNCTION TABLE
Inputs
NC7SP57
NC7SP58
I2
L
I1
L
I0
Y = (I0) w (I2) + (I1) w (I2)
Y = (I0) w (I2) + (I1) w (I2)
L
H
L
H
L
H
L
L
L
L
L
H
H
L
H
L
L
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
FUNCTION SELECTION TABLE
2−Input Logic Function
2−Input AND
Device Selection
NC7SP57
NC7SP58
NC7SP57
NC7SP58
NC7SP57
NC7SP58
NC7SP58
NC7SP57
NC7SP58
NC7SP57
NC7SP58
NC7SP57
NC7SP58
NC7SP57
Connection Configuration
Figure 2
2−Input AND with inverted input
2−Input AND with both inputs inverted
2−Input NAND
Figure 8, 9
Figure 5
Figure 7
2−Input NAND with inverted input
2−Input NAND with both inputs inverted
2−Input OR
Figure 3, 4
Figure 10
Figure 10
2−Input OR with inverted input
2−Input OR with both inputs inverted
2−Input NOR
Figure 3, 4
Figure 7
Figure 5
2−Input NOR with inverted input
2−Input NOR with both inputs inverted
2−Input XOR
Figure 8, 9
Figure 2
Figure 11
2−Input XNOR
Figure 6
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2
NC7SP57, NC7SP58
Logic Configurations NC7SP57
Figure 2. 2−Input AND Gate
Figure 3. 2−Input NAND with Inverted A Input
Figure 5. 2−Input NOR Gate
Figure 4. 2−Input NAND with Inverted B Input
Figure 6. 2−Input XNOR Gate
NOTE: Figure 2 through Figure 6 show the logical functions that can be implemented using the NC7SP57. The diagrams show the
DeMorgan’s equivalent logic duals for a given 2−input function. Next to the logical implementation is the board level physical
implementation of how the pins of the function should be connected.
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3
NC7SP57, NC7SP58
Logic Configurations NC7SP58
Figure 8. 2−Input AND with Inverted A Input
Figure 7. 2−Input NAND Gate
Figure 10. 2−Input OR Gate
Figure 9. 2−Input AND with Inverted B Input
Figure 11. 2−Input XOR Gate
NOTE: Figure 7 through Figure 11 show the logical functions that can be implemented using the NC7SP58. The diagrams show the
DeMorgan’s equivalent logic duals for a given 2−input function. Next to the logical implementation is the board level physical
implementation of how the pins of the function should be connected.
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4
NC7SP57, NC7SP58
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +4.3
−0.5 to +4.3
V
IN
V
V
OUT
Active−Mode (High or Low State)
Tri−State Mode (Note 11)
−0.5 to V + 0.5
V
CC
−0.5 to +4.3
−0.5 to +4.3
Power−Down Mode (V = 0 V)
CC
I
DC Input Diode Current
V
< GND
< GND
−50
−50
mA
mA
mA
mA
°C
IK
IN
I
DC Output Diode Current
V
OUT
OK
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin or Ground Pin
Storage Temperature Range
50
OUT
I
or I
GND
STG
50
CC
T
−65 to +150
260
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 12)
°C
L
T
+150
°C
J
q
SC−88
MicroPak
377
154
°C/W
JA
P
D
Power Dissipation in Still Air
SC−88
MicroPak
332
812
mW
MSL
Moisture Sensitivity
Level 1
−
−
V
F
R
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage (Note 3)
Human Body Model
Charged Device Model
2000
1000
I
Latchup Performance (Note 4)
100
mA
Latchup
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Applicable to devices with outputs that may be tri−stated.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow per JESD51−7.
3. HBM tested to EIA / JESD22−A114−A. CDM tested to JESD22−C101−A. JEDEC recommends that ESD qualification to EIA/JESD22−A115A
(Machine Model) be discontinued.
4. Tested to EIA/JESD78 Class II.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
0.9
0
Max
3.6
Unit
V
V
CC
Positive DC Supply Voltage
DC Input Voltage
V
IN
3.6
V
V
OUT
DC Output Voltage
Active−Mode (High or Low State)
Tri−State Mode (Note 11)
0
0
0
V
CC
3.6
3.6
Power−Down Mode (V = 0 V)
CC
T
A
Operating Temperature Range
−40
+85
°C
t , t
Input Transition Rise and Fall Time
0
No Limit
ns/V
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
NC7SP57, NC7SP58
DC ELECTRICAL CHARACTERISTICS
T
A
= 255C
Typ
T
= −405C to +855C
A
Min
Max
Min
Max
Symbol
Parameter
Condition
V
CC
(V)
Unit
0.9
0.62
−
−
−
V
Positive Threshold
Voltage
V
−
−
−
−
−
−
P
1.1
1.4
1.0
1.2
1.5
1.9
2.6
−
1.0
1.2
1.5
1.9
2.6
−
−
1.65
3.0
−
−
−
−
−
−
−
−
−
−
3.0 to 3.6
0.9
−
0.34
−
V
V
Negative Threshold
Voltage
V
V
V
N
1.1
0.15
0.2
0.15
0.2
−
−
−
−
1.4
−
1.65
2.3
0.25
0.4
−
0.25
0.4
−
−
−
−
−
3.0
0.6
−
−
0.6
−
0.9
−
0.29
−
−
−
−
Hysteresis Voltage
H
1.1
0.08
0.09
0.1
0.6
0.8
1.0
1.1
1.8
0.08
0.09
0.1
0.6
0.8
1.0
1.1
1.8
1.4
−
1.65
2.3
−
0.25
0.6
−
0.25
0.6
3.0
−
V
I
= V or V
V
OH
High−Level Output
Voltage
IN
IH
IL
0.9
−
V
CC
0.1
−
−
−
−
= −20 mA
OH
1.1 to 1.3
1.4 to 1.6
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.1 to 1.3
1.4 to 1.6
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
V
V
V
V
V
− 0.1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
V
− 0.1
−
−
−
−
−
−
−
−
−
−
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
− 0.1
− 0.1
− 0.1
− 0.1
V
V
V
V
− 0.1
− 0.1
− 0.1
− 0.1
I
I
I
I
I
= −0.5 mA
= −1 mA
0.75 x V
1.07
0.70 x V
0.99
OH
OH
OH
OH
OH
CC
CC
= −1.5 mA
= −2.1 mA
= −2.6 mA
= V or V
1.24
1.22
1.95
1.87
2.61
2.55
V
V
OL
Low−Level Output
Voltage
V
IN
IH
IL
0.9
−
−
−
−
−
−
−
−
−
−
−
0.1
−
−
0.1
−
−
−
−
−
−
−
−
−
−
−
−
0.1
I
= 20 mA
OL
1.1 to 1.3
1.4 to 1.6
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.1 to 1.3
1.4 to 1.6
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
−
0.1
0.1
−
0.1
0.1
−
0.1
0.1
−
0.1
0.1
I
OL
I
OL
I
OL
I
OL
I
OL
= 0.5 mA
= 1 mA
−
0.3 x V
0.31
0.31
0.31
0.31
0.3 x V
0.37
0.35
0.33
0.33
CC
CC
−
= 1.5 mA
= 2.1 mA
= 2.6 mA
−
−
−
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6
NC7SP57, NC7SP58
DC ELECTRICAL CHARACTERISTICS (continued)
T
A
= 255C
Typ
−
T
= −405C to +855C
A
Min
Max
Min
Max
Symbol
Parameter
Condition
V
CC
(V)
Unit
I
IN
Input Leakage
Current
V
IN
= 0 V to 3.6 V
0.9 to 3.6
−
0.1
−
−
−
0.5
mA
I
Power Off Leakage
Current
V
V
= 0 V to 3.6 V or
OUT
0
−
−
−
−
0.5
0.9
0.5
0.9
mA
mA
OFF
IN
= 0 V to 3.6 V
I
Quiescent Supply
Current
V
IN
= V or GND
0.9 to 3.6
CC
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
Typ
54.3
15.1
8.2
T
= −405C to +855C
A
Min
−
Max
−
Min
Max
Symbol
, t
Parameter
Condition
R = 1 MW, C = 10 pF
V
(V)
Unit
CC
t
t
t
Propagation Delay,
(I0 or I1 or I2) to Y
(Figures 12 and 13)
0.9
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
PLH PHL
L
L
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
0.9
−
30.8
17.0
14.0
10.0
8.0
51.0
21.0
17.0
13.0
12.0
−
−
−
5.9
−
4.0
−
3.4
, t
Propagation Delay,
(I0 or I1 or I2) to Y
(Figures 12 and 13)
R = 1 MW, C = 15 pF
−
55.8
15.6
8.6
−
ns
ns
PLH PHL
L
L
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
0.9
−
32.1
18.0
15.0
11.0
9.0
52.0
22.0
18.0
14.0
12.0
−
−
−
6.3
−
4.2
−
3.6
, t
Propagation Delay,
(I0 or I1 or I2) to Y
(Figures 12 and 13)
R = 1 MW, C = 30 pF
−
60.2
17.2
9.9
−
PLH PHL
L
L
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
−
33.6
20.0
17.0
12.0
11.0
55.0
24.0
20.0
15.0
14.0
−
−
7.4
−
5.0
−
4.1
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance (Note 5)
Test Condition
Typical (T = 25°C)
Unit
pF
A
C
V
V
= 0 V
= 0 V
2.0
4.0
8.0
IN
CC
C
pF
OUT
CC
C
f = 10 MHz, V = 0.9 to 3.6 V, V = 0 V or V
CC
pF
PD
CC
IN
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption: P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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7
NC7SP57, NC7SP58
OPEN
Test
/ t
Switch Position
2 x V
DUT
GND
CC
t
Open
PLH PHL
t
/ t
2 x V
CC
PLZ PZL
R
1
L
t
/ t
GND
PHZ PZH
INPUT
OUTPUT
R
R
C *
L
T
C includes probe and jig capacitance
L
R is Z
of pulse generator (typically 50 W)
T
OUT
f = 1 MHz
Figure 12. Test Circuit
V
CC
t = 3 ns
r
t = 3 ns
f
V
CC
90%
90%
INPUT
V
mi
V
mi
V
mi
V
mi
INPUT
GND
~V
10%
10%
GND
t
t
PLZ
PZL
t
t
PLH
PHL
CC
V
OH
V
V
OUTPUT
OUTPUT
mo
V
V
V
V
OUTPUT
OUTPUT
mo
mo
V
+ V
OL
OL
Y
V
V
V
OL
t
t
PHZ
PZH
t
t
PLH
PHL
V
OH
OH
V
− V
OH
Y
mo
mo
mo
V
OL
~0 V
V
, V
V
, V
V
, V
/ 2
/ 2
/ 2
/ 2
/ 2
V , V
CC
mi
mo
CC
CC
CC
CC
CC
Y
0.9
V
CC
V
CC
V
CC
V
CC
V
CC
/ 2
/ 2
/ 2
/ 2
/ 2
V
V
V
V
V
0.1
0.1
1.1 to 1.3
1.4 to 1.6
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
0.1
0.15
0.15
0.3
1.5
1.5
Figure 13. Switching Waveforms
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8
NC7SP57, NC7SP58
ORDERING INFORMATION
Pin 1 Orientation
(See below)
†
Device
NC7SP57P6X
NC7SP57L6X
NC7SP58P6X
NC7SP58L6X
Package
SC−88
Marking
P57
K9
Shipping
Q4
Q4
Q4
Q4
3000 / Tape & Reel
5000 / Tape & Reel
3000 / Tape & Reel
5000 / Tape & Reel
MicroPak
SC−88
P58
L3
MicroPak
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Pin 1 Orientation in Tape and Reel
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9
NC7SP57, NC7SP58
PACKAGE DIMENSIONS
SIP6 1.45X1.0
CASE 127EB
ISSUE O
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10
NC7SP57, NC7SP58
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−− 0.043
−−− 0.004
6X b
B
TOP VIEW
A
−−−
−−−
1.10
A1 0.00
A2 0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1 1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXMG
6X
0.66
G
1
2.50
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
www.onsemi.com
11
NC7SP57, NC7SP58
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1. ANODE 2
2. N/C
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1. ANODE
2. ANODE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
3. COLLECTOR
3. CATHODE 1
4. ANODE 1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR 2
6. ANODE
6. CATHODE
6. CATHODE 2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
4. SOURCE 1
5. DRAIN 1
6. GATE 2
4. DRAIN 1
5. DRAIN 2
6. GATE 2
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
5. BASE 2
6. COLLECTOR 2
STYLE 13:
PIN 1. ANODE
2. N/C
STYLE 14:
PIN 1. VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1. VIN1
2. VCC
PIN 1. ANODE 1
2. ANODE 2
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE 3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
5. EMITTER 1
6. COLLECTOR 1
5. EMITTER 2
6. COLLECTOR 1
6. CATHODE
STYLE 19:
PIN 1. I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1. ANODE 1
2. N/C
STYLE 22:
PIN 1. D1 (i)
2. GND
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
STYLE 24:
PIN 1. CATHODE
2. ANODE
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE 2
4. CATHODE 2
5. N/C
3. D2 (i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2 (c)
5. VBUS
6. D1 (c)
4. N/C
5. V EN
5. CH2
6. N/C
6. V REF
6. CATHODE 1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1. ANODE
2. ANODE
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
3. DRAIN 2
4. SOURCE 2
5. GATE 2
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR 1
6. DRAIN 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
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