NB4N855S_06 [ONSEMI]
3.3 V, 1.5 Gb/s Dual AnyLevel TM to LVDS Receiver/Driver/Buffer/ Translator; 3.3 V ， 1.5 Gb / s的双AnyLevel以旧换新LVDS接收器/驱动器/缓冲器/翻译
| 型号： | NB4N855S_06 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V, 1.5 Gb/s Dual AnyLevel TM to LVDS Receiver/Driver/Buffer/ Translator |
| 文件： | 总9页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB4N855S
3.3 V, 1.5 Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator
Description
http://onsemi.com
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel input signal (LVPECL, CML, HSTL,
LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance,
noise immunity of the system design, and transmission line media, this
device will receive, drive or translate data or clock signals up to
1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin plug in
compatible to the SY55855V in a 3.3 V applications.
MARKING
DIAGRAM*
10
1
855S
AYWG
G
Micro−10
M SUFFIX
CASE 846B
The NB4N855S has a wide input common mode range of
1
GND + 50 mV to V − 50 mV. This feature is ideal for translating
CC
A
Y
W
G
= Assembly Location
= Year
differential or single−ended data or clock signals to 350 mV typical
LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S
is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Application notes, models, and support documentation are available
at www.onsemi.com.
*For additional marking information, refer to
Application Note AND8002/D.
Features
• Guaranteed Input Clock Frequency up to 1.0 GHz
• Guaranteed Input Data Rate up to 1.5 Gb/s
• 490 ps Maximum Propagation Delay
• 1.0 ps Maximum RMS Jitter
D0
D0
Q0
Q0
• 180 ps Maximum Rise/Fall Times
• Single Power Supply; V = 3.3 V ±10%
CC
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
D1
D1
Q1
Q1
• GND + 50 mV to V − 50 mV V
Range
CC
CMR
• Pb−Free Package is Available
Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Device DDJ = 7 ps
TIME (133 ps/div)
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5
(VINPP = 100 mV, Input Signal DDJ = 24 ps)
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 2
NB4N855S/D
NB4N855S
D0
D0
V
CC
1
2
10
9
Q0
Q0
D1
8
3
4
5
7
6
D1
Q1
Q1
GND
Figure 2. Pin Configuration and Block Diagram
(Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
D0
LVPECL, CML, LVCMOS,
LVTTL, LVDS
Noninverted Differential Clock/Data D0 Input.
2
3
4
D0
D1
D1
LVPECL, CML, LVCMOS,
LVTTL, LVDS
Inverted Differential Clock/Data D0 Input.
LVPEL, CML, LVDS LVCMOS, Noninverted Differential Clock/Data D1 Input.
LVTTL
LVPECL, CML, LVDS
LVCMOS LVTTL
Inverted Differential Clock/Data D1 Input.
5
6
GND
Q1
−
Ground. 0 V.
LVDS Output
Inverted Q1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
7
8
Q1
Q0
Q0
LVDS Output
LVDS Output
LVDS Output
−
Noninverted Q1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
Inverted Q0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
9
Noninverted Q0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
10
V
CC
Positive Supply Voltage.
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2
NB4N855S
Table 2. ATTRIBUTES
Characteristics
Value
Pb−Free Pkg
Level 1
Moisture Sensitivity (Note 1)
Pb Pkg
Level 1
Micro−10
Flammability Rating
ESD Protection
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 1 kV
Transistor Count
281
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Positive Input
Condition 1
GND = 0 V
Condition 2
Rating
3.8
Unit
V
V
CC
V
I
GND = 0 V
V = V
3.8
V
I
CC
I
IN
Input Current Through R (50 W Resistor)
Static
Surge
35
70
mA
mA
T
I
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
mA
OSC
Q or Q to GND
Q to Q
Continuous
Continuous
12
24
T
Operating Temperature Range
Micro−10
−40 to +85
°C
°C
A
T
stg
Storage Temperature Range
−65 to +150
Thermal Resistance (Junction−to−Ambient) (Note 2)
0 lfpm
500 lfpm
Micro−10
Micro−10
177
132
°C/W
°C/W
q
JA
Thermal Resistance (Junction−to−Case)
1S2P (Note 4)
40
°C/W
°C
Micro−10
q
JC
T
sol
Wave Solder
Pb <3 Sec @ 248°C
Pb−Free <3 Sec @ 260°C
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power).
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3
NB4N855S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS V = 3.0 V to 3.6 V, GND = 0 V, T = −40°C to +85°C
CC
A
Symbol
Characteristic
Min
Typ
Max
Unit
I
Power Supply Current (Note 3)
40
53
mA
CC
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 10 and 12)
V
th
V
IH
V
IL
Input Threshold Reference Voltage Range (Note 4)
Single−ended Input HIGH Voltage
GND +100
V
− 100
mV
mV
mV
CC
V
th
+ 100
V
CC
Single−ended Input LOW Voltage
GND
V
− 100
th
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11 and 13)
V
IHD
V
ILD
V
CMR
V
ID
Differential Input HIGH Voltage
100
V
mV
mV
mV
mV
CC
Differential Input LOW Voltage
GND
V
− 100
CC
Input Common Mode Range (Differential Configuration)
GND + 50
100
V
− 50
CC
Differential Input Voltage (V
− V
)
V
CC
IHD
ILD
LVDS OUTPUTS (Note 5)
Differential Output Voltage
V
OD
250
0
450
25
mV
mV
mV
mV
mV
mV
DV
Change in Magnitude of V for Complementary Output States (Note 6)
1.0
OD
OD
V
OS
Offset Voltage (Figure 9)
1125
0
1375
25
DV
Change in Magnitude of V for Complementary Output States (Note 6)
1.0
OS
OS
V
OH
V
OL
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 8)
1425
1075
1600
900
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Dx/Dx at the DC level within V
and output pins loaded with R = 100 W across differential.
CMR
L
4. V is applied to the complementary input when operating in single−ended mode.
th
5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 8.
6. Parameter guaranteed by design verification not tested in production.
7. V max = V max + ½ V max.
OH
OS
OD
8. V max = V min − ½ V max.
OL
OS
OD
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4
NB4N855S
Table 5. AC CHARACTERISTICS V = 3.0 V to 3.6 V, GND = 0 V; (Note 9)
CC
−40°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (@ V
) f ≤ 1.0 GHz 230 350
INPPMIN in
230 350
200 300
230 350
200 300
mV
OUTPP
(Figure 3)
f = 1.5 GHz 200 300
in
f
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
ps
DATA
t
t
,
Differential Input to Differential Output
Propagation Delay
330 410
490
330 410
490
330 410
490
PLH
PHL
t
Duty Cycle Skew (Note 10)
Within −Device Skew (Note 11)
Device to Device Skew (Note 12)
8
10
20
45
35
100
8
10
20
45
35
100
8
10
20
45
35
100
ps
SKEW
t
RMS Random Clock Jitter (Note 13)
f
= 1.0 GHz
= 1.5 GHz
0.5
0.5
6
1
0.5
0.5
6
1
0.5
0.5
6
1
JITTER
in
in
f
1
1
1
ps
Deterministic Jitter (Note 14)
f
f
f
= 622 Mb/s
= 1.5 Gb/s
= 2.488 Gb/s
15
20
25
40
15
20
25
40
15
20
25
40
DATA
DATA
DATA
7
7
7
10
20
10
20
10
20
Crosstalk Induced Jitter (Note 15)
Input Voltage Swing/Sensitivity
V
100
V
−
100
V
−
100
V
−
mV
ps
INPP
CC
GND
CC
GND
CC
GND
(Differential Configuration) (Note 16)
t
r
t
f
Output Rise/Fall Times @ 250 MHz
(20% − 80%)
Q, Q 50
110
180
50
110
180
50
110
180
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing V
with 50% duty cycle clock source and V − 1400 mV offset. All loading with an external R = 100 W across
INPPMIN
C
C
L
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
10.See Figure 7 differential measurement of t = |t − t | for a nominal 50% differential clock input waveform @ 250 MHz.
skew
PLH
PHL
11. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
12.Skew is measured between outputs under identical transition @ 250 MHz.
13.RMS jitter with 50% Duty Cycle clock signal.
23
14.Deterministic jitter with input NRZ data at PRBS 2 −1 and K28.5.
23
15.Crosstalk Induced Jitter is the additive Deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 2 −1 as
an asynchronous signals.
16.Input voltage swing is a single−ended measurement operating in differential mode.
400
350
300
−40°C
250
85°C
200
25°C
150
100
50
0
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
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5
NB4N855S
Device DDJ = 6 ps
Device DDJ = 6 ps
TIME (322 ps/div)
TIME (322 ps/div)
Figure 4. Typical Output Waveform at 1.5 Gb/s with 223−1
(VINPP = 100 mV (left) & VINPP = 400 mV (right), Input Signal DDJ = 24 ps)
Device DDJ = 10 ps
Device DDJ = 10 ps
TIME (80 ps/div)
TIME (80 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with 223−1
(VINPP = 100 mV (left) & VINPP = 400 mV (right), Input Signal DDJ = 30 ps)
R
R
C
C
1.25 kW
1.25 kW
Dx
1.25 kW
1.25 kW
I
D
x
Figure 6. Input Structure
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6
NB4N855S
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 7. AC Reference Measurement
Z = 50 W
Q
Q
D
D
o
LVDS
LVDS
Receiver
Device
Driver
100 W
Z = 50 W
Device
o
Figure 8. Typical LVDS Termination for Output Driver and Device Evaluation
Q
Q
V
N
N
OH
OL
V
OS
V
OD
V
Figure 9. LVDS Output
D
D
D
D
V
V
IH
V
IL
th
V
th
Figure 10. Differential Input Driven
Figure 11. Differential Inputs Driven
Differentially
Single−Ended
V
CC
V
V
V
IH(MAX)
V
CC
V
V
IHmax
V
IL
thmax
ILmax
D
IH
V
CMR
V
= V − V
IHD ILD
INPP
V
th
V
IL
V
V
IHmin
V
V
V
IH
thmin
ILmin
D
GND
IL(MIN)
V
EE
Figure 13. VCMR Diagram
Figure 12. Vth Diagram
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7
NB4N855S
ORDERING INFORMATION
Device
†
Package
Shipping
NB4N855SMR4
Micro−10
1000 / Tape & Reel
1000 / Tape & Reel
NB4N855SMR4G
Micro−10
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
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8
NB4N855S
PACKAGE DIMENSIONS
Micro−10
CASE 846B−03
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846B−01 OBSOLETE. NEW STANDARD
846B−02
−B−
K
G
PIN 1 ID
D 8 PL
M
S
S
A
0.08 (0.003)
T B
MILLIMETERS
INCHES
DIM MIN
MAX
3.10
3.10
MIN
MAX
0.122
0.122
0.043
0.012
A
B
C
D
G
H
J
2.90
2.90
0.95
0.20
0.114
0.114
1.10 0.037
0.30 0.008
0.50 BSC
0.020 BSC
C
0.038 (0.0015)
−T−
0.05
0.10
4.75
0.40
0.15 0.002
0.21 0.004
5.05 0.187
0.70 0.016
0.006
0.008
0.199
0.028
SEATING
PLANE
L
K
L
H
J
SOLDERING FOOTPRINT*
1.04
0.041
0.32
0.0126
10X
10X
3.20
4.24
5.28
0.126
0.167 0.208
0.50
mm
inches
ǒ
Ǔ
8X0.0196
SCALE 8:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
AnyLevel is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Order Literature: http://www.onsemi.com/litorder
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2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NB4N855S/D
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