NB4N507ADR2G [ONSEMI]

3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer; 3.3V / 5V ， 50 MHz至200 MHz的PECL时钟合成器


型号：	NB4N507ADR2G
厂家：	ONSEMI
描述：	3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer 3.3V / 5V ， 50 MHz至200 MHz的PECL时钟合成器时钟
文件：	总7页 (文件大小：124K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NB4N507A

3.3V/5V, 50 MHz to 200 MHz

PECL Clock Synthesizer

Description

The NB4N507A is a precision clock synthesizer which generates a

very low jitter differential PECL output clock. It produces a clock

output based on an integer multiple of an input reference frequency.

The NB4N507A accepts a standard fundamental mode crystal,

using Phase−Locked−Loop (PLL) techniques, will produce output

clocks up to 200 MHz. In addition, the PLL circuitry will produce a

50% duty cycle square−wave clock output.

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The NB4N507A can be programmed to generate a selection of input

reference frequency multiples. An exact 155.52 MHz output clock can

be generated from a 19.44 MHz crystal and the x8 multiplier selection.

The NB4N507A is intended for low output jitter clock generation.

SOIC−16

D SUFFIX

CASE 751B

Features

• Input Crystal Frequency of 10 − 27 MHz

• Enable Usage of Common Low−Cost Crystal

• Differential PECL Output Clock Frequencies up to 200 MHz

• Duty Cycle of 48%/52%

MARKING DIAGRAM

• Operating Range: V = 3.0 V to 5.5 V

• Ideal for SONET Applications and Oscillator Manufacturers

• Available in Die Form

• Packaged in 16−Pin Narrow SOIC

• Pb−Free Packages are Available*

NB4N507AG

AWLYWW

ꢀ

Osc

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

CLKOUT

PECL

VCO

ꢀ

Mult

S0 S1

Figure 1. Simplified Logic Block

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 2

NB4N507A/D

NB4N507A

X1/CLK

Crystal

CLKOUT

Oscillator

Buffer

ꢀ

Phase

Detector

Charge

Pump

PECL

Output

VCO

Feedback

Multiplier

Select

ꢀ

S0 S1

GND

Figure 2. NB4N507A Logic Diagram

Table 1. CLOCK MULTIPLIER SELECT TABLE

X1/CLK

Multiplier

9.72X*

10X

12X

6.25X

GND

CLKOUT

Table 2. OE, OUTPUT ENABLE FUNCTION

Function

Disable

Enable

Figure 3. 16−Pin SOIC (Top View)

*Crystal = 16 MHz, f

L = GND

= 155.52 MHz

CLKOUT

H = V

M = OPEN

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NB4N507A

Table 3. PIN DESCRIPTION

Pin #

SOIC−16

Name

I/O

Description

X1/CLK

Crystal Input

Power Supply

Tri−Level Input

Power Supply

No Connect

Crystal or Clock Input

2,3

Positive Supply Voltage (3.0 V to 5.5 V)

Multiplier Select Pin; When Left Open, Defaults to V B 2

5,6

GND

Negative Supply Voltage

7,10,11,12,

CLKOUT

PECL Output

Non−inverted differential PECL clock output.

Inverted differential PECL clock output.

(LV)CMOS/(LV)TTL

Input

Output Enable for the CLKOUT/CLKOUT Outputs. Outputs are

enabled when HIGH or when left open; OE pin has internal pullup resistor. Disables

both outputs when LOW. CLKOUT goes LOW, CLKOUT goes HIGH.

Tri−Level Input

Multiplier Select Pin; When Left Open, Defaults to V B 2

Crystal Input

Table 4. ATTRIBUTES

Characteristics

Value

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 1 kV

> 150 V

> 1 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Transistor Count

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

1145 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 5. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

Positive Power Supply

GND = 0 V

Input Voltage

GND − 0.5 ≤ V ≤ V + 0.5

Operating Temperature Range

Storage Temperature Range

Thermal Resistance (Junction−to−Ambient)

−40 to +85

°C

−65 to +150

stg

0 lfpm

500 lfpm

SOIC−16

100

°C/W

Thermal Resistance (Junction−to−Case)

(Note 2)

33 to 36

°C/W

°C

sol

Wave Solder

Pb < 3 sec @ 248°C

Pb−Free < 3 sec @ 260°C

265

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).

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NB4N507A

Table 6. DC CHARACTERISTICS (V = 3.0 V to 5.5 V, GND = 0 V, T = −40°C to +85°C (Note 3))

Symbol

Characteristic

Min

Typ

Max

Unit

Power Supply Current

= 5 V

(does not include output load resistor current)

= 3.3 V

Output HIGH Voltage (Notes 5 & 6)

= 5 V

= 3.3 V

3.95

2.57

4.05

2.67

4.15

2.77

Output LOW Voltage (Notes 5 & 6)

Input HIGH Voltage (Note 4)

Input LOW Voltage,(Note 4)

= 5 V

3.12

1.90

3.20

2.00

3.30

2.10

= 3.3 V

S0, S1, X1

– 0.5

2.0

S0, S1, X1

0.5

0.8

Internal Crystal Capacitance, X1 & X2

Input Capacitance, S0, S1, OE

5.0

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. PECL output parameters vary 1:1 with V

4. S0 and S1 default to V B 2 when left open.

Table 7. AC CHARACTERISTICS (V = 3.0 V to 5.5 V, GND = 0 V, T = −40°C to +85°C (Note 5))

Symbol

Characteristic

Min

Typ

Max

Unit

MHz

Crystal Input Frequency

Xtal

Input Clock Frequency (Note 8)

Output Frequency Range

CLK

OUT

550

200

Output Amplitude

680

out pk−pk

Clock Output Duty Cycle (Note 8)

PLL Bandwidth (Note 8)

PLL

kHz

jitter (pd)

Period Jitter (RMS, 1s, 10,000 Cycles)

Period Jitter (Peak−to−Peak, 10,000 Cycles)

Output Rise and Fall Times (Note 8)

$20

500

tr/tf

270

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. PECL outputs loaded with external resistors for proper operation (see Figure 4).

6. V

and V can be set by the external resistors, which can be modified.

7. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors

should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL

is the specified crystal load capacitance: Crystal caps (pF) = (CL−5) x 2. So, for a crystal with 16 pF load capacitance, use two 22 pF caps.

8. Guaranteed by design and characterization.

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NB4N507A

GND

NB4N507

z = 50 W

62 W

PECL

Driver

PECL

Receiver

62 W

z = 50 W

270 W

GND

Figure 4. Recommended PECL Output Loading for the NB4N507A

APPLICATIONS INFORMATION

High Frequency Differential PECL Oscillators: The

NB4N507A. Since the output of the chip is phase−locked to

the input, the NB4N507A has no temperature dependence,

and the temperature coefficient of the combined system is

the same as that of the low frequency TCXO.

NB4N507A, along with a low frequency fundamental mode

crystal, can build a high frequency differential PECL output

oscillator. For example, a 10 MHz crystal connected to the

NB4N507A with the 12X output selected (S1 = 0, S0 = 1)

produces a 120 MHz PECL output clock.

High Frequency VCXO: The bandwidth of the PLL is

guaranteed to be greater than 10 kHz. This means that the

PLL will track any modulation on the input with a frequency

of less than 10 kHz. By using this property, a low frequency

VCXO can be built. The output can then be multiplied by the

NB4N507A, thereby producing a high frequency VCXO.

High Frequency TCXO: Extending the previous

application, an inexpensive, low frequency TCXO can be

built and the output frequency can be multiplied using the

Decoupling and External Components

The NB4N507A requires a 0.01 mF decoupling capacitor

to be connected between V and GND on pins 2 and 5. It

must be connected close to the NB4N507A. Other V and

GND connections should be connected to those pins, or to the

and GND planes on the board. Another four resistors are

needed for the PECL outputs as shown on the block diagram

in Figure 1. Suggested values of these resistors are shown in

the Block Diagram, but they can be varied to change the

differential pair output swing, and the DC level.

ORDERING INFORMATION

†

Device

NB4N507AD

Package

Shipping

SOIC−16

48 Units / Rail

NB4N507ADG

SOIC−16

(Pb−Free)

NB4N507ADR2

SOIC−16

2500 / Tape & Reel

NB4N507ADR2G

SOIC−16

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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NB4N507A

Resource Reference of Application Notes

AN1405/D

AN1406/D

AN1503/D

AN1504/D

AN1568/D

AN1672/D

AND8001/D

AND8002/D

AND8020/D

AND8066/D

AND8090/D

−

ECL Clock Distribution Techniques

Designing with PECL (ECL at +5.0 V)

ECLinPSt I/O SPiCE Modeling Kit

Metastability and the ECLinPS Family

Interfacing Between LVDS and ECL

The ECL Translator Guide

Odd Number Counters Design

Marking and Date Codes

Termination of ECL Logic Devices

Interfacing with ECLinPS

AC Characteristics of ECL Devices

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NB4N507A

PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

CASE 751B−05

ISSUE J

−A−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

−B−

P 8 PL

0.25 (0.010)

MILLIMETERS

INCHES

MIN

DIM MIN

MAX

10.00

4.00

1.75

0.49

1.25

MAX

0.393

0.157

0.068

0.019

0.049

9.80

3.80

1.35

0.35

0.40

0.386

0.150

0.054

0.014

0.016

R X 45

1.27 BSC

0.050 BSC

−T−

SEATING

PLANE

0.19

0.10

0.25

0.008

0.004

0.009

16 PL

5.80

0.25

6.20

0.50

0.229

0.010

0.244

0.019

0.25 (0.010)

T B

ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

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For additional information, please contact your local

Sales Representative

NB4N507A/D

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NB4N507ADR2G [ONSEMI]

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