NB3H60113GH2MTR2G [ONSEMI]
3.3 V OmniClock Generator with Single Ended LVCMOS Output;
| 型号： | NB3H60113GH2MTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V OmniClock Generator with Single Ended LVCMOS Output |
| 文件： | 总11页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V OmniClock Generator
with Single Ended LVCMOS
Output
NB3H60113GH2
The NB3H60113GH2, which is a member of the OmniClock family,
is a low power PLL−based clock generator. The device accepts
a single ended LVCMOS reference clock as input. It generates one
single ended LVCMOS modulated output at CLKOUT. Two LVCMOS
spread select signals SS1% and SS0% select one of the four spread
spectrum options at the output. The device can be powered down using
the Power Down pin (PD#).
www.onsemi.com
WDFN8
CASE 511AT
Features
• Member of the OmniClock Family of Programmable Clock
Generators
MARKING DIAGRAM
• Operating Power Supply: 3.3 V 10%
• I/O Standards:
1
♦ Input: 100 MHz CLKIN
H2MG
♦ Output: 100 MHz Modulated CLKOUT (LVCMOS)
G
• Input Frequency Range:
♦ Reference Clock: 100 MHz (LVCMOS)
• Configurable Spread Spectrum Frequency Modulation Parameters
(Type, Deviation, Rate)
H2 = Specific Device Code
M
G
= Date Code
= Pb−Free Device
• Output Drive Current for Single Ended Output: 16 mA
• Power Saving Mode through Power Down Pin
(Note: Microdot may be in either location)
• Temperature Range −40°C to 85°C
• Packaged in 8−Pin WDFN
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
• These are Pb−Free Devices
Typical Applications
• Display (TV Wall)
VDD
PD#
Output Control
Crystal /Clock Control
Configuration
Memory
Output
Divider
CLKOUT
Frequency and SS
CMOS/
Diff Buffer
PLL Block
Phase
Detector
CLKIN
NC
Clock Buffer/
Crystal
Oscillator
and AGC
Charge
Pump
VCO
SS1%
SS0%
SS%
Select
Feedback
Divider
GND
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
December, 2019 − Rev. 0
NB3H60113GH2/D
NB3H60113GH2
PIN FUNCTION DESCRIPTION
1
CLKIN
NC
SS1%
VDD
8
2
7
NB3H60113GH2
3
4
PD#
GND
6
5
SS0%
CLKOUT
Figure 2. Pin Connections (Top View) – WDFN8
Table 1. PIN DESCRIPTION
Pin No.
Pin Name
CLKIN
NC
Pin Type
Description
1
2
3
Input
Output
Input
100 MHz single ended external reference input clock (LVCMOS)
No connect. Not to be connected to any circuit
PD#
Asynchronous LVCMOS input. Active Low Master Reset to disable the device and set
output Low. Internal pull−down resistor. This pin needs to be pulled High for normal
operation of the chip.
4
5
6
7
8
GND
CLKOUT
SS0%
Ground
Output
Input
Power supply ground
100 MHz Modulated Clock Output Single ended (LVCMOS)
SS% Selection Input (LVCMOS). Default Pin High
3.3 V Power supply
V
DD
Power
Input
SS1%
SS% Selection Input (LVCMOS). Default Pin High
Table 2. POWER DOWN FUNCTION TABLE
PD#
0
Function
Device Powered Down
Device Powered Up
1
Table 3. SPREAD SELECTION
SS1%
SS0%
SS% (+ )
0.125
1.0
0
0
1
0
1
0
1
0.5
1
0.375*
*SS1% = 1, SS0% = 1 is the default condition.
www.onsemi.com
2
NB3H60113GH2
FUNCTIONAL DESCRIPTION
The NB3H60113GH2 is a 3.3 V programmable, single
operation and while in standby. The One−Time
Programmable memory allows programming and storing of
one configuration in the memory space.
ended clock generator, designed to meet the clock
requirements for consumer and portable markets. It has a
small package size and it requires low power during
VDD (3.3 V)
0.01 mF
0.1 mF
1 mF
Reference Clock Input
100 MHz Modulated Output
CLKIN
CLKOUT
VDD
100 MHz
SS1%
NB3H60113GH2
VDD
VDD
PD#
SS0%
GND
Figure 3. Power Supply Noise Suppression and Typical Application Setup
Device Power Supply
Lowering EMI by increasing a signal’s bandwidth is called
‘spread spectrum modulation’. The outputs of the
NB3H60113GH2 has been programmed to have center
spread from 0.125% to 1% The programmable step size
for spread spectrum deviation is 0.125% for center spread.
Additionally, the frequency modulation rate is also
programmable. Frequency modulation of 100 kHz has been
selected. Spread spectrum, when on, applies to all the
outputs of the device. There exists a tradeoff between the
input clock frequency and the desired spread spectrum
profile.
The NB3H60113GH2 is designed to work with a 3.3 V
V
power supply. In order to suppress power supply noise
DD
it is recommended to connect decoupling capacitors of
0.1 mF and 0.01 mF close to the V
pin as shown in
DD
Figure 3.
Clock Input: Input Frequency
The NB3H60113GH2 clock input block is programmed
for a single ended reference clock source of 100 MHz.
Automatic Gain Control (AGC)
The Automatic Gain Control (AGC) feature adjusts the
gain to the input clock based on its signal strength to
maintain a good quality input clock signal level. This feature
takes care of low clock swings fed from external reference
clocks and ensures proper device operation.
Programmable Clock Output:
Output Type and Frequency
The NB3H60113GH2 provides one single−ended
LVCMOS output of 100 MHz with frequency modulation.
Figure 4.
Spread Spectrum Frequency Modulation
Control Inputs
Spread spectrum is a technique using frequency
modulation to achieve lower peak electromagnetic
interference (EMI). It is an elegant solution compared to
techniques of filtering and shielding. Refer Figure 4. The
NB3H60113GH2 modulates the output of its PLL in order
to “spread” the bandwidth of the synthesized clock,
decreasing the peak amplitude at the center frequency and at
the frequency’s harmonics. This results in significantly
lower system EMI compared to the typical narrow band
signal produced by oscillators and most clock generators.
Power Down
Power saving mode can be activated through the power
down PD# input pin. This input is an LVCMOS/LVTTL
active Low Master Reset that disables the device and sets
outputs Low. By default it has an internal pull−down resistor.
The chip functions are disabled by default and when PD# pin
is pulled high the chip functions are activated. Refer
Figure 8.
www.onsemi.com
3
NB3H60113GH2
Configuration Space
NB3H60113GH2 has one Configuration. Table 4 shows the device configuration.
Table 4. DEVICE CONFIGURATION
Output
Inversion
Output
Enable
Input Frequency
Output Frequency
V
DD
SS%
SS Mod Rate
Output Drive
100MHz
CLK0 = 100 MHz
3.3 V
0.375
100 kHz
CLK0 = 16 mA
CLK0 = N
CLK0 = Y
Table 5. ATTRIBUTES
Characteristics
Value
ESD Protection Human Body Model
2 kV
50 kW
MSL1
Internal Input Default State Pull Up/Down Resistor
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
130 k
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 6. ABSOLUTE MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Rating
Unit
V
Positive Power Supply with Respect to Ground
Input Voltage with Respect to Chip Ground
Output Voltage with Respect to Chip Ground
−0.5 to +4.6
V
V
DD
V
−0.5 to V + 0.5
DD
I
V
OUT
−0.5 to V + 0.5
V
DD
T
Operating Ambient Temperature Range (Industrial Grade)
Storage Temperature
−40 to +85
−65 to +150
265
°C
°C
°C
°C/W
A
T
STG
SOL
T
Max. Soldering Temperature (10 s)
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
q
JA
129
84
Thermal Resistance (Junction−to−Case)
35 to 40
125
q
°C/W
°C
JC
T
Junction Temperature
J
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
2
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). ESD51.7 type board. Back side Copper heat spreader area 100 mm , 2 oz
(0.070 mm) copper thickness.
Table 7. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Condition
3.3 V operation
Min
Typ
Max
Unit
V
V
DD
Core Power Supply Voltage
2.97
3.3
3.63
C
Clock Output Load Capacitance for
LVCMOS Clock
f
f
< 100 MHz
≥ 100 MHz
15
5
pF
L
out
out
fclkin
Reference Clock Frequency
Single ended clock Input
100
MHz
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
4
NB3H60113GH2
Table 8. DC ELECTRICAL CHARACTERISTICS (V = 3.3V 10%, GND = 0 V, T = −40°C to 85°C, Notes 4, 5)
DD
A
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I
_
Power Supply Current for Core
Configuration Dependent. V = 3 V,
DD
A
CLKOUT = 100 MHz, 16 mA output
drive
25
mA
DD 3.3V
T = 25°C, CLKIN = 100 MHz,
Power Down Supply Current
Input HIGH Voltage
PD# is Low to make all outputs OFF,
SS default
20
I
mA
PD
V
V
Pin XIN
Pin PD#
Pin XIN
Pin PD#
0.65 V
V
DD
IH
DD
0.85 V
V
DD
DD
Input LOW Voltage
V
V
0
0
0.35 V
IL
DD
0.15 V
DD
Zo
Nominal Output Impedance
22
Configuration Dependent. 16 mA
drive
W
Internal Pull Up/ Pull Down Resistor
Input Capacitance
R
kW
V
= 3.3 V
50
4
PUP/PD
DD
Cin
Pin PD#
6
pF
LVCMOS OUTPUT
Output HIGH Voltage
0.75 V
V
V
V
OH
V
V
= 3.3 V, I = 16 mA
DD
OH
DD
Output LOW Voltage
= 3.3 V, I = 16 mA
0.25 V
V
OL
DD
OL
DD
I
Configuration Dependent. T = 25°C,
6.5
LVCMOS Output
Supply Current
mA
DD_LVCMOS
A
CLKOUT = fout in PLL bypass mode,
measured on V = 3.3 V,
DD
L
f
= 100 MHz, C = 5 pF
out
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Measurement taken with single ended clock outputs terminated with test load capacitance of 5 pF and 15 pF. See Figure 5. Specification for
LVTTL are valid for the V 3.3 V only.
DD
5. Parameter guaranteed by design verification not tested in production.
Table 9. AC ELECTRICAL CHARACTERISTICS (V = 3.3V 10%, GND = 0 V, T = −40°C to 85°C, Notes 6, 8 and 9)
DD
A
Symbol
Parameter
Condition
Min
Typ
100
Max
Unit
MHz
kHz
%
fout
Single Ended Output Frequency
Spread Spectrum Modulation Rate
f
fclkin ≥ 6.75 MHz
100
MOD
SS
Percent Spread Spectrum
(deviation from nominal frequency)
Center Spread
0.375
SSstep
Percent Spread Spectrum Change
Step Size
Center Spread step size
0.125
3.0
3.0
0
%
ms
t
t
Stabilization Time from Power−up
V
= 3.3V with Frequency
PU
DD
Modulation
Stabilization Time from Power Down Time from falling edge on PD# pin to
ms
PD
tri−stated outputs (Asynchronous)
Eppm
Synthesis Error
Configuration Dependent
ppm
www.onsemi.com
5
NB3H60113GH2
Table 9. AC ELECTRICAL CHARACTERISTICS (V = 3.3V 10%, GND = 0 V, T = −40°C to 85°C, Notes 6, 8 and 9)
DD
A
Symbol
Parameter
Condition
Min
Typ
Max
Unit
SINGLE ENDED OUTPUTS
Configuration Dependent.
100 MHz CLKIN input,
ps
t
Period Jitter Peak−to−Peak
Cycle−Cycle Peak Jitter
90
JITTER−3.3V
f
= 100 MHz, SS min ( 0.125)
out
(Notes 7, 9 and 10, see Figure 7)
Configuration Dependent.
100 MHz CLKIN input,
60
f
= 100 MHz, SS default
out
(Notes 7, 9 and 10, see Figure 7)
Measured between 20% to 80% with
1
Rise/Fall Time
ns
%
tr/tf
15 pF load, f = 100 MHz,
out
V
DD
= 3.3V, Max Drive
V
= 3.3V Duty Cycle of Ref clock
40
50
60
Output Clock Duty Cycle
t
DD
DC
is 50%
Reference Clock
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Measurement taken with single ended clock outputs terminated with test load capacitance of 5 pF and 15 pF. See Figure 5. Specification for
LVTTL are valid for the V 3.3 V only.
DD
7. Measurement taken from single−ended waveform.
8. Parameter guaranteed by design verification not tested in production.
9. AC performance parameters like jitter change based on the output frequency, spread selection, power supply and loading conditions of the
output. For application specific AC performance parameters, please contact ON Semiconductor.
10.Period jitter Sampled with 10,000 cycles, Cycle−cycle jitter sampled with 1,000 cycles. Jitter measurement may vary. Actual jitter is
dependent on Input jitter and edge rate, number of active outputs, inputs and output frequencies, supply voltage, temperature, and output
load.
PARAMETER MEASUREMENT TEST CIRCUITS
Measurement
Equipment
CLKx
Hi−Z Probe
CL
LVCMOS Clock
Figure 5. LVCMOS Parameter Measurement
www.onsemi.com
6
NB3H60113GH2
TIMING MEASUREMENT DEFINITIONS
t
2
t = 100 × t / t
DC 1 2
t
1
80% of VDD
50% of VDD
20% of VDD
GND
LVCMOS
Clock Output
t
f
t
r
Figure 6. LVCMOS Measurement for AC Parameters
t
period−jitter
50% of CLK Swing
Clock
Output
t
t
(N+1)cycle
Ncycle
50% of CLK Swing
Clock
Output
t
= t
−t
(N+1)cycle Ncycle (over 1000 cycles)
CTC−jitter
−
Tpower−down
Tpower−up
VIH
PD#
VIL
CLK Output
Figure 8. Output Enable/Disable and Power Down Functions
www.onsemi.com
7
NB3H60113GH2
APPLICATION GUIDELINES
LVCMOS Interface
LVCMOS output swings rail−to−rail up to V supply
Cload includes the load capacitor connected to the output,
the pin capacitor posed by the output pin (typically 5 pF) and
the cap load posed by the receiver input pin.
DD
and can drive up to 15 pF load at max 16 mA. The
NB3H60113GH2 is programmed for max drive of 16 mA.
The load current consists of the static current component
(varies with drive) and dynamic current component. For any
supply voltage, the dynamic load current range per
LVCMOS output can be approximated by formula:
Cload + (CL ) Cpin ) Cin)
(eq. 2)
Output Interface and Terminations
The NB3H60113GH2 consists of a unique Single ended
Output Driver to support LVCMOS standard. Termination as
required must be considered and taken care of by the system
designer. An optional series resistor Rs can be connected at
the output for impedance matching, to limit the overshoots
and ringing.
IDD + fout @ Cload @ VDD
(eq. 1)
Figure 9. Simplified LVCMOS Output Structure
Field Programming Kit and Software
transition time (slew rate) and due to impedance mismatch.
Impedance matching with proper termination is required to
reduce the signal reflections. The amplitude of overshoots is
due to the difference in impedance and can be minimized by
adding a series resistor (Rs) near the output pin. Greater the
difference in impedance, greater is the amplitude of the
overshoots and subsequent ripples. The ripple frequency is
dependent on the signal travel time from the receiver to the
source. Shorter traces results in higher ripple frequency, as
the trace gets longer the travel time increases, reducing the
ripple frequency. The ripple frequency is independent of
signal frequency, and only depends on the trace length and
the propagation delay.
For eg. on an FR4 PCB with approximately 150 ps/inch of
propagation rate, on a 2 inch trace, the ripple frequency = 1/
(150 ps × 2 inch × 5) = 666.6 MHz; [5 = number of times the
signal travels, 1 trip to receiver plus 2 additional round trips]
PCB traces should be terminated when trace length tr/f /
(2 × tprate); tr/f = rise/fall time of signal, tprate =
propagation rate of trace.
The NB3H60113GH2 is programmed using the ‘Clock
Cruiser Programmable Clock Kit’. This device uses the 8L
daughter card on the hardware kit. To design a new clock,
‘Clock Cruiser Software’ is required to be installed from the
ON Semiconductor website. The user manuals for the
hardware kit Clock Cruiser Programmable Clock Kit and
Clock Cruiser Software can be found following the link
www.onsemi.com.
Recommendation for Clock Performance
Clock performance is specified in terms of Jitter in time
domain and Phase noise in frequency domain.
Details and measurement techniques of Cycle−cycle
jitter, period jitter, TIE jitter and Phase Noise are explained
in application note AND8459/D. In order to have a good
clock signal integrity for minimum data errors, it is
necessary to reduce the signal reflections. Reflection
coefficient can be zero only when the source impedance
equals the load impedance. Reflections are based on signal
www.onsemi.com
8
NB3H60113GH2
PCB Design Recommendation
source or the receiver. In an optimum layout all components
are on the same side of the board, minimizing vias through
other signal layers.
For a clean clock signal waveform it is necessary to have
a clean power supply for the device. The device must be
isolated from system power supply noise. A 0.1 mF and
a 2.2 mF decoupling capacitor should be mounted on the
component side of the board as close to the V
pin as
DD
possible. No vias should be used between the decoupling
capacitor and V pin. The PCB trace to V pin and the
DD
DD
ground via should be kept thicker and as short as possible.
All the V pins should have decoupling capacitors.
DD
Stacked power and ground planes on the PCB should be
large. Signal traces should be on the top layer with minimum
vias and discontinuities and should not cross the reference
planes. The termination components must be placed near the
Figure 10. Signal Reflection Components
ORDERING INFORMATION
†
Part Number
Case
Package
Shipping
NB3H60113GH2MTR2G
511AT
WDFN8
(Pb−Free)
3,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT−01
ISSUE O
DATE 26 FEB 2010
SCALE 4:1
L
L
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
L1
PIN ONE
REFERENCE
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
2X
0.10
C
A1
A3
b
0.20 REF
2X
0.10
C
0.20
0.30
EXPOSED Cu
MOLD CMPD
TOP VIEW
2.00 BSC
2.00 BSC
0.50 BSC
D
E
e
DETAIL B
L
0.40
---
0.50
0.60
0.15
0.70
0.05
C
L1
L2
DETAIL B
A
ALTERNATE
CONSTRUCTIONS
GENERIC
MARKING DIAGRAM*
8X
0.05
C
A1
A3
SIDE VIEW
SEATING
PLANE
C
1
XXMG
G
e/2
e
DETAIL A
7X
L
XX = Specific Device Code
4
1
M
= Date Code
L2
G
= Pb−Free Device
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
8
5
8X
b
0.10
C
A
B
RECOMMENDED
SOLDERING FOOTPRINT*
NOTE 3
0.05
C
BOTTOM VIEW
7X
0.78
PACKAGE
OUTLINE
2.30
0.88
1
0.50
PITCH
8X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON48654E
WDFN8, 2X2, 0.5 P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
©2020 ICPDF网 联系我们和版权申明