N256S0830HDAT2-20I [ONSEMI]
32KX8 STANDARD SRAM, PDSO8, 4.40 MM, GREEN, PLASTIC, TSSOP-8;
| 型号： | N256S0830HDAT2-20I |
| 厂家： | 
ONSEMI |
| 描述： | 32KX8 STANDARD SRAM, PDSO8, 4.40 MM, GREEN, PLASTIC, TSSOP-8 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMI Semiconductor, Inc.
IMD - Medical Business Unit
650 N. Mary Ave.
N256S0818HDA/N256S0830HDA
Sunnyvale, CA 94085
PH: 408-962-1900, FAX: 408-962-1997
256Kb Low Power Serial SRAMs
32K × 8 bit Organization
Overview
Features
The AMI Semiconductor serial SRAM family
includes several integrated memory devices
including this 256Kb serially accessed Static
Random Access Memory, internally organized as
32K words by 8 bits. The devices are designed and
fabricated using AMI’s advanced CMOS
• Power Supply Options
1.8V and 3.3V
• Very low standby current
Typical Isb as low as 200nA
• Very low operating current
As low as 3mA
technology to provide both high-speed
performance and low power. The devices operate
with a single chip select (CS) input and use a
simple Serial Peripheral Interface (SPI) serial bus.
A single data in and data out line is used along with
a clock to access data within the devices. The
N256S08xxHDA devices include a HOLD pin that
allows communication to the device to be paused.
While paused, input transitions will be ignored.
The devices can operate over a wide temperature
• Simple memory control
Single chip select (CS)
Serial input (SI) and serial output (SO)
• Flexible operating modes
Word read and write
Page mode (32 word page)
Burst mode (full array)
• Organization
32K x 8 bit
o
o
range of -40 C to +85 C and can be available in
• Self timed write cycles
several standard package offerings.
• Built-in write protection (CS high)
• HOLD pin for pausing communication
• High reliability
Unlimited write cycles
• RoHS Compliant Packages
Green SOIC and TSSOP
Device Options
Typical
Power
Speed
Read/Write
Part Number
Density
Feature
Standby
Current
Supply (V)
(MHz)
Operating Current
N256S0818HDA
N256S0830HDA
1.8
3.0
16
20
200nA
1uA
256Kb
HOLD
3 mA @ 1Mhz
Stock No. 23476-H
The specification is subject to change without notice.
1
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
Pin Names
Package Configurations
Pin Name
Pin Function
1
8
7
6
5
CS
SO
NC
VCC
HOLD
SCK
SI
CS
SCK
SI
SO
HOLD
NC
Chip Select Input
Serial Clock Input
Serial Data Input
Serial Data Output
Hold Input
2
3
4
VSS
No Connect
Power
Ground
1
8
7
6
5
VCC
VSS
CS
SO
NC
VCC
HOLD
SCK
SI
2
3
4
VSS
Functional Block Diagram
SCK
Clock
Circuitry
HOLD
Decode
Logic
CS
SI
SRAM
Array
Data In
Receiver
Data Out
Buffer
SO
Stock No. 23476-H
The specification is subject to change without notice.
2
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
1
Absolute Maximum Ratings
Item
Symbol
VIN,OUT
VCC
Rating
–0.3 to VCC+0.3
–0.3 to 4.5
500
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
PD
mW
oC
oC
oC
TSTG
Storage Temperature
–40 to 125
TA
Operating Temperature
-40 to +85
260oC, 10sec
TSOLDER
Soldering Temperature and Time
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Typ1
Item
Symbol
Test Conditions
Min.
Max
Unit
VCC
VCC
VIH
Supply Voltage
Supply Voltage
1.8V Device
3V Device
1.7
2.7
0.7 x VCC
1.95
3.6
VCC+0.3
0.8
V
V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
V
VIL
–0.3
VCC–0.5
V
VOH
VOL
ILI
IOH = -0.4mA
IOL = 1mA
V
0.2
0.5
0.5
3
V
CS = VCC, VIN = 0 to VCC
CS = VCC, VOUT = 0 to VCC
F = 1MHz, IOUT = 0
F = 10MHz, IOUT = 0
F = fCLK MAX, IOUT = 0
µA
µA
mA
mA
mA
nA
ILO
ICC1
ICC2
ICC3
Read/Write Operating
Current
6
10
500
1.8V Device
CS = VCC, VIN = VSS or VCC
200
1
ISB
Standby Current
3V Device
CS = VCC, VIN = VSS or VCC
4
µA
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and are not 100% tested.
1
Capacitance
Item
Symbol
CIN
Test Condition
Min
Max
7
Unit
pF
VIN = 0V, f = 1 MHz, TA = 25oC
VIN = 0V, f = 1 MHz, TA = 25oC
Input Capacitance
I/O Capacitance
CI/O
7
pF
1. These parameters are verified in device characterization and are not 100% tested
Stock No. 23476-H
The specification is subject to change without notice.
3
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
Timing Test Conditions
Item
0.1VCC to 0.9 VCC
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
5ns
0.5 VCC
CL = 100pF
-40 to +85 oC
Operating Temperature
Timing
1.8V Device
Min. Max.
3V Device
Item
Symbol
Units
Min.
Max.
fCLK
tR
Clock Frequency
Clock Rise Time
Clock Fall Time
Clock High Time
Clock Low Time
Clock Delay Time
CS Setup Time
CS Hold Time
16
2
20
2
MHz
us
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tF
2
2
tHI
32
32
32
32
50
32
5
25
25
25
25
50
25
5
tLO
tCLD
tCSS
tCSH
tCSD
tSCS
tSU
tHD
tV
CS Disable Time
SCK to CS
Data Setup Time
Data Hold Time
10
10
10
10
Output Valid From Clock Low
Output Hold Time
32
20
25
20
tHO
tDIS
tHS
tHH
tHZ
tHV
0
0
Output Disable Time
HOLD Setup Time
10
10
10
10
10
10
HOLD Hold Time
HOLD Low to Output High-Z
HOLD High to Output Valid
50
50
Stock No. 23476-H
The specification is subject to change without notice.
4
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
Serial Input Timing
t
CSD
t
CS
CLD
t
t
t
CSH
R
F
t
t
SCS
CSS
SCK
t
t
HD
SU
MSB in
LSB in
SI
SO
High-Z
Serial Output Timing
CS
t
t
HI
LO
t
CSH
SCK
t
V
t
DIS
SO
MSB out
LSB out
SI
Don’t Care
Hold Timing
CS
t
t
HH
HS
t
t
HS
SCK
t
HH
HV
SO
SI
n+2
n+1
n
High-Z
n
n-1
t
t
SU
HZ
Don’t Care
n
n-1
n+2
n+1
n
HOLD
Stock No. 23476-H
The specification is subject to change without notice.
5
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
Control Signal Descriptions
Signal
Name
I/O
Description
A low level selects the device and a high level puts the device in standby mode. If
CS is brought high during a program cycle, the cycle will complete and then the
device will enter standby mode. When CS is high, SO is in high-Z. CS must be
driven low after power-up prior to any sequence being started.
CS
Chip Select
I
Synchronizes all activities between the memory and controller. All incoming
addresses, data and instructions are latched on the rising edge of SCK. Data out is
updated on SO after the falling edge of SCK.
SCK
Serial Clock
I
SI
SO
Serial Data In
Serial Data Out
I
O
Receives instructions, addresses and data on the rising edge of SCK.
Data is transferred out after the falling edge of SCK.
A high level is required for normal operation. Once the device is selected and a
serial sequence is started, this input may be taken low to pause serial communica-
tion without resetting the serial sequence. The pin must be brought low while SCK
is low for immediate use. If SCK is not low, the Hold function will not be invoked
until the next SCK high to low transition. The device must remain selected during
this sequence. SO is high-Z during the Hold time and SI and SCK are inputs are
ignored. To resume operations, HOLD must be pulled high while the SCK pin is
low.
HOLD
Hold
I
Lowering the HOLD input at any time will take to SO output to High-Z.
Functional Operation
Basic Operation
The 256Kb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI)
common on many standard micro-controllers. It may also interface with other non-SPI ports by
programming discrete I/O lines to operate the device.
The serial SRAM contains an 8-bit instruction register and is accessed via the SI pin. The CS pin must be
low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of
SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the
device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it
was held.
The following table contains the possible instructions and formats. All instructions, addresses and data are
transferred MSB first and LSB last.
Instruction Set
Instruction
Instruction Format
Description
READ
WRITE
RDSR
WRSR
0000 0011
0000 0010
0000 0101
0000 0001
Read data from memory starting at selected address
Write data to memory starting at selected address
Read status register
Write status register
Stock No. 23476-H
The specification is subject to change without notice.
6
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
READ Operations
The serial SRAM READ is selected by enabling CS low. First, the 8-bit READ instruction is transmitted to
the device followed by the 16-bit address with the MSB being a don’t care. After the READ instruction and
addresses are sent, the data stored at that address in memory is shifted out on the SO pin after the output
valid time from the clock edge.
If operating in page mode, after the initial word of data is shifted out, the data stored at the next memory
location on the page can be read sequentially by continuing to provide clock pulses. The internal address
pointer is automatically incremented to the next higher address on the page after each word of data is read
out. This can be continued for the entire page length of 32 words long. At the end of the page, the
addresses pointer will be wrapped to the 0 word address within the page and the operation can be
continuously looped over the 32 words of the same page.
If operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory
location can be read sequentially by continuing to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address after each word of data is read out. This can be
continued for the entire array and when the highest address is reached (7FFFh), the address counter
wraps to the address 0000h. This allows the burst read cycle to be continued indefinitely.
All READ operations are terminated by pulling CS high.
Word READ Sequence
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
Instruction
16-bit address
SI
0
0
0
0
0
0
1
1
15 14 13 12
2
1
0
Data Out
High-Z
7
6
5
4
3
2
1
0
SO
Stock No. 23476-H
The specification is subject to change without notice.
7
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
Page and Burst READ Sequence
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
Instruction
16-bit address
SI
0
0
0
0
0
0
1
1
15 14 13 12
2
1
0
Don’t Care
ADDR 1
Data Out from ADDR 1
High-Z
7
6
5
4
3
2
1
0
SO
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Don’t Care
Data Out from ADDR 3
Data Out from ADDR 2
Data Out from ADDR n
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
...
Page READ Sequence
SI
16-bit address
Page address (X)
Word address (Y)
Data Words: sequential, at the end of the page the
address wraps back to the beginning of the page
SO
Page X
Word Y
Page X
Word Y+1 Word Y+2
Page X
Page X
Word 31 Word 0
Page X
Page X
Word 1
Burst READ Sequence
SI
Data Words: sequential, at the end of the page the address wraps to the beginning
of the page and continues incrementing up to the starting word address. At that
time, the address increments to the next page and the burst continues.
16-bit address
Page address (X)
Word address (Y)
. . .
. . .
SO
Page X
Word Y
Page X
Word Y+1
Page X
Word 31 Word 0
Page X
Page X
Word 1
Page X
Word Y-1 Word Y
Page X+1 Page X+1
Word Y+1
Stock No. 23476-H
The specification is subject to change without notice.
8
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
WRITE Operations
The serial SRAM WRITE is selected by enabling CS low. First, the 8-bit WRITE instruction is transmitted
to the device followed by the 16-bit address with the MSB being a don’t care. After the WRITE instruction
and addresses are sent, the data to be stored in memory is shifted in on the SI pin.
If operating in page mode, after the initial word of data is shifted in, additional data words can be written as
long as the address requested is sequential on the same page. Simply write the data on SI pin and
continue to provide clock pulses. The internal address pointer is automatically incremented to the next
higher address on the page after each word of data is written in. This can be continued for the entire page
length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word
address within the page and the operation can be continuously looped over the 32 words of the same
page. The new data will replace data already stored in the memory locations.
If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to
the next sequential memory locations by continuing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address after each word of data is read out. This can be
continued for the entire array and when the highest address is reached (7FFFh), the address counter
wraps to the address 0000h. This allows the burst write cycle to be continued indefinitely. Again, the new
data will replace data already stored in the memory locations.
All WRITE operations are terminated by pulling CS high.
Word WRITE Sequence
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
Data In
Instruction
16-bit address
SI
0
0
0
0
0
0
1
0
15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
...
High-Z
SO
Stock No. 23476-H
The specification is subject to change without notice.
9
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
Page and Burst WRITE Sequence
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
Instruction
16-bit address
SI
0
0
0
0
0
0
1
0
15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
ADDR 1
Data In to ADDR 1
SO
High-Z
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data In to ADDR 2 Data In to ADDR 3
Data In to ADDR n
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
...
High-Z
Page WRITE Sequence
Data Words: sequential, at the end of the page the
address wraps back to the beginning of the page
SI
16-bit address
Page address (X)
Word address (Y)
Page X
Word Y
Page X
Word Y+1 Word Y+2
Page X
Page X
Word 31 Word 0
Page X
Page X
Word 1
SO
High-Z
Burst WRITE Sequence
. . .
. . .
SI
16-bit address
Page address (X)
Word address (Y)
Page X
Word Y
Page X
Word Y+1
Page X
Word 31 Word 0
Page X
Page X
Word 1
Page X
Page X+1 Page X+1
Word Y-1 Word Y Word Y+1
Data Words: sequential, at the end of the page the address wraps to the beginning of the page and
continues incrementing up to the starting word address. At that time, the address increments to the
next page and the burst continues.
SO
High-Z
Stock No. 23476-H
The specification is subject to change without notice.
10
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
WRITE Status Register Instruction (WRSR)
This instruction provides the ability to write the status register and select among several operating modes.
Several of the register bits must be set to a low ‘0’ if any of the other bits are written. The timing sequence
to write to the status register is shown below, followed by the organization of the status register.
WRITE Status Register Sequence
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Instruction
Status Register Data In
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
High-Z
SO
Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mode
0 0 = Word Mode
(Default)
Reserved
Must = 0
Reserved
Must = 0
Hold Function
0 = Hold (Default)
1 = No Hold
1 0 = Page Mode
0 1 = Burst Mode
1 1 = Reserved
Stock No. 23476-H
The specification is subject to change without notice.
11
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
READ Status Register Instruction (RDSR)
This instruction provides the ability to read the Status register. The register may be read at any time by
performing the following timing sequence.
READ Status Register Instruction (RDSR)
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Instruction
0
0
0
0
0
1
0
1
SI
Status Register Data Out
High-Z
7
6
5
4
3
2
1
0
SO
Power-Up State
The serial SRAM enters a know state at power-up time. The device is in low-power standby state with CS
= 1. A low level on CS is required to enter a active state.
Stock No. 23476-H
The specification is subject to change without notice.
12
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
8-Lead Plastic Small Outline, 150mil SOIC
E
E1
p
D
α
B
A2
A1
A
h
45o
c
φ
β
L
Parameter
Sym
Min
Nom
Max
Pin Pitch
Overall height
Molded Package Thickness
Standoff
p
A
A2
A1
E
E1
D
h
1.27
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.35
1.32
0.10
5.79
3.71
4.80
0.25
0.48
0
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
L
Foot Angle
φ
Lead Thickness
Lead Width
c
B
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
Mold Draft Angle Top
α
β
Mold Draft Angle Bottom
0
12
15
Note:
1. All dimensions in Millimeters
2. Package dimensions exclude mold flash and protusions.
Stock No. 23476-H
The specification is subject to change without notice.
13
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
8-Lead Plastic Thin Shrink Small Outline, 4.4 mm TSSOP
E
E1
p
D
B
α
A2
A1
A
c
φ
β
L
Parameter
Sym
Min
Nom
Max
Pin Pitch
Overall height
Molded Package Thickness
Standoff
p
A
A2
A1
E
E1
D
L
0.65
1.10
0.95
0.15
6.50
4.50
3.10
0.70
8
0.85
0.05
6.25
4.30
2.90
0.50
0
0.90
0.10
6.38
4.40
3.00
0.60
4
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
φ
Lead Thickness
Lead Width
c
B
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Mold Draft Angle Top
α
β
Mold Draft Angle Bottom
0
5
10
Note:
1. All dimensions in Millimeters
2. Package dimensions exclude mold flash and protusions.
Stock No. 23476-H
The specification is subject to change without notice.
14
N256S0818HDA/N256S0830HDA
AMI Semiconductor, Inc.
Ordering Information
N256S08 XX XX A X- XX I
16 = 16MHz (1.8V device)
20 = 20MHz (3V device)
Performance
S2 = Green SOIC (RoHS Compliant)
T2 = Green TSSOP (RoHS Compliant)
Package
HD = Hold Function Input
Function
18 = 1.8V
30 = 3V
Voltage
Revision History
Revision #
Date
Change Description
A
B
C
D
October 2005
January 2006
January 2006
January 2006
Initial advance release
Separated density, removed write protection and added page and burst modes
Changed packages to green type
Changed TSSOP pinout to match SOIC
Split x8 and x16 devices
Converted to AMI Semiconductor
E
September 2006
F
May 2007
Updated DC parameters
G
October 2007
Maximum frequency changed to 16MHz for 1.8V device
Removed ADVANCE from datasheet
H
January 2008
Changed AMIS address
© 2006-2008 AMI Semiconductor, Inc. All rights reserved.
AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-
poses only and they vary depending upon specific applications.
AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of
any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be
expected to result in significant injury or death, including life support systems and critical medical instruments.
Stock No. 23476-H
The specification is subject to change without notice.
15
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