MT9V032C12STC [ONSEMI]
MT9V032C12STC;
| 型号： | MT9V032C12STC |
| 厂家： | 
ONSEMI |
| 描述： | MT9V032C12STC |
| 文件： | 总13页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Features
1/3-Inch Wide-VGA CMOS Digital Image
Sensor
MT9V032C12STM (Monochrome, Pb-Free)
MT9V032C12STC (Color, Pb-Free)
Table 1:
Key Performance Parameters
Value
Features
®
®
•
•
Micron DigitalClarity CMOS imaging technology
Parameter
Array format: Wide-VGA, active 752H x 480V
(360,960 pixels)
Optical format
Active imager size
1/3-inch
4.51mm(H) x 2.88mm(V)
5.35mm diagonal
752H x 480V
6.0µm x 6.0µm
Monochrome or color RGB
Bayer pattern
Global shutter—TrueSNAP™
26.6 MPS/26.6 MHz
•
•
Global shutter photodiode pixels; simultaneous
integration and readout
Monochrome or color: Near_IR enhanced
performance for use with non-visible NIR
illumination
Active pixels
Pixel size
Color filter array
•
•
•
•
•
Readout modes: Progressive or interlaced
Shutter efficiency: >99%
Simple two-wire serial interface
Shutter type
Maximum data rate/
master clock
Full resolution
Frame rate
ADC resolution
Responsivity
Register lock capability
752 x 480
Window size: User programmable to any smaller
format (QVGA, CIF, QCIF, and so on). Data rate can
be maintained independent of window size
Binning: 2 x 2 and 4 x 4 of the full resolution
ADC: On-chip, 10-bit column-parallel (option to
operate in 12-bit to 10-bit companding mode)
Automatic controls: Auto exposure control (AEC)
and auto gain control (AGC); variable regional and
variable weight AEC/AGC
60 fps (at full resolution)
10-bit column-parallel
4.8 V/lux-sec (550nm)
>55dB linear;
>80−100dB in HiDy mode
3.3V +0.3V (all supplies)
<320mW at maximum data
rate; 100µW standby current
•
•
Dynamic range
Supply voltage
Power consumption
•
Operating temperature –30°C to +70°C
Packaging
Output gain
Read noise
Dark current
•
•
Support for four unique serial control register IDs to
control multiple imagers on the same bus
Data output formats:
48-pin CLCC
15.3 e-/LSB
25 e-PRMS at 1X
9,042 e-/pix/s at 55°C
•
Single sensor mode:
10-bit parallel/stand-alone
8-bit or 10-bit serial LVDS
Ordering Information
•
Stereo sensor mode:
Interspersed 8-bit serial LVDS
Table 2:
Available Part Numbers
Description
48-pin CLCC (mono)
Part Number
Applications
•
•
•
•
•
•
•
•
Security
MT9V032C12STM ES
MT9V032C12STC ES
High dynamic range imaging
Unattended surveillance
Stereo vision
Video as input
Machine vision
Automation
48-pin CLCC (color)
MT9V032C12STMD ES Demo kit (mono)
MT9V032C12STMH ES Demo kit headboard only
(mono)
MT9V032C12STCD ES
MT9V032C12STCH ES
Demo kit (color)
Demo kit headboard only (color)
Traffic camera
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MT9V032_LDS_1.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
1
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
General Description
General Description
The Micron Imaging MT9V032 is a 1/3-inch wide-VGA format CMOS active-pixel digital
image sensor with global shutter and high dynamic range (HDR) operation. The sensor
has specifically been designed to support the demanding interior and exterior unat-
tended surveillance imaging needs, which makes this part ideal for a wide variety of
imaging applications in real-world environments.
This wide-VGA CMOS image sensor features DigitalClarity⎯Micron’s breakthrough
low-noise CMOS imaging technology that achieves CCD image quality (based on signal-
to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and
integration advantages of CMOS.
The active imaging pixel array is 752H x 480V. It incorporates sophisticated camera
functions on-chip—such as binning 2 x 2 and 4 x 4, to improve sensitivity when oper-
ating in smaller resolutions—as well as windowing, column and row mirroring. It is
programmable through a simple two-wire serial interface.
The MT9V032 can be operated in its default mode or be programmed for frame size,
exposure, gain setting, and other parameters. The default mode outputs a wide-VGA-
size image at 60 frames per second (fps).
An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolu-
tion companded for 10-bits for small signals can be alternatively enabled, allowing more
accurate digitization for darker areas in the image.
In addition to a traditional, parallel logic output the MT9V032 also features a serial low-
voltage differential signaling (LVDS) output. The sensor can be operated in a stereo-
camera mode, and the sensor, designated as a stereo-master, is able to merge the data
from itself and the stereo-slave sensor into one serial LVDS stream.
Figure 1:
Block Diagram
Serial
Register
I/O
Control Register
Active-Pixel
Sensor (APS)
Array
752H x 480V
Timing and Control
Analog Processing
ADCs
Parallel
Video
Digital Processing
Data Out
Serial Video
LVDS Out
Slave Video LVDS In
(for stereo applications only)
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
General Description
Figure 2:
MT9V032 Quantum Efficiency vs. Wavelength
Blue
40
35
30
25
20
15
10
5
Green (B)
Green (R)
Red
0
350
450
550
650
750
850
950
1050
Wavelength (nm)
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
3
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Pin Descriptions
Pin Descriptions
Figure 3 shows the package pinout for the MT9V032. Table 3 on page 5 provides the pin
descriptions.
Figure 3:
48-Pin CLCC Package Pinout Diagram
6
5
4
3
2
1
48
47
46
45
44
43
42
7
8
D
OUT
OUT
3
4
LVDSGND
BYPASS_CLKIN_N
BYPASS_CLKIN_P
SER_DATAIN_N
SER_DATAIN_P
LVDSGND
41
40
39
38
D
9
VAAPIX
10
11
V
AA
GND
A
37
36
35
34
33
12
13
14
NC
NC
D
GND
DD
VAA
V
15
16
17
18
AGND
DOUT
DOUT
DOUT
DOUT
5
6
7
8
STANDBY
RESET#
32
31
S_CTRL_ADR1
19
20
21
22
23
24
25
26
27
28
29
30
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
4
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Pin Descriptions
Table 3:
Pin Descriptions
Only pins DOUT0 through DOUT9 may be tri-stated
Pin Number
Symbol
Type
Description
Notes
29
10
RSVD
Input
Input
1
Connect to DGND.
SER_DATAIN_N
Serial data in for stereoscopy (differential negative). Tie to
1kΩ pull-up (to 3.3V) in non-stereoscopy mode.
11
8
SER_DATAIN_P
BYPASS_CLKIN_N
BYPASS_CLKIN_P
Input
Input
Input
Serial data in for stereoscopy (differential positive). Tie to
DGND in non-stereoscopy mode.
Input bypass shift-CLK (differential negative). Tie to 1KΩ
pull-up (to 3.3V) in non-stereoscopy mode.
9
Input bypass shift-CLK (differential positive). Tie to DGND
in non-stereoscopy mode.
23
25
EXPOSURE
SCLK
Input
Input
Rising edge starts exposure in slave mode.
Two-wire serial interface clock. Connect to VDD with 1.5K
resistor even when no other two-wire serial interface
peripheral is attached.
28
30
31
32
33
47
24
OE
Input
Input
Input
Input
Input
Input
I/O
2
DOUT enable pad, active HIGH.
S_CTRL_ADR0
S_CTRL_ADR1
RESET#
Two-wire serial interface slave address bit 3.
Two-wire serial interface slave address bit 5.
Asynchronous reset. All registers assume defaults.
Shut down sensor operation for power saving.
Master clock (26.6 MHz).
STANDBY
SYSCLK
SDATA
Two-wire serial interface data. Connect to VDD with 1.5K
resistor even when no other two-wire serial interface
peripheral is attached.
22
26
STLN_OUT
I/O
I/O
Output in master mode—start line sync to drive slave chip
in-phase; input in slave mode.
STFRM_OUT
Output in master mode—start frame sync to drive a slave
chip in-phase; input in slave mode.
20
21
15
16
17
18
19
27
41
42
43
44
45
46
2
LINE_VALID
FRAME_VALID
DOUT5
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Asserted when DOUT data is valid.
Asserted when DOUT data is valid.
Parallel pixel data output 5.
DOUT6
Parallel pixel data output 6.
DOUT7
Parallel pixel data output 7.
DOUT8
Parallel pixel data output 8
DOUT9
Parallel pixel data output 9.
LED_OUT
DOUT4
LED strobe output.
Parallel pixel data output 4.
DOUT3
Parallel pixel data output 3.
DOUT2
Parallel pixel data output 2.
DOUT1
Parallel pixel data output 1.
DOUT0
Parallel pixel data output 0.
PIXCLK
Pixel clock out. DOUT is valid on rising edge of this clock.
Output shift CLK (differential negative).
Output shift CLK (differential positive).
Serial data out (differential negative).
Serial data out (differential positive).
SHFT_CLKOUT_N
SHFT_CLKOUT_P
SER_DATAOUT_N
SER_DATAOUT_P
3
4
5
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
5
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Pin Descriptions
Table 3:
Pin Descriptions (continued)
Only pins DOUT0 through DOUT9 may be tri-stated
Pin Number
Symbol
Type
Description
Notes
1, 14
35, 39
40
VDD
VAA
Supply
Supply
Supply
Supply
Ground
Ground
Ground
NC
Digital power 3.3V.
Analog power 3.3V.
Pixel power 3.3V.
VAAPIX
VDDLVDS
LVDSGND
DGND
6
Dedicated power for LVDS pads.
Dedicated GND for LVDS pads.
Digital GND.
7, 12
13, 48
34, 38
36, 37
AGND
Analog GND.
NC
3
No connect.
Notes: 1. Pin 29 (RSVD) must be tied to GND.
2. Output Enable (OE) tri-states signals DOUT0–DOUT9. No other signals are tri-stated with OE.
3. No connect. These pins must be left floating for proper operation.
Figure 4:
Typical Configuration (Connection)—Parallel Output Mode
V
AA
VAAPIX
VAAPIX
V
DD
VDDLVDS
V
DD
VAA
D
OUT(9:0)
Master Clock
SYSCLK
OE
LINE_VALID
FRAME_VALID
PIXCLK
To Controller
RESET#
EXPOSURE
STANDBY from
Controller or
Digital GND
STANDBY
To LED output
LED_OUT
S_CTRL_ADR0
S_CTRL_ADR1
SCLK
Two-Wire
Serial Interface
SDATA
RSVD
DGND LVDSGND
AGND
0.1μF
Note:
LVDS signals are to be left floating.
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
6
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Electrical Specifications
Electrical Specifications
Table 4:
DC Electrical Characteristics
VPWR = 3.3V 0.3V; TA = Ambient = 25°C
Symbol
Definition
Condition
Min
Typ
Max
Unit
VPWR -0.5
-0.3
–
–
–
VPWR +0.3
0.8
V
V
VIH
VIL
IIN
Input high voltage
Input low voltage
-15.0
15.0
µA
Input leakage current
No pull-up resistor;
VIN = VPWR or VGND
VPWR -0.7
–
–
–
0.3
–
V
V
VOH
Output high voltage
Output low voltage
Output high current
Output low current
Analog power supply
Analog supply current
Digital power supply
Digital supply current
Pixel array power supply
Pixel supply current
LVDS power supply
LVDS supply current
IOH = -4.0mA
–
-9.0
–
VOL
IOL = 4.0mA
–
mA
mA
V
IOH
VOH = VDD - 0.7
VOL = 0.7
–
9.0
3.6
60.0
3.6
60
IOL
3.0
–
3.3
35.0
3.3
35.0
3.3
1.4
3.3
13.0
3
VAA
Default settings
Default settings
Default settings
Default settings, CLOAD= 10pF
Default settings
Default settings
Default settings
Default settings
mA
V
IPWRA
VDD
3.0
–
mA
V
IPWRD
VAAPIX
IPIX
3.0
0.5
3.0
11.0
2
3.6
3.0
3.6
15.0
4
mΑ
V
VLVDS
ILVDS
mA
µA
IPWRA
Analog standby supply current STDBY = VDD
Standby
1
–
2
4
–
µA
IPWRD
Standby
Clock Off
Digital standby supply current STDBY = VDD, CLKIN = 0 MHz
with clock off
1.05
mA
IPWRD
Standby
Clock On
Digital standby supply current STDBY= VDD, CLKIN = 27 MHz
with clock on
Table 5:
Symbol
LVDS Driver DC Specifications
VPWR = 3.3V 0.3V; TA = Ambient = 25°C
Definition
Condition
Min
Typ
Max
Unit
250
–
–
–
400
50
mV
mV
|VOD|
Output differential voltage
|DVOD|
Change in VOD between
complementary output states
RLOAD = 100
1.0
–
1.2
–
1.4
35
mV
mV
VOS
Output offset voltage
DVOS
Change in VOS between
complementary output states
Ω ±1%
±10
±1
±12
±10
mA
µA
IOS
IOZ
Output current when driver
shorted to ground
Output current when driver is
tri-state
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
7
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Electrical Specifications
Table 6:
Symbol
LVDS Receiver DC Specifications
VPWR = 3.3V 0.3V; TA = Ambient = 25°C
Definition
Condition
Min
Typ
Max
Unit
| VGPD| <925mV
-100
–
–
–
100
mV
µA
VIDTH+
Iin
Input differential
Input current
±20
Caution Stresses greater than those listed in Table 7 may cause permanent damage to the device.
Table 7:
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VSUPPLY
ISUPPLY
IGND
-0.3
–
4.5
200
V
mA
mA
V
Power supply voltage (all supplies)
Total power supply current
Total ground current
–
200
VIN
-0.3
-0.3
-40
VDDQ + 0.3
VDDQ + 0.3
+125
DC input voltage
VOUT
TSTG
V
DC output voltage
°C
Storage temperature
Note:
These are stress ratings only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
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8
©2006 Micron Technology, Inc. All rights reserved.
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Package Dimensions
Package Dimensions
Figure 5:
48-Pin CLCC Package Outline Drawing
2.3 0.2
D
A
1.7
Seating
plane
Substrate material: alumina ceramic 0.7 thickness
Wall material: alumina ceramic
Lid material: borosilicate glass 0.55 thickness
8.8
48X R 0.15
1.75
H CTR
Ø0.20 A
0.8
TYP
First
clear
pixel
47X
1.0 0.2
4.4
B C
48
1
48X
0.40 0.05
5.215
4.84
V CTR
Ø0.20 A
10.9 0.1
CTR
11.43
8.8
B C
4.4
5.715
0.8 TYP
Image
sensor die:
0.675 thickness
4X
0.2
Optical
center1
5.215
5.715
Optical
area
A
C
10.9 0.1
CTR
11.43
B
0.05
0.10 A
Optical area:
1.400 0.125
Maximum rotation of optical area relative to package edges: 1º
Maximum tilt of optical area relative to
seating plane A : 50 microns
Lead finish:
Au plating, 0.50 microns
minimum thickness
over Ni plating, 1.27 microns
minimum thickness
0.90
for reference only
0.35
Maximum tilt of optical area relative to
top of cover glass D : 100 microns
for reference only
Notes: 1. Optical center = package center.
2. All dimensions are in millimeters.
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
9
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Appendix A – Serial Configurations
Appendix A – Serial Configurations
With the LVDS serial video output, the deserializer can be up to 8 meters from the
sensor. The serial link can save on the cabling cost of 14 wires (DOUT[9:0], LINE_VALID,
FRAME_VALID, PIXCLK, GND). Instead, just three wires (two serial LVDS, one GND) are
sufficient to carry the video signal.
Configuration of Sensor for Stand-Alone Serial Output with Internal PLL
In this configuration, the internal PLL generates the shift-clk (x12). The LVDS pins
SER_DATAOUT_P and SER_DATAOUT_N must be connected to a deserializer (clocked
at approximately the same system clock frequency).
Figure 6 shows how a standard off-the-shelf deserializer (National Semiconductor
DS92LV1212A) can be used to retrieve the standard parallel video signals of DOUT[9:0],
LINE_VALID and FRAME_VALID.
Figure 6:
Stand-Alone Topology
26.6 MHz
Osc.
CLK
LVDS
SER_DATAIN
Sensor
LVDS
BYPASS_CLKIN
LVDS
SHIFT_CLKOUT
LVDS
SER_DATAOUT
8 meters (maximum)
26.6 MHz
Osc.
DS92LV1212A
8
2
PIXEL LINE_VALID
FRAME_VALID
8-bit configuration shown
Typical configuration of the sensor:
1. Power up sensor.
2. Enable LVDS driver (set R0xB3[4]= 0).
3. De-assert LVDS power-down (set R0xB1[1] = 0.
4. Issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0.
If necessary:
5. Force sync patterns for the deserializer to lock (set R0xB5[0] = 1).
6. Stop applying sync patterns (set R0xB5[0] = 0).
PDF: 09005aef824c9998/Source: 09005aef824c999c
MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
10
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Appendix A – Serial Configurations
Configuration of Sensor for Stereoscopic Serial Output with Internal PLL
In this configuration the internal PLL generates the shift-clk (x18) in phase with the
system-clock. The LVDS pins SER_DATAOUT_P and SER_DATAOUT_N must be
connected to a deserializer (clocked at approximately the same system clock frequency).
Figure 7 shows how a standard off-the-shelf deserializer can be used to retrieve back
DOUT(9:2) for both the master and slave sensors. Additional logic is required to extract
out LINE_VALID and FRAME_VALID embedded within the pixel data stream.
Figure 7:
Stereoscopic Topology
SLAVE
MASTER
26.6 MHz
Osc.
LVDS
SER_DATAIN
LVDS
SER_DATAIN
SENSOR
SENSOR
LVDS
LVDS
BYPASS_CLKIN
BYPASS_CLKIN
LVDS
SHIFT_CLKOUT
LVDS
SHIFT_CLKOUT
LVDS
SER_DATAOUT
LVDS
SER_DATAOUT
5 meters (maximum)
1. PLL in non-bypass mode
1. PLL in bypass mode
2. PLL in x 18 mode (stereoscopy)
26.6 MHz
Osc.
DS92LV16
8
8
PIXEL
FROM
SLAVE
PIXEL
FROM
MASTER
LV and FV are embedded in the data stream
Typical configuration of the master and slave sensors:
1. Power up the sensors.
2. Broadcast WRITE to de-assert LVDS power-down (set R0xB1[1] = 0).
3. Individual WRITE to master sensor putting its internal PLL into bypass mode (set
R0xB1[0] = 1).
4. Broadcast WRITE to both sensors to set the stereoscopy bit (set R0x07[5] = 1).
5. Make sure all resolution, vertical blanking, horizontal blanking, window size, and
AEC/AGC configurations are done through broadcast WRITE to maintain lockstep.
6. Broadcast WRITE to enable LVDS driver (set R0xB3[4] = 0).
7. Broadcast WRITE to enable LVDS receiver (set R0xB2[4] = 0).
8. Individual WRITE to master sensor, putting its internal PLL into bypass mode (set
R0xB1[0] = 1).
9. Individual WRITE to slave sensor, enabling its internal PLL (set R0xB1[0] = 0).
10. Individual WRITE to slave sensor, setting it as a stereo slave (set R0x07[6] = 1).
11. Individual WRITEs to master sensor to minimize the inter-sensor skew (set
R0xB2[2:0], R0xB3[2:0], and R0xB4[1:0] appropriately). Use R0xB7 and R0xB8 to get
lockstep feedback from stereo_error_flag.
12. Broadcast WRITE to issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0).
Note:
The stereo_error_flag is set if a mismatch has occurred at a reserved byte (slave and
master sensor’s codes at this reserved byte must match). If the flag is set, steps 11 and
12 are repeated until the stereo_error_flag remains cleared.
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MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
11
©2006 Micron Technology, Inc. All rights reserved.
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Appendix A – Serial Configurations
Broadcast and Individual Writes for Stereoscopic Topology
In stereoscopic mode, the two sensors are required to run in lockstep. This implies that
control logic in each sensor is in exactly the same state as its pair on every clock. To
ensure this, all inputs that affect control logic must be identical and arrive at the same
time at each sensor.
These inputs include:
•
•
•
•
system clock
system reset
two-wire serial interface clk - SCL
two-wire serial interface data - SDA
Figure 8:
Two-Wire Serial Interface Configuration in Stereoscopic Mode
L
26.6 MHz
Osc.
L
L
S_CTRL_ADR[0]
CLK
S_CTRL_ADR[0]
CLK
SLAVE
SENSOR
MASTER
SENSOR
CLK
SCL
SDA
SCL
SDA
HOST
SCL
SDA
Host launches SCL and SDA on positive
edge of SYSCLK.
All system clock lengths (L) must be equal.
SCL and SDA lengths to each sensor (from the host) must also be equal.
The setup in Figure 8 shows how the two sensors can maintain lockstep when their
configuration registers are written through the two-wire serial interface. A WRITE to
configuration registers would either be broadcast (simultaneous WRITES to both
sensors) or individual (WRITE to just one sensor at a time). READs from configuration
registers would be individual (READs from just one sensor at a time).
One of the two serial interface slave address bits of the sensor is hardwired. The other is
controlled by the host. This allows the host to perform either a broadcast or a one-to-
one access.
Broadcast WRITES are performed by setting the same S_CTRL_ADR input bit for both
slave and master sensor. Individual WRITES are performed by setting opposite
S_CTRL_ADR input bit for both slave and master sensor. Similarly, individual READs are
performed by setting opposite S_CTRL_ADR input bit for both slave and master sensor.
PDF: 09005aef824c9998/Source: 09005aef824c999c
MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
12
©2006 Micron Technology, Inc. All rights reserved.
‡
Preliminary
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
Revision History
Revision History
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/28/2007
Updated package drawing
•
PDF: 09005aef824c9998/Source: 09005aef824c999c
MT9V032_LDS_2.fm - Rev. B 3/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
13
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