MMJT9410T1 [ONSEMI]

NPN 双极功率晶体管;
MMJT9410T1
型号: MMJT9410T1
厂家: ONSEMI    ONSEMI
描述:

NPN 双极功率晶体管

晶体管
文件: 总7页 (文件大小:192K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MMJT9410  
Bipolar Power Transistors  
NPN Silicon  
Features  
SOT223 Surface Mount Packaging  
http://onsemi.com  
Epoxy Meets UL 94 V0 @ 0.125 in  
These Devices are PbFree and are RoHS Compliant  
POWER BJT  
IC = 3.0 AMPERES  
BVCEO = 30 VOLTS  
MAXIMUM RATINGS  
Rating  
CollectorEmitter Voltage  
CollectorBase Voltage  
Symbol Value  
Unit  
Vdc  
Vdc  
Vdc  
Adc  
Adc  
Adc  
V
30  
45  
CEO  
V
CE(sat) = 0.2 VOLTS  
V
CB  
EB  
EmitterBase Voltage  
V
6.0  
1.0  
3.0  
5.0  
Base Current Continuous  
Collector Current Continuous  
Collector Current Peak  
I
B
4
C 2,4  
I
C
C
I
CM  
Total Power Dissipation @ T = 25°C  
P
D
3.0  
24  
W
mW/°C  
W
C
Derate above 25°C  
B
1
C
2
E
3
Total P @ T = 25°C mounted on 1” sq.  
1.7  
D
A
(645 sq. mm) Collector pad on FR4  
B 1  
E 3  
Top View  
Pinout  
bd material  
Schematic  
Total P @ T = 25°C mounted on 0.012” sq.  
0.75  
D
A
(7.6 sq. mm) Collector pad on FR4 bd material  
Operating and Storage Junction  
Temperature Range  
T
T
55 to  
°C  
J, stg  
+150  
MARKING  
DIAGRAM  
4
ESD Human Body Model  
ESD Machine Model  
HBM  
MM  
3B  
C
V
V
1
2
3
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
AYW  
9410G  
G
SOT223  
CASE 318E  
STYLE 1  
1
THERMAL CHARACTERISTICS  
A
Y
W
= Assembly Location  
= Year  
= Work Week  
Characteristic  
Symbol  
Max  
42  
Unit  
°C/W  
°C/W  
Thermal Resistance, JunctiontoCase  
R
q
JC  
Thermal Resistance, JunctiontoAmbient on  
1” sq. (645 sq. mm) Collector pad on FR4 bd  
material  
R
75  
9410 = Device Code  
q
JA  
G
= PbFree Package  
(Note: Microdot may be in either location)  
Thermal Resistance, JunctiontoAmbient on  
0.012” sq. (7.6 sq. mm) Collector pad on  
FR4 bd material  
R
165  
260  
°C/W  
°C  
q
JA  
ORDERING INFORMATION  
Maximum Lead Temperature for Soldering  
Purposes, 1/8” from case for 5 seconds  
T
L
Device  
Package  
Shipping  
MMJT9410G  
SOT223  
(PbFree)  
1000 / Tape & Reel  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
August, 2013 Rev. 7  
MMJT9410/D  
MMJT9410  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
C
Characteristic  
OFF CHARACTERISTICS  
Symbol  
Min  
Typ  
Max  
Unit  
CollectorEmitter Sustaining Voltage  
V
Vdc  
Vdc  
CEO(sus)  
30  
(I = 10 mAdc, I = 0 Adc)  
C
B
EmitterBase Voltage  
(I = 50 mAdc, I = 0 Adc)  
V
EBO  
6.0  
E
C
Collector Cutoff Current  
(V = 25 Vdc, R = 200 W)  
I
mAdc  
CER  
20  
200  
CE  
BE  
(V = 25 Vdc, R = 200 W, T = 125°C)  
CE  
BE  
J
Emitter Cutoff Current  
(V = 5.0 Vdc)  
BE  
I
mAdc  
EBO  
10  
ON CHARACTERISTICS (Note 1)  
CollectorEmitter Saturation Voltage  
(I = 0.8 Adc, I = 20 mAdc)  
V
V
Vdc  
CE(sat)  
0.105  
0.150  
0.150  
0.200  
0.450  
C
B
(I = 1.2 Adc, I = 20 mAdc)  
C
B
(I = 3.0 Adc, I = 0.3 Adc)  
C
B
BaseEmitter Saturation Voltage  
(I = 3.0 Adc, I = 0.3 Adc)  
Vdc  
Vdc  
BE(sat)  
1.25  
1.10  
C
B
BaseEmitter On Voltage  
V
BE(on)  
(I = 1.2 Adc, V = 4.0 Vdc)  
C
CE  
DC Current Gain  
h
FE  
85  
80  
60  
200  
(I = 0.8 Adc, V = 1.0 Vdc)  
C
CE  
(I = 1.2 Adc, V = 1.0 Vdc)  
C
CE  
(I = 3.0 Adc, V = 1.0 Vdc)  
C
CE  
DYNAMIC CHARACTERISTICS  
Output Capacitance  
C
pF  
pF  
ob  
85  
200  
72  
135  
(V = 10 Vdc, I = 0 Adc, f = 1.0 MHz)  
CB  
E
Input Capacitance  
(V = 8.0 Vdc)  
EB  
C
ib  
CurrentGain Bandwidth Product (Note 2)  
(I = 500 mA, V = 10 Vdc, F = 1.0 MHz)  
f
T
MHz  
C
CE  
test  
1. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.  
2. f = |h | f  
T
FE  
test  
0.25  
0.20  
0.15  
0.10  
1.0  
0.75  
0.50  
1.2 A  
I
C
= 3.0 A  
1.2 A  
0.8 A  
0.5 A  
0.8 A  
0.25  
0
0.05  
0
0.5 A  
I
C
= 0.25 A  
10  
0.25 A  
1.0  
10  
100  
1000  
1.0  
100  
1000  
I , BASE CURRENT (mA)  
B
I , BASE CURRENT (mA)  
B
Figure 1. Collector Saturation Region  
Figure 2. Collector Saturation Region  
http://onsemi.com  
2
 
MMJT9410  
1000  
1000  
150°C  
150°C  
25°C  
25°C  
100  
100  
-ꢀ55°C  
-ꢀ55°C  
V
CE  
= 1.0 V  
V
CE  
= 4.0 V  
10  
10  
0.1  
1.0  
10  
0.1  
1.0  
I , COLLECTOR CURRENT (A)  
10  
I , COLLECTOR CURRENT (A)  
C
C
Figure 3. DC Current Gain  
Figure 4. DC Current Gain  
1.0  
10  
I /I = 10  
C B  
V
BE(sat)  
1.0  
V
BE(sat)  
0.1  
V
CE(sat)  
0.1  
V
CE(sat)  
I /I = 50  
C B  
0.01  
0.01  
0.1  
1.0  
10  
0.1  
1.0  
10  
I , COLLECTOR CURRENT (A)  
C
I , COLLECTOR CURRENT (A)  
C
Figure 5. “On” Voltages  
Figure 6. “On” Voltages  
1.2  
0.8  
1000  
100  
10  
-ꢀ55°C  
25°C  
C
ob  
150°C  
0.4  
V
CE  
= 4.0 V  
0
1.0  
0.1  
1.0  
10  
0.1  
1.0  
10  
100  
I , COLLECTOR CURRENT (A)  
C
V , REVERSE VOLTAGE (VOLTS)  
R
Figure 7. VBE(on) Voltage  
Figure 8. Capacitance  
http://onsemi.com  
3
MMJT9410  
10  
100  
0.5 ms  
100 ms  
5.0 ms  
1.0  
0.1  
V
= 10 V  
= 1.0 MHz  
CE  
0.01  
f
test  
BONDING WIRE LIMIT  
THERMAL LIMIT (Single Pulse)  
SECONDARY BREAKDOWN LIMIT  
T = 25°C  
A
0.001  
10  
0.1  
1.0  
10  
100  
0.1  
1.0  
10  
V
CE  
, COLLECTOR-EMITTER VOLTAGE (VOLTS)  
I , COLLECTOR CURRENT (AMP)  
C
Figure 9. CurrentGain Bandwidth Product  
Figure 10. Active Region Safe Operating Area  
4.0  
There are two limitations on the power handling ability of  
a transistor: average junction temperature and secondary  
breakdown. Safe operating area curves indicate I V  
C
CE  
3.0  
2.0  
limits of the transistor that must be observed for reliable  
operation; i.e., the transistor must not be subjected to greater  
dissipation than the curves indicate.  
T
C
The data of Figure 10 is based on T  
= 150°C; T is  
J(pk)  
C
variable depending on conditions. Secondary breakdown  
pulse limits are valid for duty cycles to 10% provided T  
J(pk)  
1.0  
0
v 150°C. T  
may be calculated from the data in  
J(pk)  
Figure 12. At high case temperatures, thermal limitations  
will reduce the power that can be handled to values less than  
the limitations imposed by secondary breakdown.  
T
A
25  
50  
75  
100  
125  
150  
T, TEMPERATURE (°C)  
Figure 11. Power Derating  
1.0  
D = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
0.01  
P
(pk)  
0.01  
R
(t) = r(t) q  
JA  
q
JA  
q
= 165°C/W  
JA  
D CURVES APPLY FOR POWER  
PULSE TRAIN SHOWN  
READ TIME AT t  
SINGLE PULSE  
t
1
0.001  
t
2
1
T
- T = P q (t)  
A (pk) JA  
J(pk)  
DUTY CYCLE, D = t /t  
1
2
0.0001  
0.0001  
0.001  
0.01  
0.1  
t, TIME (seconds)  
1.0  
10  
100  
1000  
Figure 12. Thermal Response  
http://onsemi.com  
4
 
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
SOT223 (TO261)  
CASE 318E04  
ISSUE R  
DATE 02 OCT 2018  
SCALE 1:1  
q
q
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42680B  
SOT223 (TO261)  
PAGE 1 OF 2  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
© Semiconductor Components Industries, LLC, 2018  
www.onsemi.com  
SOT223 (TO261)  
CASE 318E04  
ISSUE R  
DATE 02 OCT 2018  
STYLE 1:  
PIN 1. BASE  
2. COLLECTOR  
3. EMITTER  
4. COLLECTOR  
STYLE 2:  
PIN 1. ANODE  
STYLE 3:  
STYLE 4:  
PIN 1. SOURCE  
STYLE 5:  
PIN 1. DRAIN  
PIN 1. GATE  
2. DRAIN  
2. CATHODE  
3. NC  
2. DRAIN  
3. GATE  
4. DRAIN  
2. GATE  
3. SOURCE  
4. DRAIN  
3. SOURCE  
4. GATE  
4. CATHODE  
STYLE 6:  
PIN 1. RETURN  
STYLE 7:  
STYLE 8:  
STYLE 9:  
STYLE 10:  
PIN 1. ANODE 1  
2. CATHODE  
3. ANODE 2  
CANCELLED  
PIN 1. INPUT  
2. GROUND  
3. LOGIC  
PIN 1. CATHODE  
2. ANODE  
2. INPUT  
3. OUTPUT  
4. INPUT  
3. GATE  
4. CATHODE  
4. GROUND  
4. ANODE  
STYLE 11:  
PIN 1. MT 1  
STYLE 12:  
STYLE 13:  
PIN 1. INPUT  
2. OUTPUT  
3. NC  
PIN 1. GATE  
2. COLLECTOR  
3. EMITTER  
4. COLLECTOR  
2. MT 2  
3. GATE  
4. MT 2  
4. OUTPUT  
GENERIC  
MARKING DIAGRAM*  
AYW  
XXXXXG  
G
1
A
Y
= Assembly Location  
= Year  
W
= Work Week  
XXXXX = Specific Device Code  
G
= PbFree Package  
(Note: Microdot may be in either location)  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
PbFree indicator, “G” or microdot “G”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42680B  
SOT223 (TO261)  
PAGE 2 OF 2  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
© Semiconductor Components Industries, LLC, 2018  
www.onsemi.com  
onsemi,  
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates  
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.  
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