MMBF4391LT1 [ONSEMI]
JFET Switching Transistors; JFET开关晶体管
| 型号： | MMBF4391LT1 |
| 厂家： | 
ONSEMI |
| 描述： | JFET Switching Transistors |
| 文件： | 总6页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MMBF4391LT1,
MMBF4392LT1,
MMBF4393LT1
JFET Switching Transistors
N−Channel
http://onsemi.com
Features
2 SOURCE
• Pb−Free Packages are Available
3
GATE
MAXIMUM RATINGS
Rating
Drain−Source Voltage
Symbol
Value
30
Unit
Vdc
1 DRAIN
V
DS
DG
GS
Drain−Gate Voltage
V
V
30
Vdc
Gate−Source Voltage
30
Vdc
MARKING
DIAGRAM
Forward Gate Current
I
50
mAdc
G(f)
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
3
SOT−23
Total Device Dissipation FR−5 Board
P
mW
xx M
CASE 318
STYLE 10
D
1
(Note 1) T = 25°C
225
1.8
A
2
Derate above 25°C
mW/°C
°C/W
Thermal Resistance,
Junction−to−Ambient
R
556
q
JA
xx
M
= Specific Device Code
= Date Code
Junction and Storage Temperature
T , T
−55 to +150
°C
J
stg
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1. FR−5 = 1.0 ꢀ 0.75 ꢀ 0.062 in.
DEVICE MARKING INFORMATION
See specific marking information in the device marking
section on page 2 of this data sheet.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
September, 2004 − Rev. 4
MMBF4391LT1/D
MMBF4391LT1, MMBF4392LT1, MMBF4393LT1
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Gate−Source Breakdown Voltage
(I = 1.0 mAdc, V = 0)
V
30
−
Vdc
(BR)GSS
G
DS
Gate Reverse Current
(V = 15 Vdc, V = 0, T = 25°C)
I
GSS
−
−
1.0
0.20
nAdc
mAdc
GS
DS
A
(V = 15 Vdc, V = 0, T = 100°C)
GS
DS
A
Gate−Source Cutoff Voltage
(V = 15 Vdc, I = 10 nAdc)
V
GS(off)
Vdc
MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
−4.0
−2.0
−0.5
−10
−5.0
−3.0
DS
D
Off−State Drain Current
(V = 15 Vdc, V = −12 Vdc)
I
D(off)
−
−
1.0
1.0
nAdc
mAdc
DS
GS
(V = 15 Vdc, V = −12 Vdc, T = 100°C)
DS
GS
A
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current
I
mAdc
Vdc
W
DSS
(V = 15 Vdc, V = 0)
MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
50
25
5.0
150
75
30
DS
GS
Drain−Source On−Voltage
(I = 12 mAdc, V = 0)
V
DS(on)
DS(on)
MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
−
−
−
0.4
0.4
0.4
D
GS
(I = 6.0 mAdc, V = 0)
D
GS
(I = 3.0 mAdc, V = 0)
D
GS
Static Drain−Source On−Resistance
(I = 1.0 mAdc, V = 0)
r
MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
−
−
−
30
60
100
D
GS
SMALL−SIGNAL CHARACTERISTICS
Input Capacitance
(V = 15 Vdc, V = 0, f = 1.0 MHz)
DS
C
−
−
14
pF
pF
iss
GS
Reverse Transfer Capacitance
(V = 0, V = 12 Vdc, f = 1.0 MHz)
C
3.5
rss
DS
GS
ORDERING INFORMATION
Device
†
Marking
Package
Shipping
MMBF4391LT1
6J
SOT−23
MMBF4391LT1G
SOT−23
(Pb−Free)
6J
MMBF4392LT1
MMBF4393LT1
MMBF4393LT1G
6K
6G
SOT−23
SOT−23
3000 / Tape & Reel
SOT−23
(Pb−Free)
6G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
MMBF4391LT1, MMBF4392LT1, MMBF4393LT1
TYPICAL CHARACTERISTICS
1000
1000
500
T = 25°C
J
T = 25°C
J
500
R
K
= R
D’
MMBF4391
MMBF4392
MMBF4393
V
= 12 V
= 7.0 V
= 5.0 V
GS(off)
MMBF4391
MMBF4392
MMBF4393
V
= 12 V
= 7.0 V
= 5.0 V
GS(off)
R
K
= R
D’
200
100
50
200
100
50
20
10
20
10
R
K
= 0
R
K
= 0
5.0
5.0
2.0
1.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
I , DRAINꢀ CURRENT (mA)
20 30
50
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
20 30
50
I , DRAINꢀ CURRENT (mA)
D
D
Figure 1. Turn−On Delay Time
Figure 2. Rise Time
1000
500
1000
500
T = 25°C
T = 25°C
J
J
R
K
= R
D’
MMBF4391
MMBF4392
MMBF4393
V
= 12 V
= 7.0 V
= 5.0 V
MMBF4391
MMBF4392
MMBF4393
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
GS(off)
200
100
50
200
100
50
R
K
= R
D’
20
10
20
10
R
K
= 0
5.0
5.0
R
K
= 0
2.0
1.0
2.0
1.0
5.0
5.0
7.0 10
0.5 0.7 1.0
2.0 3.0
7.0 10
20 30
50
0.5 0.7 1.0
2.0 3.0
20 30
50
I , DRAINꢀ CURRENT (mA)
D
I , DRAINꢀ CURRENT (mA)
D
Figure 3. Turn−Off Delay Time
Figure 4. Fall Time
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3
MMBF4391LT1, MMBF4392LT1, MMBF4393LT1
NOTE 1
V
DD
The switching characteristics shown above were measured using
a test circuit similar to Figure 5. At the beginning of the switching
R
D
interval, the gate voltage is at Gate Supply Voltage (−V ). The
GG
SET V
= 10 V
DS(off)
Drain−Source Voltage (V ) is slightly lower than Drain Supply
DS
INPUT
R
K
R
Voltage (V ) due to the voltage divider. Thus Reverse Transfer
T
DD
OUTPUT
R
GEN
50 W
Capacitance (C ) of Gate−Drain Capacitance (C ) is charged to
rss
gd
R
GG
V
GG
+ V
.
50
W
DS
50
W
During the turn−on interval, Gate−Source Capacitance (C )
V
V
GEN
gs
GG
discharges through the series combination of R
and R . C
K gd
Gen
must discharge to V
parallel combination of effective load impedance (R’ ) and
Drain−Source Resistance (r ). During the turn−off, this charge
flow is reversed.
through R and R in series with the
G K
DS(on)
INPUT PULSE
t ≤ 0.25 ns
R
GG
> R
K
r
D
R
D’
= R (R + 50)
D T
t ≤ 0.5 ns
f
DS
R
+ R + 50
T
PULSE WIDTH = 2.0 ms
DUTY CYCLE ≤ 2.0%
D
Predicting turn−on time is somewhat difficult as the channel
resistance r is a function of the gate−source voltage. While C
DS
gs
Figure 5. Switching Time Test Circuit
discharges, V approaches zero and r decreases. Since C
GS
DS
gd
discharges through r , turn−on time is non−linear. During turn−
DS
off, the situation is reversed with r increasing as C charges.
DS
gd
The above switching curves show two impedance conditions;
1) R is equal to R which simulates the switching behavior of
K
D’
cascaded stages where the driving source impedance is normally
the load impedance of the previous stage, and 2) R = 0 (low
K
impedance) the driving source impedance is that of the generator.
15
10
20
MMBF4392
MMBF4391
C
gs
10
7.0
5.0
7.0
5.0
MMBF4393
C
gd
T
= 25°C
channel
V
DS
= 15 V
T
= 25°C
3.0
2.0
channel
(C is negligible
ds
3.0
2.0
1.5
1.0
0.030.05 0.1
0.3 0.5 1.0
3.0 5.0 10
30
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
I , DRAINꢀ CURRENT (mA)
20 30
50
V , REVERSE VOLTAGE (VOLTS)
R
D
Figure 7. Typical Capacitance
Figure 6. Typical Forward Transfer Admittance
200
2.0
1.8
I
125 mA
100 mA
50 mA 75 mA
DSS 25 mA
I
D
= 1.0 mA
= 10
mA
V
GS
= 0
160
120
80
40
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
T
= 25°C
channel
−70 −40 −10
20
50
80
110 140 170
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
V
GS
, GATE−SOURCE VOLTAGE (VOLTS)
T
, CHANNEL TEMPERATURE (°C)
channel
Figure 8. Effect of Gate−Source Voltage
on Drain−Source Resistance
Figure 9. Effect of Temperature on Drain−Source
On−State Resistance
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4
MMBF4391LT1, MMBF4392LT1, MMBF4393LT1
NOTE 2
The Zero−Gate−Voltage Drain Current (I ) is the
principle determinant of other J−FET characteristics.
Figure 10 shows the relationship of Gate−Source Off
DSS
10
100
90
80
70
60
50
40
30
20
10
0
T
= 25°C
channel
9.0
8.0
7.0
6.0
Voltage (V
) and Drain−Source On Resistance
GS(off)
r
@ V = 0
GS
DS(on)
(r
) to I . Most of the devices will be within
DS(on)
DSS
±10% of the values shown in Figure 10. This data will
be useful in predicting the characteristic variations for
a given part number.
V
GS(off)
5.0
4.0
3.0
2.0
1.0
0
For example:
Unknown
r
and V range for an MMBF4392
GS
DS(on)
The electrical characteristics table indicates that an
MMBF4392 has an I range of 25 to 75 mA. Figure
70 80 90 100 110 120 130 140 150
10 20 30 40 50 60
DSS
I
, ZERO−GATE VOLTAGE DRAIN CURRENT (mA)
DSS
10 shows r
= 52 Ohms for I
= 75 mA. The corresponding V values
= 25 mA and 30
DS(on)
DSS
Figure 10. Effect of IDSS on Drain−Source
Resistance and Gate−Source Voltage
Ohms for I
DSS
GS
are 2.2 V and 4.8 V.
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5
MMBF4391LT1, MMBF4392LT1, MMBF4393LT1
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AJ
NOTES:
A
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
3
S
C
B
1
2
4. 318−03 AND −07 OBSOLETE, NEW STANDARD
318−08.
V
G
INCHES
MIN
MILLIMETERS
DIM
A
B
C
D
G
H
J
MAX
0.1197
0.0551
0.0440
0.0200
0.0807
0.0040
0.0070
0.0285
0.0401
0.1039
0.0236
MIN
2.80
1.20
0.89
0.37
1.78
0.013
0.085
0.35
0.89
2.10
0.45
MAX
3.04
1.40
1.11
0.50
2.04
0.100
0.177
0.69
1.02
2.64
0.60
0.1102
0.0472
0.0350
0.0150
0.0701
0.0005
0.0034
0.0140
0.0350
0.0830
0.0177
H
J
D
K
K
L
S
V
STYLE 10:
PIN 1. DRAIN
2. CSOURCE
3. GATE
SOLDERING FOOTPRINT*
0.95
0.037
0.95
0.037
2.0
0.079
0.9
0.035
0.8
0.031
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MMBF4391LT1/D
相关型号：
MMBF4391_NL
Small Signal Field-Effect Transistor, 1-Element, N-Channel, Silicon, Junction FET,
FAIRCHILD
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