MC74VHCT541ADTG [ONSEMI]
Octal Bus Buffer; 八路总线缓冲器型号: | MC74VHCT541ADTG |
厂家: | ONSEMI |
描述: | Octal Bus Buffer |
文件: | 总6页 (文件大小:104K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74VHCT541A
Octal Bus Buffer
The MC74VHCT541A is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHCT541A is a noninverting, 3−state, buffer/line
driver/line receiver. When either OE1 or OE2 is high, the terminal
outputs are in the high impedance state.
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The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
MARKING
DIAGRAMS
The VHCT541A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltage−input/output voltage mismatch, battery backup, hot insertion,
etc.
20
1
VHCT541A
AWLYYWWG
SOIC−20WB
SUFFIX DW
CASE 751D
1
Features
20
• High Speed: t = 5.4 ns (Typ) at V = 5.0 V
PD
CC
VHCT
541A
ALYWG
G
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
1
TSSOP−20
SUFFIX DT
CASE 948E
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
1
• Designed for 4.5 V to 5.5 V Operating Range
• Low Noise: V
= 1.6 V (Max)
OLP
20
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
74VHCT541
AWLYWWG
SOEIAJ−20
SUFFIX M
CASE 967
1
• ESD Performance:
1
Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
• Pb−Free Packages are Available*
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output Y
OE1 OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
January, 2006 − Rev. 4
MC74VHCT541A/D
MC74VHCT541A
2
3
4
5
6
7
8
9
18
Y1
A1
A2
A3
A4
A5
A6
A7
17
Y2
OE1
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
V
CC
16
Y3
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
Y4
DATA
INPUTS
NONINVERTING
OUTPUTS
14
Y5
13
Y6
12
Y7
11
A8
Y8
GND 10
11 Y8
1
OE1
Figure 2. Pin Assignment
OUTPUT
ENABLES
19
OE2
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
– 0.5 to + 7.0
V
CC
V
in
– 0.5 to + 7.0
– 0.5 to + 7.0
V
V
V
out
Outputs in 3−State
High or Low State
– 0.5 to V + 0.5
CC
I
Input Diode Current
− 20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
IK
in
V
out
should be constrained to the
I
Output Diode Current (V
< GND; V
> V
)
CC
OK
OUT
OUT
range GND v (V or V ) v V
.
CC
in
out
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
25
Unused inputs must always be
tied to an appropriate logic voltage
out
I
75
CC
CC
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
P
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
D
T
Storage Temperature
– 65 to + 150
_C
stg
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
4.5
5.5
V
CC
V
0
5.5
V
V
in
V
Outputs in 3−State
High or Low State
0
0
5.5
out
V
CC
T
Operating Temperature
Input Rise and Fall Time
− 40
0
+ 85
20
_C
ns/V
A
t , t
r
V =5.0V 0.5V
CC
f
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2
MC74VHCT541A
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min Typ
Max
Min
2.0
Max
V
Symbol
Parameter
Test Conditions
Unit
V
Minimum High−Level Input Voltage
4.5 to 5.5 2.0
4.5 to 5.5
V
IH
V
Maximum Low−Level Input Voltage
Minimum High−Level Output
0.8
0.8
V
V
IL
V
I
I
I
I
= − 50mA
= − 8mA
4.5
4.5
4.4
4.5
0.0
4.4
OH
OH
OH
OL
OL
Voltage
V = V or V
in IH IL
3.94
3.80
V
Maximum Low−Level Output
Voltage = V or V
IL
= 50mA
4.5
0.1
0.36
0.1
0.1
0.44
1.0
V
OL
V
in
IH
= 8mA
4.5
I
Maximum Input Leakage Current
Maximum 3−State Leakage Current
V
V
= 5.5 V or GND
0 to 5.5
5.5
mA
mA
in
in
I
= V or V
IH
0.25
2.5
OZ
in
IL
V
out
= V or GND
CC
I
Maximum Quiescent Supply Current
Quiescent Supply Current
V
= V or GND
5.5
5.5
4.0
40.0
1.50
mA
CC
in
CC
I
Per Input: V = 3.4V
1.35
mA
CCT
IN
Other Input: V or GND
CC
I
Output Leakage Current
V
= 5.5V
0
0.5
5.0
mA
OPD
OUT
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation Delay,
A to Y
V
V
= 5.0 0.5V
C = 15pF
C = 50pF
L
5.0
5.5
6.9
7.9
1.0
1.0
8.0
9.0
ns
PLH
t
CC
CC
L
PHL
,
Output Enable TIme,
OE to Y
= 5.0 0.5V
C = 15pF
8.3
8.8
11.3
12.3
1.0
1.0
13.0
14.0
ns
ns
ns
PZL
t
L
R = 1kW
C = 50pF
L
PZH
L
,
Output Disable Time,
OE to Y
V
= 5.0 0.5V
C = 50pF
L
9.4
11.9
1.0
10
1.0
13.5
1.0
10
PLZ
CC
t
R = 1kW
PHZ
L
t
,
Output to Output Skew
V
= 5.0 0.5V
C = 50pF
L
OSLH
CC
t
(Note 1)
OSHL
C
in
Maximum Input Capacitance
4
9
pF
pF
C
Maximum 3−State Output Capacitance
(Output in High Impedance State)
out
Typical @ 25°C, V = 5.0V
CC
19
C
PD
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. t
= |t
− t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /8 (per bit). C is used to determine the no−load
CC(OPR
PD CC in CC PD
2
dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Parameter
Unit
V
V
Quiet Output Maximum Dynamic V
1.2
1.6
−1.6
2.0
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−1.2
V
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
0.8
V
ILD
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3
MC74VHCT541A
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHCT541ADW
SOIC−20WB
38 Units / Rail
38 Units / Rail
MC74VHCT541ADWG
SOIC−20WB
(Pb−Free)
MC74VHCT541ADWR2
MC74VHCT541ADWRG
SOIC−20WB
1000 / Tape & Reel
1000 / Tape & Reel
SOIC−20WB
(Pb−Free)
MC74VHCT541ADT
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOEIAJ−20
75 Units / Rail
75 Units / Rail
MC74VHCT541ADTG
MC74VHCT541ADTR2
MC74VHCT541ADTRG
MC74VHCT541AMEL
MC74VHCT541AMELG
2500 / Tape & Reel
2500 / Tape & Reel
2000 / Tape & Reel
2000 / Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
3V
OE1 or OE2
1.5V
3V
GND
t
t
PLZ
A
Y
1.5V
PZL
HIGH
IMPEDANCE
GND
t
t
PHL
Y
Y
1.5V
PLH
V
V
+0.3V
V
V
OL
OH
OL
t
t
PHZ
PZH
1.5V
−0.3V
OH
1.5V
HIGH
IMPEDANCE
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST POINT
TEST POINT
OUTPUT
CONNECT TO V WHEN
.
CC
TESTING t AND t
1 kW
OUTPUT
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
TEST
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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4
MC74VHCT541A
PACKAGE DIMENSIONS
SOIC−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
MILLIMETERS
1
10
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
TSSOP−20
D5 SUFFIX
CASE 948E−02
ISSUE B
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
0.25 (0.010)
N
S
0.15 (0.006) T U
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
−W−
C
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
J
G
J1
K
D
H
DETAIL E
K1
L
0.100 (0.004)
6.40 BSC
0.252 BSC
0
−T− SEATING
PLANE
M
0
8
8
_
_
_
_
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5
MC74VHCT541A
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
1
H
E
E
_
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
A
−−−
0.05
2.05
A
1
A
b
1
0.20 0.002
0.50 0.014
0.25 0.006
12.80 0.486
5.45 0.201
0.008
0.020
0.010
0.504
0.215
b
c
0.35
0.15
M
0.10 (0.004)
0.13 (0.005)
D
E
e
12.35
5.10
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
0.035
0
_
_
_
_
0.70
−−−
1
Z
0.81
−−− 0.032
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MC74VHCT541A/D
相关型号:
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