概述
数据手册
替代型号MC74VHC257MELG 概述
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MC74VHC257MELG 数据手册
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PDF下载MC74VHC257
Quad 2−Channel Multiplexer
with 3−State Outputs
The MC74VHC257 is an advanced high speed CMOS quad
2−channel multiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
It consists of four 2−input digital multiplexers with common select
(S) and enable (OE) inputs. When (OE) is held High, selection of data
is inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
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MARKING DIAGRAMS
16
1
9
8
VHC257
AWLYWW
SO−16
D SUFFIX
CASE 751B
• High Speed: t = 4.1 ns (Typ) at V = 5.0 V
PD
CC
• Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C
CC
A
16
9
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
VHC257
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
1
• Low Noise: V
= 0.8 V (Max)
8
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: FETs = 100; Equivalent Gates = 25
9
16
VHC257
ALYW
EIAJ SO−16
M SUFFIX
CASE 966
8
1
V
S
1
2
16
15
CC
A0
OE
A3
B3
A
L, WL
Y
= Assembly Location
= Wafer Lot
= Year
B0
Y0
3
4
14
13
W, WW = Work Week
ORDERING INFORMATION
A1
B1
Y3
A2
5
6
12
11
†
Device
Package
Shipping
MC74VHC257D
SO−16
48 Units/Rail
B2
Y2
7
8
10
9
Y1
MC74VHC257DR2
SO−16
2500 Tape & Reel
96 Units/Rail
GND
MC74VHC257DT
TSSOP−16
MC74VHC257DTR2 TSSOP−16 2500 Tape & Reel
MC74VHC257M EIAJSO−16 50 Units/Rail
Figure 1. Pin Assignment
MC74VHC257MEL EIAJSO−16 2000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
September, 2004 − Rev. 3
MC74VHC257/D
MC74VHC257
OE
I
0a
I
1a
I
0b
I
1b
I
0c
I
1c
I
0d
I
1d
S
Z
Z
Z
Z
d
a
b
c
Figure 2. Expanded Logic Diagram
15
OE
EN
G1
1
S
2
3
5
6
MUX
A0
B0
A1
B1
1
1
4
7
Y0
Y1
Y2
Y3
11
10
14
13
A2
B2
9
A3
B3
12
Figure 3. IEC Logic Symbol
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
FUNCTION TABLE
Inputs
Outputs
OE
S
Y0 − Y3
H
L
L
X
L
H
Z
cuit. For proper operation, V and
A0−A3
B0−B3
in
V
out
should be constrained to the
range GND v (V or V ) v V
.
A0 − A3, B0 − B3 = the levels
of the respective Data−Word
Inputs.
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
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2
MC74VHC257
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
CC
IN
V
DC Output Voltage
−0.5 to V +0.5
V
OUT
CC
I
I
I
I
Input Diode Current
−20
$20
$25
$75
mA
mA
mA
mA
mW
IK
Output Diode Current
DC Output Current, per Pin
OK
OUT
CC
DC Supply Current, V and GND Pins
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
V
Human Body Model (Note 1)
Machine Model (Note 2)
>2000
>200
V
ESD
Charged Device Model (Note 3)
>2000
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
$300
143
164
mA
LATCHUP
CC
q
Thermal Resistance, Junction−to−Ambient
SOIC Package
TSSOP
°C/W
JA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1
2
3
4
Tested to EIA/JESD22−A114−A
Tested to EIA/JESD22−A115−A
Tested to JESD22−C101−A
Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
5.5
Unit
V
V
V
V
DC Supply Voltage
CC
IN
DC Input Voltage
5.5
V
DC Output Voltage
0
V
CC
V
OUT
T
Operating Temperature Range, all Package Types
Input Rise or Fall Time
−55
0
125
°C
ns/V
A
t , t
r
V
CC
V
CC
= 3.3 V + 0.3 V
= 5.0 V + 0.5 V
100
20
f
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 4. Failure Rate vs. Time Junction Temperature
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3
MC74VHC257
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
T
A
≤ 85°C
−55°C ≤ T ≤ 125°C
A
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
1.5
Min
Max
Unit
V
V
V
Minimum High−Level
Input Voltage
2.0
1.5
1.5
1.5
V
IH
3.0 to
5.5
V
CCX
V
CCX
V
CCX
V
CCX
0.7
0.7
0.7
0.7
Maximum Low−Level
Input Voltage
2.0
0.5
0.5
0.5
V
V
IL
3.0 to
5.5
V
CCX
V
CCX
V
CCX
0.3
0.3
0.3
V
I
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
Maximum High−Level
Output Voltage
IN
IH
IL
IL
IL
IL
OH
= −50 mA
OH
V
IN
= V or V
IH
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.8
2.34
3.66
OH
I
OH
V
IN
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
Maximum Low−Level
Output Voltage
V
IH
I
OL
= 50 mA
V
IN
= V or V
IH
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
OH
I
OH
I
I
Input Leakage Current
V
= 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
mA
IN
IN
Maximum 3−State
Leakage Current
V
V
= V or V
IL
5.5
±0.25
±2.5
±2.5
OZ
IN
IH
= V or GND
OUT
CC
I
Maximum Quiescent
Supply Current
V
IN
= V or GND
5.5
4.0
40.0
40.0
mA
CC
CC
(per package)
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = ≤ 85°C −55°C ≤ T ≤ 125°C
A A
Min Typ Max Min Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
,
Maximum Propagation
Delay
A or B to Y
ns
V
V
V
V
V
= 3.3 ± 0.3 V C = 15 pF
5.8
8.3
9.3
12.8
1.0
1.0
11.0
14.5
1.0
1.0
11.0
14.5
PLH
PHL
CC
CC
CC
CC
CC
L
C = 50 pF
L
= 5.0 ± 0.5 V C = 15 pF
3.6
5.1
5.9
7.9
1.0
1.0
7.0
9.0
1.0
1.0
7.0
9.0
L
C = 50 pF
L
t
t
,
Maximum Propagation
Delay
S to Y
ns
ns
ns
pF
= 3.3 ± 0.3 V C = 15 pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
1.0
1.0
13.0
16.5
PLH
PHL
L
C = 50 pF
L
= 5.0 ± 0.5 V C = 15 pF
4.0
5.5
6.8
8.8
1.0
1.0
8.0
10.0
1.0
1.0
8.0
10.0
L
C = 50 pF
L
t
t
,
Maximum Output Enable
Time
OE to Y
= 3.3 ± 0.3 V C = 15 pF
6.7
9.2
10.5
14.0
1.0
1.0
12.5
16.0
1.0
1.0
12.5
16.0
PZL
PZH
L
R = 1 kW
C = 50 pF
L
L
V
CC
= 5.0 ± 0.5 V C = 15 pF
3.6
5.1
6.8
8.8
1.0
1.0
8.0
10.0
1.0
1.0
8.0
10.0
L
R = 1 kW
C = 50 pF
L
L
t
t
,
Maximum Output Disable
Time
OE to Y
V
CC
= 3.3 ± 0.3 V C = 50 pF
12.0 15.0
1.0
16.0
14.0
10
1.0
17.5
15.0
10
PLZ
PHZ
L
R = 1 kW
L
V
CC
= 5.0 ± 0.5 V C = 50 pF
5.7
4
13.0
10
1.0
1.0
L
R = 1 kW
L
C
Maximum Input
Capacitance
IN
Typical @ 25°C, V = 5.0V
CC
20
C
Power Dissipation Capacitance (Note 5)
pF
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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4
MC74VHC257
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Characteristic
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.3
0.8
− 0.8
3.5
OLP
OL
Quiet Output Minimum Dynamic V
− 0.3
V
OLV
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
V
CC
OE
50%
GND
V
CC
t
t
50%
PZL
PLZ
A, B or S
HIGH
GND
IMPEDANCE
t
50% V
PHL
Y
Y
CC
t
PLH
V
V
+ 0.3V
OL
t
t
PHZ
PZH
50% V
CC
Y
− 0.3V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 5. Switching Waveform
Figure 6. Switching Waveform
TEST POINT
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
1 kΩ
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
DEVICE
UNDER
TEST
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7. Test Circuit
Figure 8. Test Circuit
INPUT
Figure 9. Input Equivalent Circuit
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5
MC74VHC257
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
−B−
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
−T−
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T
U
V
S
0.15 (0.006) T U
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
2X L/2
J1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
B
−U−
SECTION N−N
L
J
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
PIN 1
IDENT.
8
1
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
N
0.25 (0.010)
S
0.15 (0.006) T U
A
M
−V−
N
F
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
A
B
4.90
4.30
−−−
0.193
0.169
−−−
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
−W−
C
G
H
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
J
0.10 (0.004)
J1
K
H
DETAIL E
SEATING
PLANE
−T−
D
G
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
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6
MC74VHC257
SOIC EIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
16
9
L
E
Q
1
H
E
M
_
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
−−−
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
A
1
0.20 0.002
0.50 0.014
0.27 0.007
b
c
D
E
10.50
5.45 0.201
0.390
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
0
10
0.90 0.028
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
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7
MC74VHC257
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC257/D
MC74VHC257MELG 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| MC74VHC257DR2G | ONSEMI | Quad 2-Channel Multiplexer with 3-State Outputs | 完全替代 |
|
| MC74VHC257DTG | ONSEMI | Quad 2-Channel Multiplexer with 3-State Outputs | 完全替代 |
|
MC74VHC257MELG 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MC74VHC257MG | ONSEMI | IC AHC/VHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, EIAJ, SO-16, Multiplexer/Demultiplexer | 获取价格 |
|
| MC74VHC257_14 | ONSEMI | Quad 2-Channel Multiplexer with 3-State Outputs | 获取价格 |
|
| MC74VHC259 | ONSEMI | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | 获取价格 |
|
| MC74VHC259D | ONSEMI | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | 获取价格 |
|
| MC74VHC259DG | ONSEMI | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | 获取价格 |
|
| MC74VHC259DR2 | ONSEMI | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | 获取价格 |
|
| MC74VHC259DR2G | ONSEMI | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | 获取价格 |
|
| MC74VHC259DT | ONSEMI | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | 获取价格 |
|
| MC74VHC259DTEL | ONSEMI | 暂无描述 | 获取价格 |
|
| MC74VHC259DTG | ONSEMI | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter, TSSOP-16, 96-TUBE | 获取价格 |
|
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