MC74VHC1G00DTT3 [ONSEMI]
AHC/VHC SERIES, 2-INPUT NAND GATE, PDSO5, SC-59, SOT-23, TSOP-5;
| 型号： | MC74VHC1G00DTT3 |
| 厂家： | 
ONSEMI |
| 描述： | AHC/VHC SERIES, 2-INPUT NAND GATE, PDSO5, SC-59, SOT-23, TSOP-5 栅 输入元件 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1G00
Single 2-Input NAND Gate
The MC74VHC1G00 is an advanced high speed CMOS 2−input
NAND gate fabricated with silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The MC74VHC1G00 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G00 to be used to interface 5.0 V circuits to
3.0 V circuits.
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MARKING
DIAGRAMS
Features
5
• High Speed: t = 3.0 ns (Typ) at V = 5.0 V
PD
CC
V1M G
SC−88A / SOT−353 / SC−70
DF SUFFIX
G
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
1
5
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 56
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
CASE 419A
V1 M G
G
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
1
CASE 483
• These Devices are Pb−Free and are RoHS Compliant
V1 = Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
5
4
IN B
IN A
GND
1
2
3
V
CC
PIN ASSIGNMENT
1
2
3
4
5
IN B
IN A
GND
OUT Y
OUT Y
V
CC
Figure 1. Pinout (Top View)
FUNCTION TABLE
Inputs
Output
Y
A
B
L
L
L
H
L
H
H
H
L
IN A
IN B
&
OUT Y
H
H
H
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2013 − Rev. 20
MC74VHC1G00/D
MC74VHC1G00
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
*0.5 to +7.0
−0.5 to +7.0
V
IN
DC Input Voltage
V
V
OUT
DC Output Voltage
*0.5 to V +0.5
V
CC
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
−20
20
mA
mA
mA
mA
°C
IK
I
OK
I
12.5
OUT
I
25
CC
T
*65 to +150
260
STG
T
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
°C
L
+150
°C
J
q
SC70−5/SC−88A (Note 1)
TSOP−5
350
230
°C/W
JA
P
D
Power Dissipation in Still Air at 85°C
SC70−5/SC−88A
TSOP−5
150
200
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
R
V
ESD
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
N/A
V
I
Latchup Performance
Above V and Below GND at 125°C (Note 5)
500
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
V
IN
DC Input Voltage
0.0
5.5
V
V
OUT
DC Output Voltage
0.0
V
CC
V
T
Operating Temperature Range
Input Rise and Fall Time
*55
+125
°C
ns/V
A
t , t
r
V
CC
V
CC
= 3.3 V $ 0.3 V
= 5.0 V $ 0.5 V
0
0
100
20
f
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
1
9.4
37,000
4.2
1
10
100
1000
17,800
2.0
TIME, YEARS
8,900
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G00
DC ELECTRICAL CHARACTERISTICS
T
A
= 255C
Typ
T
v 855C
*555C to 1255C
A
V
CC
Min
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
Maximum Low−Level
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
V
IL
Input Voltage
V
OH
Minimum High−Level
V
IN
= V or V
IL
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
IH
Output Voltage
I
= −50 mA
OH
V
IN
= V or V
IH IL
V
IN
= V or V
IH
IL
I
= −4 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
OH
I
= −8 mA
OH
V
OL
Maximum Low−Level
V
IN
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IH
IL
Output Voltage
I
= 50 mA
OL
V
IN
= V or V
IH IL
V
IN
= V or V
IH
IL
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
OL
I
OL
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
1.0
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
V
IN
= V or GND
5.5
1.0
10
40
CC
CC
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 255C
Typ
T
v 855C
*555C to 1255C
A
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
= 3.3 $ 0.3 V C = 15 pF
Unit
t
,
Maximum Propagation
Delay, Input A or B to Y
V
CC
4.5
5.6
7.9
11.4
9.5
13.0
11.0
15.5
ns
PLH
L
t
C = 50 pF
PHL
L
V
CC
= 5.0 $ 0.5 V C = 15 pF
3.0
3.8
5.5
7.5
6.5
8.5
8.0
10.0
L
C = 50 pF
L
C
Maximum Input
Capacitance
5.5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
10
C
PD
Power Dissipation Capacitance (Note 6)
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1G00
V
CC
A or B
50%
GND
t
t
PHL
PLH
Y
50% V
CC
Figure 4. Switching Waveforms
V
CC
OUTPUT
INPUT
C
L*
*Includes all probe and jig capacitance.
A 1−MHz square input wave is recommended
for propagation delay tests.
Figure 5. Test Circuit
ORDERING INFORMATION
†
Device
MC74VHC1G00DFT1G
MC74VHC1G00DFT2G
MC74VHC1G00DTT1G
NLVVHC1G00DTT1G*
Package
Shipping
SC70−5/SC−88A/SOT−353
(Pb−Free)
3000 / Tape & Reel
SOT23−5/TSOP−5/SC59−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74VHC1G00
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
G
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
SOLDER FOOTPRINT
0.50
0.0197
K
H
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
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5
MC74VHC1G00
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
C
D
0.90
0.25
1.10
0.50
J
G
H
J
K
M
S
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1G00/D
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