MC74LVX50 [ONSEMI]
HEX BUFFER; 六角缓冲器
| 型号： | MC74LVX50 |
| 厂家： | 
ONSEMI |
| 描述： | HEX BUFFER |
| 文件： | 总10页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX50
Hex Buffer
The MC74LVX50 is an advanced high speed CMOS buffer
fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
Features
DIAGRAMS
• High Speed: t = 4.1 ns (Typ) at V = 3.3 V
PD
CC
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
14
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
SOIC−14
D SUFFIX
CASE 751A
LVX50
AWLYWW
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 3.6 V Operating Range
14
1
1
• Low Noise: V
= 0.5 V (Max)
OLP
• Pb−Free Packages are Available*
14
TSSOP−14
DT SUFFIX
CASE 948G
LVX
50
ALYW
14
1
1
14
74LVX50
ALYW
SOEIAJ−14
M SUFFIX
CASE 965
14
1
1
A
=
=
=
=
Assembly Location
Wafer Lot
Year
WL or L
Y
WW or W
Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
March, 2005 − Rev. 3
MC74LVX50/D
MC74LVX50
1
3
5
2
4
6
A1
A2
A3
Y1
Y2
1
1
1
1
1
1
A1
A2
A3
A4
A5
A6
Y1
Y2
Y3
Y4
Y5
Y6
Y3
Y = A
Y4
9
8
A4
A5
A6
11
13
10
12
Y5
Y6
Figure 1. Logic Diagram
Figure 2. Logic Symbol
V
CC
A6
Y6
A5
Y5
A4
Y4
FUNCTION TABLE
14
13
12
11
10
9
8
A Input
Y Output
L
L
H
H
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3 GND
14−Lead Pinout (Top View)
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX50D
SOIC−14
55 Units / Rail
55 Units / Rail
MC74LVX50DG
SOIC−14
(Pb−Free)
MC74LVX50DR2
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
MC74LVX50DR2G
SOIC−14
(Pb−Free)
MC74LVX50DT
MC74LVX50DTR2
MC74LVX50M
TSSOP−14*
TSSOP−14*
SOEIAJ−14
96 Units / Rail
2500 Tape & Reel
50 Units / Rail
MC74LVX50MG
SOEIAJ−14
(Pb−Free)
50 Units / Rail
MC74LVX50MEL
SOEIAJ−14
2000 Tape & Reel
2000 Tape & Reel
MC74LVX50MELG
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVX50
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
*0.5 to )7.0
*0.5 to )7.0
V
IN
DC Input Voltage
V
V
OUT
DC Output Voltage
*0.5 to V )0.5
V
CC
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
V < GND
*20
$20
mA
mA
mA
mA
_C
IK
I
I
V < GND
O
OK
I
$25
OUT
I
$50
CC
T
*65 to )150
260
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
_C
L
T
)150
_C
_C/W
J
q
(Note 1)
SOIC
JA
125
170
TSSOP
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% − 35%
UL 94−V0 @ 0.125 in
V
ESD
Human Body Model (Note 2)
Machine Model (Note 3)
> 2000
> 200
2000
V
Charged Device Model (Note 4)
I
Latchup Performance
Above V and Below GND at 85_C (Note 5)
$300
mA
Latchup
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
3.6
Unit
V
V
CC
Supply Voltage
V
I
Input Voltage
(Note 6)
5.5
V
V
O
Output Voltage
(HIGH or LOW State)
0
V
CC
V
T
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
*40
0
)85
_C
ns/V
A
Dt/DV
V
= 3.0 V $0.3 V
100
CC
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
NOTE: The q of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table
JA
and figure below.
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3
MC74LVX50
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T ≤ 85°C
A
V
CC
Min
Typ
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
High−Level Input Voltage
2.0
3.0
3.6
1.5
2.0
2.4
1.5
2.0
2.4
V
V
Low−Level Input Voltage
2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
V
V
V
IL
V
OH
High−Level Output Voltage
I
I
I
= −50 mA
= −50 mA
= −4 mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OH
OH
(V = V or V )
IN
IH
IL
V
OL
Low−Level Output Voltage
(V = V or V )
I
OL
I
OL
I
OL
= 50 mA
= 50 mA
= 4 mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
IN
IH
IL
I
Input Leakage Current
V
= 5.5 V or GND
0 to
3.6
±0.1
±1.0
mA
mA
IN
IN
I
Quiescent Supply Current
V
IN
= V or GND
3.6
2.0
20.0
CC
CC
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T ≤ 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
V
= 2.7 V
C = 15 pF
C = 50 pF
L
5.4
7.9
10.1
13.6
1.0
1.0
12.5
16.0
t
t
,
Propagation Delay,
Input A to Y
ns
CC
L
PLH
PHL
= 3.3 V ± 0.3 V
C = 15 pF
4.1
6.6
6.2
9.7
1.0
1.0
7.5
11.5
CC
L
C = 50 pF
L
V
V
= 2.7 V
C = 50 pF
1.5
1.5
10
1.5
1.5
10
t
t
Output−to−Output Skew
(Note 7)
ns
CC
L
OSHL
OSLH
= 3.3 V ±0.3V
C = 50 pF
L
CC
C
Input Capacitance
4
pF
IN
Typical @ 25°C, V = 3.3 V
CC
15
C
Power Dissipation Capacitance (Note 8)
pF
PD
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
8. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS Input t = t = 3.0ns, C = 50pF, V = 3.3 V
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Characteristic
Unit
V
V
Quiet Output Maximum Dynamic V
0.3
0.5
−0.5
2.0
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.3
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
0.8
V
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4
MC74LVX50
TEST POINT
OUTPUT
V
CC
50%
A
Y
DEVICE
UNDER
TEST
GND
t
t
PHL
PLH
C *
L
50% V
CC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
EMBOSSED CARRIER DIMENSIONS (See Notes 9 and 10)
Tape
Size
B
1
Max
D
D
E
F
K
P
P
0
P
2
R
T
W
1
8 mm
4.35 mm
(0.179”)
1.0 mm
Min
3.5 mm
±0.5
2.4 mm
Max
4.0 mm
±0.10
25 mm
(0.98”)
8.3 mm
(0.327)
1.5 mm
+ 0.1
1.75 mm
±0.1
4.0 mm
±0.1
2.0 mm
±0.1
0.6 mm
(0.024)
(0.179”)
(1.38
±0.002”)
(0.094”)
(0.157
±0.004”)
−0.0
(0.069
±0.004”)
(0.157
±0.004”)
(0.079
±0.004”)
(0.059”
+0.004
−0.0)
12 mm
8.2 mm
(0.323”)
5.5 mm
±0.5
6.4 mm
Max
4.0 mm
±0.10
12.0 mm
±0.3
1.5 mm
Min
30 mm
(1.18”)
(0.217
±0.002”)
(0.252”)
(0.157
(0.470
±0.012”)
(0.060)
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
16 mm 12.1 mm
(0.476”)
7.5 mm
±0.10
7.9 mm
Max
4.0 mm
±0.10
16.3 mm
(0.642)
(0.295
(0.311”)
(0.157
±0.004”)
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
12.0 mm
±0.10
(0.472
±0.004”)
24 mm 20.1 mm
(0.791”)
11.5 mm
±0.10
11.9 mm
Max
16.0 mm
±0.10
24.3 mm
(0.957)
(0.453
(0.468”)
(0.63
±0.004”)
±0.004”)
9. Metric Dimensions Govern−English are in parentheses for reference only.
10.A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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5
MC74LVX50
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008”)
P
0
K
t
P
2
D
TOP
COVER
TAPE
E
SEE NOTE 11
A
0
F
W
+
+
+
K
0
B
0
B
1
SEE
NOTE
11
D
1
P
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
EMBOSSMENT
USER DIRECTION OF FEED
CENTER
LINES
OF CAVITY
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B
0
*TOP COVER
TAPE THICKNESS (t )
1
0.10 mm
(0.004”) MAX.
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS “R”
WITHOUT DAMAGE
EMBOSSED
CARRIER
EMBOSSMENT
BENDING RADIUS
100 mm
(3.937”)
MAXIMUM COMPONENT ROTATION
10°
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039”) MAX
250 mm
(9.843”)
TYPICAL
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
COMPONENT
CENTER LINE
11. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
Figure 6. Carrier Tape Specifications
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6
MC74LVX50
t MAX
13.0 mm ±0.2 mm
(0.512” ±0.008”)
1.5 mm MIN
(0.06”)
20.2 mm MIN
(0.795”)
50 mm MIN
(1.969”)
A
FULL RADIUS
G
Figure 7. Reel Dimensions
REEL DIMENSIONS
Tape Size
T&R Suffix
A Max
G
t Max
8 mm
T1, T2
178 mm
(7”)
8.4 mm, +1.5 mm, −0.0
(0.33” + 0.059”, −0.00)
14.4 mm
(0.56”)
8 mm
T3, T4
R2
330 mm
(13”)
8.4 mm, +1.5 mm, −0.0
(0.33” + 0.059”, −0.00)
14.4 mm
(0.56”)
12 mm
16 mm
24 mm
330 mm
(13”)
12.4 mm, +2.0 mm, −0.0
(0.49” + 0.079”, −0.00)
18.4 mm
(0.72”)
R2
360 mm
(14.173”)
16.4 mm, +2.0 mm, −0.0
(0.646” + 0.078”, −0.00)
22.4 mm
(0.882”)
R2
360 mm
(14.173”)
24.4 mm, +2.0 mm, −0.0
(0.961” + 0.078”, −0.00)
30.4 mm
(1.197”)
DIRECTION OF FEED
BARCODE LABEL
POCKET
HOLE
Figure 8. Reel Winding Direction
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7
MC74LVX50
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
CAVITY TOP TAPE
TAPE
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
User Direction of Feed
Figure 10. TSSOP and SOIC R2 Reel Configuration/Orientation
TAPE UTILIZATION BY PACKAGE
SC88A / SOT−353
SC88/SOT−363
Tape Size
8 mm
SOIC
TSSOP
QFN
5−, 6−Lead
12 mm
16 mm
24 mm
8−Lead
8−, 14−, 16−Lead
20−, 24−Lead
48−, 56−Lead
8−, 14−, 16−Lead
20−, 24−Lead
48−, 56−Lead
14−, 16−Lead
18−, 20−, 24−, 28−Lead
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8
MC74LVX50
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
14
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T
B
A
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
−U−
L
N
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
K1
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
D
0
8
0
8
_
_
_
_
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9
MC74LVX50
PACKAGE DIMENSIONS
SOEIAJ−14
M SUFFIX
CASE 965−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
14
8
E
Q
1
H
E
_
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
7
1
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
A
e
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
b
A
1
A
1
b
c
0.20 0.002
0.50 0.014
0.27 0.007
M
0.13 (0.005)
0.10 (0.004)
D
E
e
10.50 0.390
5.45 0.201
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
0.70
−−−
1
Z
1.42
−−−
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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