MC74LCX05SD_技术文档

SEMICONDUCTOR TECHNICAL DATA

The MC74LCX05 is a high performance open drain hex inverter

operating from a 2.7 to 3.6V supply. High impedance TTL compatible

inputs significantly reduce current loading to input drivers. A V

specification of 5.5V allows MC74LCX05 inputs to be safely driven from

5V devices.

I

LOW–VOLTAGE CMOS

HEX INVERTER

The MC74LCX05 requires the addition of an external resistor to

perform a wire–NOR function. The open drain output with a 5V pull–up

resistor can be utlilized to drive 5V CMOS inputs. Current drive capability

is 24mA at the outputs.

OPEN DRAIN

• Designed for 2.7 to 3.6V V

CC

Operation

D SUFFIX

• 5V Tolerant Inputs — Interface Capability With 5V TTL Logic

• LVTTL Compatible

PLASTIC SOIC

CASE 751A–03

14

1

• LVCMOS Compatible

• 24mA Output Sink Capability

M SUFFIX

PLASTIC SOIC EIAJ

CASE 965–01

• Near Zero Static Supply Current (10µA) Substantially Reduces System

Power Requirements

14

1

• Latchup Performance Exceeds 500mA

• ESD Performance: Human Body Model >2000V; Machine Model >200V

SD SUFFIX

PLASTIC SSOP

CASE 940A–03

V

A3

13

O3

12

A4

11

O4

10

A5

9

O5

8

CC

14

1

Pinout: 14–Lead

(Top View)

DT SUFFIX

PLASTIC TSSOP

CASE 948G–01

14

1

2

3

4

5

6

7

A0

O0

A1

O1

A2

O2 GND

PIN NAMES

Pins

LOGIC DIAGRAM

Function

1

2

A0

O0

An

On

Data Inputs

Outputs

3

4

A1

A2

A3

A4

A5

O1

5

6

FUNCTION TABLE

An

O2

On

13

11

9

12

O3

L

H

L

10

O4

8

O5

This document contains information on a product under development. Motorola reserves the right to change or

discontinue this product without notice.

9/95

REV 0

40

Motorola, Inc. 1996

Low Voltage Cross Reference

Pkg

Code

Motorola

Replacement Code

Pkg

Company

Family

SN74LVTxxx

SN74LVT16xxx

SN74LVCxxx

Package

Comments

LCX has lower drive, but less power

Use TSSOP. Not footprint compatible

LCX has lower drive, but less power

TI

D

DB

DW

PW

DL

JEDEC SOIC

MC74LCXxxx

D

TI

5.3 mm SSOP II

SD

DW

DT

Wide JEDEC SOIC

4.4 mm TSSOP

48/56 7.5 mm SSOP

DGG

D

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

D

JEDEC SOIC

MC74LCXxxx

Direct replacement. LVC has no Power down High–Z

feature. Many are NOT 5V–tolerant

TI

SN74LVCxxx

DB

DW

PW

5.3 mm SSOP II

Wide JEDEC SOIC

4.4 mm TSSOP

48/56 7.5 mm SSOP

SD

DW

DT

Direct replacement. LVC has no Power down High–Z

feature. Many are NOT 5V–tolerant

Direct replacement. LVC has no Power down High–Z

feature. Many are NOT 5V–tolerant

Direct replacement. LVC has no Power down High–Z

feature. Many are NOT 5V–tolerant

TI

SN74LVC16xxx

DL

Use TSSOP. Not footprint compatible

DGG

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

Direct replacement. LVC has no Power down High–Z

feature. Many are NOT 5V–tolerant

TI

SN74LVC4245

SN74ALVC16xxx

DB

DW

PW

DL

5.3 mm SSOP II

Use TSSOP. Not footprint compatible

Similar replacement

Wide JEDEC SOIC

4.4 mm TSSOP

MC74LVX4245

DW

DT

Similar replacement

48/56 7.5 mm SSOP

Use TSSOP. Not footprint compatible

DGG

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

D

ALVC is slightly faster, but LCX16xxx offers 5V toler-

ance

TI

SN74LVxxx

D

JEDEC SOIC

MC74LVXxxx

LVX has 4mA drive vs. 6mA for LV. LVX is much faster

and has 5V tolerant inputs. Alternate: 74LVQxxx

DB

DW

PW

5.3 mm SSOP II

Wide JEDEC SOIC

4.4 mm TSSOP

SD

DW

DT

For LVX, use TSSOP. Not footprint compatible. Alter-

nate: 74LVQxxx

MC74LVXxxx

LVX has 4mA drive vs. 6mA for LV. LVX is much faster

and has 5V tolerant inputs. Alternate: 74LVQxxx

LVX has 4mA drive vs. 6mA for LV. LVX is much faster

and has 5V tolerant inputs. Alternate: 74LVQxxx

Philips

74LVTxxx

D

DB

D

JEDEC SOIC

MC74LCXxxx

D

LCX has lower drive, but less power

74LVTxxx

5.3 mm SSOP II

Wide JEDEC SOIC

4.4 mm TSSOP

48/56 7.5 mm SSOP

SD

DW

DT

LCX has lower drive, but less power

74LVTxxx

LCX has lower drive, but less power

74LVTxxx

PW

DL

DGG

D

LCX has lower drive, but less power

74LVT16xxx

74LVCxxx

74LVC16xxx

74LVC4245

Use TSSOP. Not footprint compatible

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

D

LCX has lower drive, but less power

JEDEC SOIC

MC74LCXxxx

Direct replacement. Many LVC are NOT 5V–tolerant

Use TSSOP. Not footprint compatible

DB

D

5.3 mm SSOP II

Wide JEDEC SOIC

4.4 mm TSSOP

48/56 7.5 mm SSOP

SD

DW

DT

PW

DL

DGG

DB

D

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

Direct replacement. Many LVC are NOT 5V–tolerant

Use TSSOP. Not footprint compatible

5.3 mm SSOP II

Wide JEDEC SOIC

MC74LVX4245

DW

Similar replacement

NOTE: Motorola cannot guarantee device compatibility and assumes no liability for device incompatibility either implied or stated in this Cross Reference Guide.

Compatibility must be verified by the user.

Bold: Direct replacement (See above Note); Italics: Similar replacement; Blank: Either no replacement or no footprint compatible package.

LCX DATA

3

MOTOROLA

BR1339 — REV 3

Low Voltage Cross Reference

Pkg

Code

Motorola

Replacement Code

Pkg

Company

Philips

Family

Package

4.4 mm TSSOP

Comments

74LVC4245

PW

MC74LVX4245

DT

Similar replacement

Philips

74ALVC16xxx

DL

48/56 7.5 mm SSOP

Use TSSOP. Not footprint compatible

Philips

DGG

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

N

ALVC is slightly faster, but LCX16xxx offers 5V toler-

ance

Philips

74LVxxx

N

D

PDIP

MC74LVXxxx

LVX has 4mA drive vs. 6mA for LV. LVX is much faster

and has 5V tolerant inputs

JEDEC SOIC

5.3 mm SSOP II

Wide JEDEC SOIC

4.4 mm TSSOP

D

LVX has 4mA drive vs. 6mA for LV. LVX is much faster

and has 5V tolerant inputs. Alternate: 74LVQxxx

DB

D

SD

DW

DT

For LVX, use TSSOP. Not footprint compatible. Alter-

nate: 74LVQxxx

MC74LVXxxx

LVX has 4mA drive vs. 6mA for LV. LVX is much faster

and has 5V tolerant inputs Alternate: 74LVQxxx

PW

LVX has 4mA drive vs. 6mA for LV. LVX is much faster

and has 5V tolerant inputs. Alternate: 74LVQxxx

IDT

IDT74FCT3xxx

IDT74FCT163xxx

IDT74FCT3xxxA

IDT74FCT163xxxA

PI74FCT163xxx

PI74FCT163xxxA

PI74LPTxxx

P

SO

PY

PV

PA

P

PDIP

Use SOIC. Not footprint compatible

IDT

Wide JEDEC SOIC

5.3 mm SSOP II

48/56 7.5 mm SSOP

MC74LCXxxx

DW

SD

Direct replacement. LCX also features 5V tolerance

Use TSSOP. Not footprint compatible

IDT

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

Direct replacement. LCX also features 5V tolerance

Use SOIC. Not footprint compatible

IDT

PDIP

IDT

SO

PY

PV

PA

V

Wide JEDEC SOIC

5.3 mm SSOP II

MC74LCXxxx

DW

SD

FCT3...A slightly faster, but LCX offers 5V tolerance

Use TSSOP. Not footprint compatible

IDT

48/56 7.5 mm SSOP

IDT

48/56 6.1 mm TSSOP MC74LCX16xxx

48/56 7.5 mm SSOP

DT

Direct replacement. LCX also features 5V tolerance

Use TSSOP. Not footprint compatible

Pericom

A

48/56 6.1 mm TSSOP MC74LCX16xxx

48/56 7.5 mm SSOP

Direct replacement. LCX also features 5V tolerance

Use TSSOP. Not footprint compatible

V

A

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

D

Direct replacement. LCX also features 5V tolerance

W

JEDEC SOIC

MC74LCXxxx

Direct replacement. LCX also features power down

high–Z

Pericom

PI74LPTxxx

S

Wide JEDEC SOIC

MC74LCXxxx

DW

Direct replacement. LCX also features power down

high–Z

Pericom

PI74LPTxxx

Q

R

L

QSOP

Use TSSOP. Not footprint compatible

Thin QSOP

4.4 mm TSSOP

MC74LCXxxx

DT

Direct replacement. LCX also features power down

high–Z

Pericom

Quality Semi

PI74LPTxxxA/C

PI74LPT16xxx/A/C

PI74LCXxxx

W

S

JEDEC SOIC

Wide JEDEC SOIC

QSOP

MC74LCXxxx

D

LPT...A/C slightly faster

Use TSSOP. Not footprint compatible

LPT...A/C slightly faster

Use TSSOP. Not footprint compatible

Direct replacement

DW

Q

R

L

Thin QSOP

4.4 mm TSSOP

48/56 7.5 mm SSOP

MC74LCXxxx

DT

V

A

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

D

W

S

JEDEC SOIC

MC74LCXxxx

Direct replacement

PI74LCXxxx

Wide JEDEC SOIC

4.4 mm TSSOP

DW

DT

DW

Direct replacement

PI74LCXxxx

L

Direct replacement

PI74LCX16xxx

QS74FCT3xxx

A

48/56 6.1 mm TSSOP MC74LCX16xxx

Wide JEDEC SOIC MC74LCXxxx

Direct replacement

SO

Direct replacement. LCX also features power down

high–Z

NOTE: Motorola cannot guarantee device compatibility and assumes no liability for device incompatibility either implied or stated in this Cross Reference Guide.

Compatibility must be verified by the user.

Bold: Direct replacement (See above Note); Italics: Similar replacement; Blank: Either no replacement or no footprint compatible package.

MOTOROLA

4

LCX DATA

BR1339 — REV 3

Low Voltage Cross Reference

Pkg

Code

Motorola

Replacement Code

Pkg

Company

Quality Semi

Family

Package

Comments

QS74FCT3xxx

QS74FCT3xxxA

QS74FCT163xxxA

Q

SO

Q

QSOP

Use TSSOP. Not footprint compatible

FCT3...A slightly faster, but LCX offers 5V tolerance

Use TSSOP. Not footprint compatible

Wide JEDEC SOIC

QSOP

MC74LCXxxx

DW

Q2

QVSOP

Use TSSOP. Not footprint compatible. LCX also features

power down high–Z

Quality Semi

QS74LCXxxx

SO

Wide JEDEC SOIC

MC74LCXxxx

Direct replacement. Careful, QSI may not be spec com-

patible to LCX

Quality Semi

QS74LCXxxx

Q

QSOP

Use TSSOP. Not footprint compatible

QS74LCX16xxx

Q2

QVSOP

Use TSSOP. Careful, QSI may not be spec compatible

to LCX

Toshiba

TC74LCXxxx

FN

FW

F

JEDEC SOIC

Wide JEDEC SOIC

EIAJ SOIC

MC74LCXxxx

D

DW

M

Direct replacement

FS

4.4 mm SSOP I

DT

Direct replacement. TSSOP is footprint compatible with

this SSOP

Toshiba

TC74LCX16xxx

TC74LVXxxx

FT

FN

FW

F

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

D

Direct replacement

JEDEC SOIC

Wide JEDEC SOIC

EIAJ SOIC I

MC74LVXxxx

DW

M

FS

4.4 mm SSOP

DT

Direct replacement. TSSOP is footprint compatible with

this SSOP

Toshiba

TC74LVQxxx

FN

FW

F

JEDEC SOIC

Wide JEDEC SOIC

EIAJ SOIC

MC74LVQxxx

D

DW

M

Direct replacement

FS

4.4 mm SSOP I

DT

Direct replacement. TSSOP is footprint compatible with

this SSOP

Toshiba

TC74LVX4245

FS

4.4 mm SSOP I

MC74LVX4245

DT

Direct replacement. TSSOP is footprint compatible with

this SSOP

National

74LCXxxx

74LCX16xxx

74LVXxxx

74LVQxxx

74LVX4245

M

MSA

WM

SJ

JEDEC SOIC

MC74LCXxxx

D

SD

DW

M

Direct replacement

5.3 mm SSOP II

Wide JEDEC SOIC

EIAJ SOIC

Direct replacement

MTC

MEA

MTD

M

4.4 mm TSSOP

48/56 7.5 mm SSOP

DT

Direct replacement

Use TSSOP. Not footprint compatible

Direct replacement

48/56 6.1 mm TSSOP MC74LCX16xxx

DT

D

JEDEC SOIC

Wide JEDEC SOIC

EIAJ SOIC

MC74LVXxxx

MC74LVQxxx

Direct replacement

WM

SJ

DW

M

Direct replacement

MTC

M

4.4 mm TSSOP

JEDEC SOIC

Wide JEDEC SOIC

EIAJ SOIC

DT

D

Direct replacement

WM

SJ

DW

M

Direct replacement

QSC

M

QSOP

Use TSSOP. Not footprint compatible

Direct replacement

JEDEC SOIC

4.4 mm TSSOP

MC74LVX4245

D

MTC

DT

Direct replacement

NOTE: Motorola cannot guarantee device compatibility and assumes no liability for device incompatibility either implied or stated in this Cross Reference Guide.

Compatibility must be verified by the user.

Bold: Direct replacement (See above Note); Italics: Similar replacement; Blank: Either no replacement or no footprint compatible package.

LCX DATA

5

MOTOROLA

BR1339 — REV 3

Introducing LCX

Motorola’s 3V LCX family features 5V–tolerant inputs and outputs that enable easy transition from 5V to mixed 3V/5V systems

or to 3V systems. Low power, low switching noise and fast switching speeds make this family perfect for low power portable

applications as well as high–end, advanced workstation applications.

The unique feature of this family is its ability to interface to pure 3V or both 3V and 5V buses in the same design without

sacrificing performance. The LCX family improves system performance by drastically reducing static and dynamic power

consumption which extends battery life for portable and handheld applications. Customers also realize simplified system design

in mixed voltage environments, as well as expedited development of their low voltage systems. The 3V/5V interface using LCX,

requires no other special components that would be necessary to protect other low voltage logic families that cannot tolerate

signals beyond the V

supply level.

CC

The Motorola LCX family is available in industry standard JEDEC SOIC, EIAJ SOIC, SSOP type 2, and TSSOP packages.

LCX family specifications range from –40°C to +85°C. The LCX family was developed in accordance with an alliance including

Motorola and two other major semiconductor suppliers, so there are alternate sources available now.

• Designed for 2.7 to 3.6V V

CC

Operation

• 5V Tolerant — Interface Capability With 5V TTL Logic

• Supports Live Insertion/Withdrawal (3–State Devices)

• I

OFF

Specification Guarantees High Impedance When V

(3–State Devices)

= 0V

CC

• LVTTL Compatible

• LVCMOS Compatible

• 24mA Balanced Output Sink and Source Capability

• Near Zero Static Supply Current in All Three Logic States (10µA)

Substantially Reduces System Power Requirements

• Latchup Performance Exceeds 500mA

• ESD Performance: Human Body Model >2000V; Machine Model >200V

To assist the designer in evaluating the performance of Motorola’s LCX family, data specifications and actual performance

information are included here.

ABSOLUTE MAXIMUM RATINGS*

Symbol

CC

Parameter

DC Supply Voltage

Value

Condition

Unit

V

–0.5 to +7.0

DC Input Voltage

–0.5 ≤ V ≤ +7.0

V

I

DC Output Voltage

–0.5 ≤ V ≤ +7.0

Output in 3–State

Note 1.

V

O

–0.5 ≤ V ≤ V

+ 0.5

V

O

CC

I

DC Input Diode Current

DC Output Diode Current

–50

V < GND

mA

°C

IK

I

V

O

< GND

OK

+50

V > V

O CC

I

DC Output Source/Sink Current

DC Supply Current Per Supply Pin

DC Ground Current Per Ground Pin

Storage Temperature Range

±50

O

±100

CC

GND

T

–65 to +150

STG

* Absolutemaximumcontinuousratingsarethosevaluesbeyondwhichdamagetothedevicemayoccur. Exposuretotheseconditionsorconditions

beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.

1. Output in HIGH or LOW State. I absolute maximum rating must be observed.

O

MOTOROLA

6

LCX DATA

BR1339 — REV 3

LCX Family Specifications

RECOMMENDED OPERATING CONDITIONS

Symbol

CC

Parameter

Min

Typ

Max

Unit

V

Supply Voltage

Operating

Data Retention Only

2.0

1.5

3.3

3.6

V

Input Voltage

0

5.5

V

I

Output Voltage

(HIGH or LOW State)

(3–State)

0

V

CC

O

5.5

–24

24

I

HIGH Level Output Current, V

= 3.0V – 3.6V

mA

°C

OH

OL

OH

OL

CC

LOW Level Output Current, V

= 3.0V – 3.6V

= 2.7V – 3.0V

CC

HIGH Level Output Current, V

–12

12

CC

LOW Level Output Current, V

CC

T

A

Operating Free–Air Temperature

Input Transition Rise or Fall Rate, V from 0.8V to 2.0V,

–40

0

+85

10

∆t/∆V

ns/V

IN

V

CC

= 3.0V

DC ELECTRICAL CHARACTERISTICS

T

A

= –40°C to +85°C

Symbol

Characteristic

HIGH Level Input Voltage (Note 2.)

LOW Level Input Voltage (Note 2.)

HIGH Level Output Voltage

Condition

Min

2.0

Max

Unit

V

2.7V ≤ V

≤ 3.6V

IH

CC

2.7V ≤ V

≤ 3.6V

= –100µA

0.8

V

IL

CC

≤ 3.6V; I

V

– 0.2

V

OH

CC

OH

CC

V

CC

V

CC

V

CC

= 2.7V; I

= 3.0V; I

= –12mA

= –18mA

= –24mA

2.2

OH

2.4

2.2

V

LOW Level Output Voltage

2.7V ≤ V

CC

≤ 3.6V; I

= 100µA

OL

0.2

0.4

V

OL

V

= 2.7V; I = 12mA

OL

CC

V

= 3.0V; I

= 16mA

= 24mA

0.4

OL

0.55

±5.0

I

Input Leakage Current

3–State Output Current

2.7V ≤ V

CC

≤ 3.6V; 0V ≤ V ≤ 5.5V

µA

I

2.7 ≤ V

CC

≤ 3.6V; 0V ≤ V ≤ 5.5V;

O

I

OZ

V = V or V

IH

IL

I

Power–Off Leakage Current (Note 3.)

Quiescent Supply Current

V

= 0V; V or V = 5.5V

10

µA

OFF

CC

I

O

2.7 ≤ V

≤ 3.6V; V = GND or V

CC

I

CC

2.7 ≤ V

CC

≤ 3.6V; 3.6 ≤ V or V ≤ 5.5V

±10

500

I

O

∆I

Increase in I

per Input

2.7 ≤ V

CC

≤ 3.6V; V = V

IH

– 0.6V

CC

2. These values of V are used to test DC electrical characteristics only.

I

3. I

OFF

is applicable only to devices with 3–state outputs.

DYNAMIC SWITCHING CHARACTERISTICS

T

A

= +25°C

Symbol

Characteristic

Condition

Min

Typ

0.8

Max

Unit

V

Dynamic LOW Peak Voltage (Note 4.)

Dynamic LOW Valley Voltage (Note 4.)

V

= 3.3V, C = 50pF, V = 3.3V, V = 0V

L IH IL

OLP

CC

= 3.3V, C = 50pF, V = 3.3V, V = 0V

IH IL

V

OLV

CC

L

4. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is

measured in the LOW state.

LCX DATA

7

MOTOROLA

BR1339 — REV 3

LCX Family Specifications

CAPACITIVE CHARACTERISTICS

Symbol

Parameter

Condition

= 3.3V, V = 0V or V

Typical

Unit

pF

C

Input Capacitance

V

7

IN

CC

I

CC

Output Capacitance

= 3.3V, V = 0V or V

8

pF

OUT

I/O

PD

I

Input/Output Capacitance (Note 5.)

Power Dissipation Capacitance

= 3.3V, V = 0V or V

pF

I

10MHz, V

= 3.3V, V = 0V or V

CC

Note 6.

pF

CC

I

5. Bidirectional devices only.

6. Function dependent, see individual datasheets.

2.7V

1.5V

t

0V

w

2.7V

t

w

1.5V

0V

PULSE WIDTH

= t = 2.5ns (or fast as required) from 10% to 90%;

Output requirements: V ≤ 0.8V, V ≥ 2.0V

OL OH

t

R

F

Figure 1. LCX AC Waveforms

V

CC

6V

OPEN

GND

R

1

PULSE

GENERATOR

DUT

R

T

C

L

R

L

TEST

SWITCH

Open

6V

t , t

PLH PHL

t , t

PZL PLZ

Open Collector/Drain t

PLH

and t

PHL

6V

t

, t

GND

PZH PHZ

C

L

R

L

R

T

= 50pF or equivalent (Includes jig and probe capacitance)

= R = 500Ω or equivalent

1

OUT

= Z

of pulse generator (typically 50Ω)

Figure 2. LCX Test Circuit

MOTOROLA

8

LCX DATA

BR1339 — REV 3

LCX Family Specifications

V

CC

50%

t

0V

w

V

CC

t

w

0V

PULSE WIDTH

= t = 2.5ns (or fast as required) from 10% to 90%;

Output requirements: V ≤ 0.8V, V ≥ 2.0V

OL OH

t

R

F

Figure 3. LVX AC Waveforms

V

CC

2 × V

CC

OPEN

R

1

PULSE

GENERATOR

DUT

R

T

C

L

R

L

TEST

PLH PHL PZH PHZ

SWITCH

t

, t

Open

, t

PZL PLZ

2 × V

CC

C

L

R

L

R

T

= 50pF or equivalent (Includes jig and probe capacitance)

= R = 500Ω or equivalent

1

OUT

= Z

of pulse generator (typically 50Ω)

Figure 4. LVX Test Circuit

LCXxxx Devices

V

CC

– 0.2V

2.7V

V

CC

2.0V

0.8V

0.2V

0V

AC TEST

INPUT LEVELS

DC LOW

INPUT RANGE

LOW LEVEL

NOISE

DC HIGH

INPUT RANGE

HIGH LEVEL

NOISE

TRANSITION

REGION

IMMUNITY

Figure 5. Test Input Signal Levels

LCX DATA

BR1339 — REV 3

9

MOTOROLA

LCX Family Specifications

Test Conditions

Figure 5 describes the input signal voltage levels to be

used when testing LCX circuits. The AC test conditions follow

fall time is slow enough, then the device may go into

oscillation. As device propagation delays become shorter, the

inputs will have less time to rise or fall through the threshold

region. As device gains increase, the outputs will swing more,

creating more induced voltage. Instantaneous current change

will be greater as outputs become quicker, generating more

induced voltage.

industry convention requiring V to range from 0 V for a logic

IN

LOW to 2.7V for a logic HIGH. The DC parameters are

normally tested with V at guaranteed input levels, that is V

to V (see datasheets for details). Care must be taken to

IL

I

IH

adequately decouple these high performance parts and to

protect the test signals from electrical noise. In an electrically

noisy environment, (e.g., a tester and handler not specifically

designed for high speed work), DC input levels may need

adjustment to increase the noise margin allowance for the

tester. This noise will not likely be seen in a system

environment.

Package–related causes of output oscillation are not

entirely to blame for problems with input rise and fall time

measurements. All testers have V

and ground leads with

CC

some finite inductance. This inductance must be added to the

inductance of the package to determine the overall voltage

which will be induced when the outputs change. As the

referencefortheinputsignalsmovesfurtherawayfromthepin

under test, the test will be more susceptible to problems

caused by the inductance of the leads and stray noise. Any

noise on the input signal will also cause problems.

Noise immunity testing is performed by raising V to the

I

nominal supply voltage of 3.3V then dropping to a level

corresponding to V characteristics, and then raising it again

IH

to the 3.3V level. Noise tests are performed on the V

IL

characteristics by raising V from 0 V to V , then returning to

I

IL

0 V. Both V and V noise immunity tests should not induce

IH

IL

Enable and Disable Times

a switch condition on the appropriate outputs of the LCX

device.

Figure 9 and Figure 10 show that the disable times are

measured at the point where the output voltage has risen or

Good high frequency wiring practices should be used in

constructing test jigs. Leads on the load capacitor should be

as short as possible to minimize ripples on the output wave

form transitions and to minimize undershoot. Generous

ground metal (preferably a ground plane) should be used for

fallen by 0.3V from the voltage rail level (i.e., ground for t

PLZ

or V

for t ). This change enhances the repeatability of

PHZ

CC

measurements, reduces test times, and gives the system

designer more realistic delay times to use in calculating

minimum cycle times. Since the high–impedance state rising

or falling waveform is RC–controlled, the first 0.3V of change

is more linear and is less susceptible to external influences.

More importantly, perhaps from the system designer’s point of

view, a change in voltage of 0.3V is adequate to ensure that

a device output has turned OFF. Measuring to a larger change

in voltage merely exaggerates the apparent Disable time

artificially penalizing system performance (since the designer

must use the Enable and Disable times to figure worst case

timing.)

the same reasons. A V

provided at the test socket, also with minimum lead lengths.

bypass capacitor should be

CC

Rise and Fall Times

Input signals should have rise and fall times of 2.5ns or less

(10% to 90%), and signal swing of 0V to 2.7V. Rise and fall

times less than or equal to 1ns should be used for testing f

or pulse widths.

max

CMOS devices tend to oscillate when the input rise and fall

times become lengthy. As a direct result of its increased

performance, LCXdevicescanbemoresensitivetoslowinput

rise and fall times than other lower performance technologies.

Recommended edge rate is ≤10ns/V.

It is important to understand why this oscillation occurs.

Consider the outputs, where the problem is initiated. Usually,

CMOS outputs drive capacitive loads with low DC leakage.

When the output changes from a HIGH level to a LOW level,

or from a LOW level to a HIGH level, this capacitance is

charged or discharged. With the present high performance

technologies, charging or discharging takes place in a very

short time, typically 2–3ns. The requirement to charge or

discharge the capacitive loads quickly creates a condition

where the instantaneous current change through the output

Propagation Delay, f

Recovery Times

Set, Hold, and

max,

A 1 MHz square wave is recommended for most

propagation delay tests. The repetition rate must necessarily

be increased for testing f

be used when testing f

max

required for testing such parameters as setup time (t ), hold

. A 50% duty cycle should always

. Two pulse generators are usually

max

s

time (t ), recovery time (t

) shown in Figure 8.

h

REC

Electrostatic Discharge

Precautions should be taken to prevent damage to devices

by electrostatic discharge. Static charge tends to accumulate

on insulated surfaces such as synthetic fabrics or carpeting,

plastic sheets, trays, foam, tubes or bags, and on ungrounded

electrical tools or appliances. The problem is much worse in

a dry atmosphere. In general, it is recommended that

individuals take the precaution of touching a known ground

before handling devices. To effectively avoid electrostatic

damage to LCX devices, it is recommended that individuals

wear a grounded wrist strap when handling devices. More

often, handling equipment, which is not properly grounded,

causes damage to parts. Ensure that all plastic parts of the

tester, which are near the device, are conductive and

connected to ground.

structure is quite high. A voltage is generated across the V

CC

or ground leads inside the package due to the lead

inductance. The internal ground of the chip will change in

reference to the outside world because of this induced

voltage.

Next, consider the inputs. If the internal ground changes,

the input voltage level appears to change to the DUT. If the

input rise time is slow enough, its level might still be in the

threshold region, or very close to it, when the output switches.

If the internally–induced voltage is large enough, it is possible

to shift the threshold enough so that it re–crosses the input

level. If the gain of the device is sufficient and the input rise or

MOTOROLA

10

LCX DATA

BR1339 — REV 3

LCX Family Specifications

t

w

CONTROL

IN

V

m

DATA

IN

V

m

t

rec

tpxx

V

m

CLOCK

DATA

OUT

V

m

t

PHL

t

PLH

V

m

V

m

OUTPUT

V

= 1.5V

m

Figure 6. Waveform for Inverting and

Non–Inverting Functions

Figure 7. Propagational Delay, Pulse Width and

Waveforms

t

rec

DATA

IN

V

m

OUTPUT

CONTROL

V

m

t

s

t

h

CONTROL (CLOCK)

INPUT

t

PHZ

V

m

PZH

V

OH

CC

– 0.3V

DATA

OUT

V

m

t

rec

MR

OR

CLEAR

V

m

Figure 8. Setup Time, Hold Time and Recovery Time

Figure 9. 3–State Output High Enable and

Disable Times

OUTPUT

CONTROL

V

m

t

PZL

t

PLZ

DATA

OUT

V

m

V

+ 0.3V

OL

GND

V

= 1.5V

m

Figure 10. 3–State Output Low Enable and Disable Times

LCX DATA

11

MOTOROLA

BR1339 — REV 3

Definitions of Symbols

DC Characteristics

AC Characteristics

Currents Positive current is defined as conventional current

flow into a device. Negative current is defined as

current flow out of a device.

f

Toggle Frequency/Operating Frequency – The

max

maximum rate at which clock pulses may be applied to a

sequential circuit. Above this frequency the device may cease

to function properly.

Voltages All voltages are referenced to the ground pin.

I

The current flowing into the V supply terminal

CC

t

Propagation Delay Time – The time between the

PLH

when the device is at a quiescent state.

The current flowing into the V supply terminal

specified reference points, on the input and output voltage

waveforms, with the output changing from the defined LOW

level to the defined HIGH level.

CCH

CCL

CCZ

CC

when the outputs are in the HIGH state.

The current flowing into the V

supply terminal

CC

when the outputs are in the LOW state.

t

Propagation Delay Time – The time between the

PHL

specified reference points, on the input and output voltage

waveforms, with the output changing from the defined HIGH

level to the defined LOW level.

The current flowing into the V

supply terminal

CC

when the outputs are disabled (high impedance).

∆I

CC

AdditionalI duetoTTLHIGHlevels(V –0.6V)

CC

forced on CMOS inputs.

CC

t

Pulse Width – The time between specified amplitude

w

points of the leading and trailing edges of a pulse.

I

Input Current. The current flowing into or out of an

input when a specified LOW or HIGH voltage is

applied to that input.

t

Hold Time – The interval immediately following the active

h

transition of the timing pulse (usually the clock pulse) or

following the transition of the control input to its latching level,

during which interval the data to be recognized must be

maintained at the input to ensure its continued recognition.

I

Output HIGH Current. The current flowing out of an

output which is in the HIGH state.

OH

OL

OS

Output LOW Current. The current flowing into an

output which is in the LOW state.

t SetupTime–Theintervalimmediatelyprecedingtheactive

s

Output Short Circuit Current. The current flowing

out of an output in the HIGH state when that output

is shorted to ground (or other specified potential).

transition of the timing pulse (usually the clock pulse) or

preceding the transition of the control input to its latching level,

during which interval the data to be recognized must be

maintained at the input to ensure its recognition.

I

Output high impedance current. The current

flowing into or out of a disabled output when

specified LOW or HIGH voltage is applied to that

output.

OZ

t

OutputDisableTime(ofa3–stateOutput)fromHIGH

PHZ

Level – The time between specified levels on the input and a

voltage 0.3V below the steady state output HIGH level with the

3–state output changing from the defined HIGH level to a high

impedance (OFF) state.

I

Input/Output power–off leakage current. The

maximum leakage current into or out of the

input/output transistors when forcing the

OFF

input/output from 0V to 5.5V with V

= 0V.

CC

t

Output Disable Time (of a 3–state Output) from LOW

PLZ

V

Supply Voltage. The range of power supply

voltages over which the device is guaranteed to

operate.

CC

Level – The time between specified levels on the input and a

voltage 0.3V above the steady state output LOW level with the

3–state output changing from the defined LOW level to a high

impedance (OFF) state.

V

Input HIGH Voltage. The minimum input voltage

that is recognized as a DC HIGH level.

IH

t

Output Enable Time (of a 3–state Output) to a HIGH

PZH

Input LOW Voltage. The maximum input voltage

that is recognized as a DC LOW level.

IL

Level – The time between the specified levels of the input and

output voltage waveforms with the 3–state output changing

from a high impedance (OFF) state to a HIGH level.

Output HIGH Voltage. The voltage at an output

conditioned HIGH with a specified output load and

OH

t

Output Enable Time (of a 3–state Output) to a LOW

V

supply voltage.

PZL

CC

Level – The time between the specified levels of the input and

output voltage waveforms with the 3–state output changing

from a high impedance (OFF) state to a LOW level.

V

Output LOW Voltage. The voltage at an output

conditioned LOW with a specified output load and

V

OL

supply voltage.

CC

V

Maximum (peak) voltage induced on a static LOW

output during switching of other outputs.

OLP

OLV

t

RecoveryTime–Thetimebetweenthespecifiedlevelon

rec

the trailing edge of an asynchronous input control pulse and

the same level on a synchronous input (clock) pulse such that

the device will respond to the synchronous input.

Minimum (valley) voltage induced on a static LOW

output during switching of other outputs.

MOTOROLA

12

LCX DATA

BR1339 — REV 3

LCX Family Characteristics

LCX and LVT Products

Product Family

74LCX244

74LVC244A

74LVT244A

BiCMOS

12.0

Technology

CMOS

0.01

CMOS

I

(mA)

0.01

145mA

6.5ns

CCL

vs Frequency (50MHz)

130mA

6.5ns

275mA

CC

Speed

4.1ns

Drive (2.0V/0.55V)

JEDEC (2.4V/0.4V)

>–24mA/24mA

–18mA/16mA

–24mA/24mA

–12mA/???

–32mA/64mA

–8mA/16mA

5V Tolerant

Inputs

Outputs

YES

YES*

Power–Down High–Z (I

)

YES (10µA)

NO

YES (±100µA)

OFF

Data Retention

YES

NO

* LVT claims, but does not specify, 5V–Tolerant outputs. LCX can be used to replace LVC; be careful when exchanging LCX with LVC as not all

LVC functions have 5V–tolerance!!

The following graph compares the 5V–tolerance capability of LCX, LVC and LVT. When LCX is not driving the bus (outputs are

disabled), the levels on that bus can exceed the LCX V

test data shows that a disabled LCX output can “tolerate” signals over 13V on the outputs!

with no adverse effect on the device or any loading on the bus. In fact,

CC

5V Output Tolerance

(I

vs V , V = 2.7V, +25°C)

OZ

out CC

100

75

50

25

0

LCX244

LVT244A

LVC244A

2

4

6

8

10

12

14

V

out

(V)

LCX DATA

BR1339 — REV 3

13

MOTOROLA

LCX Family Characteristics

Another advantage of the LCX family is the low dynamic current. Low dynamic current means low power consumption. Low

power consumption means smaller power supplies, longer battery life and physically smaller systems. The following graph

shows the Motorola 74LCX245’s I

that can be had with low voltage logic, a 74LCX245 consumes about the same power running at 35MHz that a 74F245 does

statically. At 100MHz the LCX device only consumes about 200mA.

vs. Frequency performance with 8 outputs switching. To give an idea of power improvement

CC

I

versus Frequency

CC

(25°C, 3.3V)

400

350

300

250

200

150

100

50

LCX245

LVT245

LVC245

0

10

20

30

40

50

60

70

80

90

100

Frequency

MOTOROLA

14

LCX DATA

BR1339 — REV 3

LCX Family Characteristics

mixed supply interface problem. These devices are not

overvoltage tolerant, but rather true voltage translators —

meaning that they receive 3V signals and output 5V signals,

and receive 5V signals and output 3V signals (which can also

be accomplished with LCX). This is done by dividing the

devices internally so that the A–side circuitry is isolated from

the B–side circuitry. The dual supply architecture allows the

LVX translators to interface 3V and 5V signals with near–zero

static power dissipation.

LCX — Low–Voltage CMOS Logic (WIth

5V–Tolerant Inputs and Outputs)

The LCX family represents Motorola’s Low–Voltage

CMOS family. These devices offer mixed 3V–5V capability

and are recommended for applications where 3.3V and 5V

subsystems interface with one another and where low power

consumption is a necessity. The input and output (Note 1)

structures of the LCX family of products will tolerate input and

output node exposure to signals or DC levels that exceed the

The MC74LVX4245 A–side is dedicated to 5V operation,

V

level (Note 2). Refer to Figure 11 for schematic

CC

with V

specified over the 4.5V–5.5V range. The B–side is

CCA

description of a typical LCX circuit. Note that the output

PMOS device P1 has its bulk potential supplied by the output

dedicated to 3.3V, with V

range.

specified over the 2.7V–3.6V

CCB

of the comparator X1 rather than by V

CMOS. The circuitry contained within the comparator is

designed such that the output is always the greater of V or

as in conventional

CC

The MC74LVXC3245 offers enhanced interfacing

features. The B–side is designed to operate over an

CC

V . This technique circumvents the P+/N– bulk–source

extended range of I/O and supply levels. The V

permitted to be set to any value between 2.7V and 5.5V. The

I/O levels on the B–side will track or scale automatically

is

O

CCB

forward junction that usually appears between the PMOS

drain at the output and the bulk connection of the output

PMOS which is usually tied to V . Eliminating this junction is

according to the level set on V

. The B–side operation is

CC

CCB

. The A–port and control

fundamental to the powered–down high Z and overvoltage

tolerance features that distinguish Motorola’s LCX family

from other Low–Voltage CMOS products.

completely independent of V

CCA

input buffers are referenced to V

, totally independent of

CCA

. The configurable dual supply translating transceiver,

V

CCB

LVXC3245, is designed to tolerate floating inputs on the

B–port when V and the control signals are set to valid

NOTE 1: U.S. Patent 5,451,889.

NOTE 2: Output overvoltage is permitted unconditionally for 3–stated outputs.

For active outputs, see datasheet.

CCA

operating levels. The combination of this on–the–fly interface

flexibility together with “empty socket” tolerance is intended

to benefit designers of PC card systems (or PCMCIA) where

expansion cards with different supply potentials must be

accommodated.

LVX-Low Voltage Dual Supply Translating

Transceivers

In applications where 3.3V signals must be “stepped up” to

5V, in order to interface full swing CMOS busses, LCX may

not be the proper solution. The LVX translating transceiver

designs have an entirely different approach to solve the

The LVX dual supply translators offer switching speeds

equivalent to 5V FCT/FAST but with low ground noise and

very low power dissipation.

Input Stage

V

CC

Data

X1

V

DD

P1

Output

Input Stage

Enable

Figure 11. Simplified LCX Schematic Diagram

LCX DATA

15

MOTOROLA

BR1339 — REV 3

LCX Applications Information

tolerant, rather than 3.3V/5V translation which is a misnomer.

(Products that are powered by 3.3V supplies do not drive 5V

rail–to–rail output swings. Dual 3.3V/5V supply devices are

needed to drive 5V CMOS level outputs. See 74LVXC3245

and 74LVX4245–translating transceivers.)

Introduction

Many system designers concerned about reducing power

in mobile computing and communications are unnecessarily

avoiding the use of 3.3V products because of either cost or

the dreaded 3V/5V interface. Cost may be a concern, but

nearly every new 3.3V device has better performance –

either increased speed, reduced power, or both – when

compared to a 5V “counterpart”. In the long run it could easily

cost the equipment maker more to continue with older

technology rather than make the move to 3.3V or mixed

3.3V/5V systems.

There is no longer reason to fear mixed voltage designs.

The LCX CMOS family is available now to help you bridge the

3.3V–5V interface.

Interfacing Dual Systems

To properly interface between integrated circuits, it is

imperative that input and output specifications be reviewed

and voltage and current levels satisfied. Output

There are three major reasons that chip manufacturers are

accelerating the introduction of low voltage devices.

First–DRAM manufacturers are worried about damage to

products with fine geometries. As memory becomes more

dense, feature geometries by necessity shrink. Voltages as

high as 5V would damage these compactly designed RAMs.

Second–as processor manufacturers have increased the

performance of their chips, they have found that packages

could not handle the increased power dissipation need. The

enabling factor was to move to 3.3V supplies. Power

dissipation varies roughly by the ratio of the squares of the

specifications (V

or exceed the input requirements (V

and V ) of the driving device must meet

OH

OL

and V ) of the

IL

IH

receiving device for the interface to function properly.

Meeting these requirements protects against malfunction

when operating at different environments which may induce

noise to the interface.

The 5V power supply has been the standard for many

years in the IC world. Several product families have been

introduced with varying speeds, drive capabilities, and power

requirements. Because of this many I/O standards have

evolved complicating the interface between 5V devices. The

move to 3.3V power supplies actually simplifies the interface

problem. Pure Bipolar products cannot function at 3.3V, so

the core technology is either BiCMOS or pure CMOS. In a

pure 3.3V MOS environment the interface can be made

directly–inputs and outputs. However, it will be several years

before all system components operate from 3.3V supplies.

This is especially true for peripheral devices such as printers,

displays, and faxes.

2

(V )(capacitance)(frequency)), so the ratioof

CC

V

s, (P

CC

D

2 2

reduction in power is 3.3 /5 (11/25) when moving from 5V to

3.3V. Third–Battery–powered system manufactures are

continually working for extended battery life. Obviously a

56+% reduction in power would considerably extend battery

life. There are other benefits as well. Smaller packaging can

be used to house the low voltage chips–saving board space

and making the end product smaller and lighter. Smaller or

fewer power supplies are required, and costly, space–

hogging heat dissipating equipment can be eliminated.

Most 3.3V logic families can directly interface with only

3.3V products. LVC, LVX, VHC, LVQ/FACT AC, FCT3, and

HC product families are lines that may work well for pure 3.3V

system interface. Of these families only LVX and redesigned

LVC guarantee 5V–tolerant inputs. The other families can

Interfacing 5V–TTL to Pure 3.3V Logic

(No 5V–Tolerance)

When the desired interface is 5V–TTL to pure 3.3V CMOS

(such as FACT AC or LVQ), the solution becomes a little

messy. The designer must make sure that the 5V–TTL

outputs do not exceed the 3.3V CMOS input specifications.

There are a few options available to protect the 3.3V device

from excessive input current. The 3.3V and 5V power

supplies should be regulated together. It would also be a

benefit to run the 5V supply on the low side reducing the

tolerate maximum input and output levels of only V +0.5V. If

CC

a 5V TTL bus voltage swings to levels that exceed these

specifications then the non 5V–tolerant products may be

damaged, destroyed, load the bus, or current may be

sourced into the 3.3V supply. Not only is it important to be

5V–tolerant on the inputs but to be 5V–tolerant on the outputs

as well.

V

–V difference. If, however, the power supplies are not

CC OH

The LCX logic family provides the necessary circuitry to

bridge the technology gap between the 5V and 3.3V worlds.

The inputs of this low voltage family can be safely driven to

5.5V, guaranteed, easily handling a 5V TTL or 5V CMOS

interface on the input bus. When the LCX device outputs, or

I/Os, have finished their tasks and are in the high–impedance

state, the voltage levels on the bus to which they are tied may

regulated together and the supplies end up at 5V+10% and

3.3V–10% then the CMOS input specifications would likely

be violated. To keep within the CMOS input specification the

5V–TTL output cannot exceed 0.5V + V

device. The simplest way to insure that V

of the CMOS

remains within

CC

OH

the input specification of the CMOS part is to use a parallel

termination resistor tied to ground. There are also CMOS

switches that can be placed between the 5V and 3.3V

rise well above the 3.3V V , up to 5.5V without loading the

CC

bus or causing damage to the device or power supply,

guaranteed. This capability has been properly termed 5V

devices to reduce the V

expensive.

, but this solution is very

OH

MOTOROLA

16

LCX DATA

BR1339 — REV 3

LCX Applications Information

contention. Care must be taken to ensure that the LCX

device is 3–Stated when there are 5V signals present on the

bus.

Interfacing 5V–CMOS to Pure 3.3V Logic

(No 5V–Tolerance)

When the interface is a 5V CMOS device and a 3.3V

CMOS device without 5V–tolerance, the problem is much the

same as with the 5V–TTL interface–but worse. The output of

the 5V device must be reduced or large currents will flow into

the 3.3V device. This type of interface is simply not

recommended.

Five volt signals can also be caused by the use of pull–ups

on the 5V bus. Similarly, certain 5V devices with internal

pull–ups may cause leakage current into an LCX enabled

output. Pay close attention to the 5V device input

specification to see if there are input pull–ups to a 5V supply.

LCX can drive a 5V–TTL input even if that input has an

internal pull–up, but the user should be aware that when

driving this type of input, some leakage current into the low

Interfacing Pure 3.3V Logic to 5V Inputs

(No 5V Output Tolerance)

voltage supply will occur. The value of this current, I , is

O

Interfacing 3.3V CMOS to 5V–TTL inputs can be done

directly. LVCMOS/LVTTL output specifications and 5V–TTL

input specifications are compatible. However, when

interfacing pure 3.3V parts (no 5V–tolerance) to a 5V bus

there is no protection against 5V signals when the 3.3V

output is disabled. If the 5V bus voltage levels exceed the

simply the 5V supply voltage value minus the 3.3V supply

voltage value divided by the pull–up resistor value.

(I =(V 5–V 3)/R ).Ifthepull–upresistoris10Kohmsfor

O

CC

pu

example, the resultant current would be 1.7V/10K=170µA

per output. In this case, there would be no reliability concern.

The specified Absolute Maximum I /I

Current (100mA

CC GND

V

of the 3.3V device, leakage current into the 3.3V device

CC

per supply/ground pin) must also be considered. For an octal

device, the current resulting from a pull–up to 5V must be

limited to 100mA/8 outputs = 12.5mA/output. 12.5mA, using

5V and 3.3V supplies, would necessitate limiting the pull–up

value to 136 ohms. Not until the 12.5mA/output value is

approached would there begin to be a chip reliability concern.

It is assumed that a low–voltage design power budget would

will occur–loading the bus. Also, be aware of 5V buses with

pull–up resistors. If pull–up resistors are used then pull–down

resistors may be necessary to compensate and reduce the

high voltage level to within the 0.5V + V

range of the 3.3V

CC

device. Interfacing a 3.3V CMOS output to a 5V CMOS input

is discouraged. The output swing of the 3.3V device is

insufficient to reliably drive the 5V CMOS device without the

assistance of a pull–up resistor. If a pull–up resistor to 5V

be spent long before the Absolute Maximum I /I

CC GND

Current specification would come into play.

V

is used to raise the input level to the required V =3.15V

CC

(for V =5V, higher for higher V s) then a massive current

IH

An LCX output is not recommended to drive a 5V CMOS

CC

input. As noted in the previous section, the V

level of the

OH

flow may result into the 3.3V device.

LCX output is not High enough to reliably drive a 5V CMOS

input. (Either an open–drain output device or dual supply

translator is recommended to drive a 5V CMOS input.)

Interfacing to 5V–Tolerant LCX CMOS Logic

Many of the problems and concerns associated with pure

3.3V interface can be resolved simply by using 5V–tolerant

LCX CMOS Logic. LCX tolerates 5V–TTL or 5V CMOS levels

on its inputs. There is no inherent leakage path that can

damage the device or in any way adversely affect this

interface.

LCX Makes Power Management Easy

LCX also offers an advanced feature which can be used to

isolate powered–down subsystems from active 3.3V or 5V

buses. The LCX’ I

specification guarantees, when the

OFF

= 0V and the voltage present on the LCX’ output,

LCX’ V

CC

The 5V–tolerant output feature protects the 3.3V bus from

high signal excursions on the 5V bus when the 3.3V bus is

inactive (3–State). Only LCX devices with 3–State capability

have 5V–tolerant outputs. Gates and MSI products without

3–State have 5V–tolerant inputs but not 5V–tolerant outputs.

When an LCX device is enabled, the 5V output tolerance is

not active and will not protect the LCX device in cases of bus

V , is 5.5V or less, that the LCX’ output will sink less than

O

10µA (typically the value is < 1µA). In other words, when V

CC

= 0V, LCX is still 5V–tolerant on both the inputs and outputs.

Using this feature a system designer can use LCX to buffer

powered–down sections of a board, from active sections,

easily implementing advanced power manage– ment. See

Figure 13.

LCX DATA

17

MOTOROLA

BR1339 — REV 3

LCX Applications Information

3V

Bulk–Biased

5V–Tolerant

Circuitry

5V Cache

SRAM

3–State

Control

5V DRAM

3V CPU

Output

LCX244

LCX373

OE

3.3V Host Bus

5V–Tolerant

Input

LCX

245

3V

Core

Logic

LCX373

Input

LCX Gates

Video

DRAM

LCD/Video

ROM

BIOS

LCX244

5V I/O Bus

Module

L

C

X

• Docking Station

• PCMCIA

• Ethernet

• Fax/Modem

• Token Ring

IDE

Drive

Super

I/O

EIA

232

Keyboard

µC

RTC

• Wireless Comm/LAN

LCX245

Figure 12. LCX System Block Diagram

Power Down

= 0V

V

CC

= 5V or 3V

V

CC

5V or 3V

Pull OE to V

CC

(Optional)

Active

Devices

I

< 10µA

L

C

X

OFF

Powered

Down

Devices

Active

Devices

LCX Signal Pins –

High Impedance

Active

Devices

LCX will isolate active and

powered down subsystems. . .

POWERED DOWN SUBSYSTEM

ACTIVE SUBSYSTEM

Figure 13. LCX Provides Power Management

MOTOROLA

18

LCX DATA

BR1339 — REV 3

Design Considerations

The LCX family was designed to alleviate many of the

drawbacks that are common to current low–voltage logic

circuits. LCX combines the low static power consumption and

the high noise margins of CMOS with a high fan–out, low input

loading and a 50Ω transmission line drive capability.

where

T

= maximum junction temperature

= maximum ambient temperature

= calculated maximum power dissipation including

effects of external loads (see Power Dissipation in

J

T

A

P

D

Performance features such as 5ns speeds at CMOSpower

levels, ±24mA drive, excellent noise, ESD and latch–up

section III).

immunity

are

characteristics

that

designers

of

Θ

= average thermal resistance, junction to case

= average thermal resistance, case to ambient

= average thermal resistance, junction to ambient

JC

CA

JA

state–of–the–art systems require. LCX provides this level of

performance. To fully utilize the advantages provided by LCX,

the system designer should have an understanding of the

flexibility as well as the trade–offs of CMOS design. The

following section discusses common design concerns relative

to the performance and requirements of LCX.

This Motorola recommended formula has been approved

by RADC and DESC for calculating a “practical” maximum

operating junction temperature for MIL–M–38510 (JAN)

devices.

Only two terms on the right side of equation (1) can be

varied by the user — the ambient temperature, and the device

There are six items of interest which need to be evaluated

when implementing LCX devices in new designs:

• Thermal Management — circuit performance and long–

case–to–ambient thermal resistance, Θ . (To some extent

the device power dissipation can also be controlled, but under

CA

term circuit reliability are affected by die temperature.

recommended use the V

supply and loading dictate a fixed

CC

power dissipation.) Both system air flow and the package

mounting technique affect the Θ thermal resistance term.

• Interfacing — interboard and technology interfaces, battery

backup and power down or live insert/extract systems

require some special thought.

CA

is essentially independent of air flow and external

Θ

JC

• Transmission Line Driving — LCX has excellent line driving

mounting method, but is sensitive to package material, die

bonding method, and die area.

capabilities.

For applications where the case is held at essentially a

fixed temperature by mounting on a large or temperature–

controlled heat sink, the estimated junction temperature is

calculated by:

• Noise effects — As edge rates increase, the probability of

crosstalk and ground bounce problems increases. The

enhanced noise immunity and high threshold levels

improve LCX’s resistance to crosstalk problems.

T = T + P (Θ )

JC

(3)

J

C

D

• Board Layout — Prudent board layout will ensure that most

where T = maximum case temperature and the other

C

parameters are as previously defined.

noise effects are minimized.

• Power Supplies and Decoupling — Maximize ground and

V

traces to keep V /ground impedance as low as

CC

possible; full ground/V

Air Flow

planes are best. Decouple any

CC

The effect of air flow over the packages on Θ (due to a

decrease in Θ ) reduces the temperature rise of the

package, therefore permitting a corresponding increase in

power dissipation without exceeding the maximum

permissible operating junction temperature.

JA

device driving a transmission line; otherwise add one

capacitor for every package

CA

Thermal Management

Even though different device types mounted on a printed

circuit board may each have different power dissipations, all

will have the same input and output levels provided that each

is subject to identical air flow and the same ambient air

temperature. This eases design, since the only change in

levels between devices is due to the increase in ambient

temperatures as the air passes over the devices, or

differences in ambient temperature between two devices.

The majority of users employ some form of air–flow

cooling. As air passes over each device on a printed circuit

board, it absorbs heat from each package. This heat gradient

from the first package to the last package is a function of the

air flow rate and individual package dissipations.

Circuit performance and long–term circuit reliability are

affected by die temperature. Normally, both are improved by

keeping the IC junction temperatures low.

Electrical power dissipated in any integrated circuit is a

source of heat. This heat source increases the temperature of

the die relative to some reference point, normally the ambient

temperature of 25°C in still air. The temperature increase,

then, depends on the amount of power dissipated in the circuit

and on the net thermal resistance between the heat source

and the reference point. See the Thermal Management

Considerations Section on page 283 for LCX power

calculations.

The temperature at the junction is a function of the

packaging and mounting system’s ability to remove heat

generated in the circuit — from the junction region to the

ambient environment. The basic formula for converting power

dissipation to estimated junction temperature is:

Optimizing The Long Term Reliability of

Plastic Packages

Todays plastic integrated circuit packages are as reliable

as ceramic packages under most environmental conditions.

However when the ultimate in system reliability is required,

thermal management must be considered as a prime system

design goal.

T = T + P (Θ

+ Θ )

CA

(1)

(2)

J

A

D

JC

T = T + P (Θ )

JA

or

J

A

D

LCX DATA

19

MOTOROLA

BR1339 — REV 3

Design Considerations

Modern plastic package assembly technology utilizes gold

wire bonded to aluminum bonding pads throughout the

electronics industry. When exposed to high temperatures for

protracted periods of time an intermetallic compound can form

in the bond area resulting in high impedance contacts and

degradation of device performance. Since the formation of

intermetallic compounds is directly related to device junction

temperature, it is incumbent on the designer to determine that

the device junction temperatures are consistent with system

reliability goals.

Table 1 is graphically illustrated in Figure 14 which shows

that the reliability for plastic and ceramic devices is the same

until elevated junction temperatures induce intermetallic

failures in plastic devices. Early and mid–life failure rates of

plastic devices are not effected by this intermetallic

mechanism.

FAILURE RATE OF PLASTIC = CERAMIC

UNTIL INTERMETALLICS OCCUR

Predicting Bond Failure Time

Based on the results of almost ten (10) years of +125°C

operating life testing, a special arrhenius equation has been

developed to show the relationship between junction

temperature and reliability.

1

11554.267

1

10

100

1000

–9

(1) T = (6.376 × 10 )e

273.15 + T

TIME, YEARS

J

Where: T

= Time in hours to 0.1% bond failure (1 failure

per 1,000 bonds).

= Device junction temperature, °C.

Figure 14. Failure Rate versus Time

Junction Temperature

T

J

Procedure

And:

After the desired system failure rate has been established

for failure mechanisms other than intermetallics, each device

in the system should be evaluated for maximum junction

temperature. Knowing the maximum junction temperature,

refer to Table 1 or Equation 1 to determine the continuous

operating time required to 0.1% bond failures due to

intermetallic formation. At this time, system reliability departs

from the desired value as indicated in Figure 14.

Air flow is one method of thermal management which

should be considered for system longevity. Other commonly

used methods include heat sinks for higher powered devices,

refrigerated air flow and lower density board stuffing. Since

(2) T = T + P Θ = T + ∆T

D JA J

J

A

Where: T

= Device junction temperature, °C.

= Ambient temperature, °C.

= Device power dissipation in watts.

= Device thermal resistance, junction to air,

°C/Watt.

J

T

A

P

Θ

D

JA

∆T = Increase in junction temperature due to

J

on–chip power dissipation.

Table

1 shows the relationship between junction

temperature, and continuous operating time to 0.1% bond

failure, (1 failure per 1,000 bonds).

Θ

is entirely dependent on the application, it is the

CA

responsibility of the designer to determine its value. This can

be achieved by various techniques including simulation,

modeling, actual measurement, etc.

TABLE 1 — DEVICE JUNCTION TEMPERATURE versus

TIME TO 0.1% BOND FAILURES.

Junction

Temperature °C

The material presented here emphasizes the need to

consider thermal management as an integral part of system

design and also the tools to determine if the management

methods being considered are adequate to produce the

desired system reliability.

Time, Hours

Time, Years

80

1,032,200

419,300

178,700

79,600

37,000

17,800

8,900

117.8

47.9

20.4

9.4

90

100

110

120

130

140

4.2

2.0

1.0

MOTOROLA

20

LCX DATA

BR1339 — REV 3

Design Considerations

Line Driving

Withtheavailablehigh–speedlogicfamilies, designerscan

reach new heights in system performance. Yet, these faster

devices require a closer look at transmission line effects.

Although all circuit conductors have transmission line

properties, these characteristics become significant when the

edge rates of the drivers are equal to or less than three times

the propagation delay of the line. Significant transmission line

properties may be exhibited in an example where devices

have edge rates of 3ns and lines of 8 inches or greater,

assuming propagation delays of 1.7 ns/ft for an unloaded

printed circuit trace.

c: Parallel Termination

d: AC Parallel Termination

Of the many properties of transmission lines, two are of

major interest to the system designer: Z , the effective

oe

pde

equivalent impedance of the line, and t

, the effective

propagation delay down the line. It should be noted that the

intrinsic values of line impedance and propagation delay, Z

o

and t , are geometry–dependent. Once the intrinsic values

are known, the effects of gate loading can be calculated. The

pd

loaded values for Z and t

can be calculated with:

oe

pde

e: Thevenin Termination

Z

o

Z

oe

Figure 15. Termination Schemes

1

C C

t

l

t

1

C C

t

pde

pd

l

Series Terminations

Series terminations are most useful in high–speed

applications where most of the loads are at the far end of the

line. Loads that are between the driver and the end of the line

will receive a two–step waveform. The first wave will be the

incident wave. The amplitude is dependent upon the output

impedanceofthedriver, thevalueoftheseriesresistorandthe

impedance of the line according to the formula

where C = intrinsic line capacitance and C = additional

capacitance due to gate loading.

I

t

The formulas indicate that the loading of lines decreases

the effective impedance of the line and increases the

propagation delay. Lines that have a propagation delay

greater than one third the rise time of the signal driver should

be evaluated for transmission line effects. When performing

transmission line analysis on a bus, only the longest, most

heavily loaded and the shortest, least loaded lines need to be

analyzed. All linesinabusshouldbeterminatedequally;ifone

line requires termination, all lines in the bus should be

terminated. This will ensure similar signals on all of the lines.

There are several termination schemes which may be

used. Included are series, parallel, AC parallel and Thevenin

terminations. AC parallel and series terminations are the most

useful for low power applications since they do not consume

anyDCpower. ParallelandTheveninterminationsexperience

high DC power consumption.

V

= V

/(Z + R + Z )

CC ^{• Z}oe oe

W

S

The amplitude will be one–half the voltage swing if R (the

S

series resistor) plus the output impedance (Z ) of the driver is

S

equal to the line impedance. The second step of the waveform

is the reflection from the end of the line and will have an

amplitude equal to that of the first step. All devices on the line

will receive a valid level only after the wave has propagated

down the line and returned to the driver. Therefore, all inputs

will see the full voltage swing within two times the delay of the

line.

Parallel Termination

Parallel terminations are not generally recommended for

CMOS circuits due to their power consumption, which can

exceed the power consumption of the logic itself. The power

consumption of parallel terminations is a function of the

resistor value and the duty cycle of the signal. In addition,

parallel termination tends to bias the output levels of the driver

Termination Schemes

towards either V

desirable for driving CMOS inputs, it can be useful for driving

TTL inputs.

or ground. While this feature is not

CC

a: No Termination

AC Parallel Termination

AC parallel terminations work well for applications where

the delays caused by series terminations are unacceptable.

TheeffectsofACparallelterminationsaresimilartotheeffects

of standard parallel terminations. The major difference is that

the capacitor blocks any DC current path and helps to reduce

power consumption.

b: Series Termination

LCX DATA

21

MOTOROLA

BR1339 — REV 3

Design Considerations

Thevenin Termination

transformer action. Reverse crosstalk increases linearly with

distance up to a critical length. This critical length is the

distance that the signal can travel during its rise or fall time.

Although crosstalk cannot be totally eliminated, there are

some design techniques that can reduce system problems

resulting from crosstalk. LCX’s industry–leading noise

margins makes it easier to design systems immune to

crosstalk–related problems.

Thevenin terminations are also not generally recommended

due to their power consumption. Like parallel termination, a

DC path to ground is created by the terminating resistors. The

power consumption of a Thevenin termination will generally

not be a function of the signal duty cycle. Thevenin

terminations are more applicable for driving CMOS inputs

because they do not bias the output levels as paralleled

terminations do. It should be noted that lines with Thevenin

terminations should not be left floating since this will cause the

input levels to float between V

consumption.

or ground, increasing power

CC

LCXcircuitshavebeendesignedtodrive50Ω transmission

lines over the full temperature range.

LCX devices also feature balanced totem pole output

structures to allow equal source and sink current capability.

This provides balanced edge rates and equal rise and fall

times. Balanced drive capability and transition times

eliminates the need to calculate two different delay times for

each signal path and the requirement to correct signal polarity

for the shortest delay time.

Noise Effects

LCX offers excellent noise immunity. However, even the

most advanced technology alone cannot eliminate noise

problems. Good circuit board layout techniques are essential

to take full advantage of the superior performance of LCX

circuits.

0.0 V

Well–designed circuit boards also help eliminate

manufacturing and testing problems.

Another recommended practice is to segment the board

into a high–speed area, a medium–speed area and a low–

speed area. The circuit areas with high current requirements

(i.e., buffer circuits and high–speed logic) should be as close

tothepowersuppliesaspossible;low–speedcircuitareascan

be furthest away.

TIME (ns) (5.0 ns/DIV)

Figure 16. Forward Crosstalk on PCB Traces

Decoupling capacitors should be adjacent to all buffer

chips; they should be distributed throughout the logic: one

capacitor per chip. Transmission lines need to be terminated

to keep reflections minimal. To minimize crosstalk, long signal

lines should not be close together.

Key

Vertical Scale Horizontal Scale

Active Driver

Forward Crosstalk

Active Receiver

1.0 V/Div

0.2 V/Div

1.0 V/Div

50 ns/Div

5.0 ns/Div

Crosstalk

This figure shows traces taken on a test fixture designed to exaggerate the

amplitude of crosstalk pulses.

The problem of crosstalk and how to deal with it is

becoming more important as system performance and board

densities increase. Crosstalk is the capacitive coupling of

signals from one line to another. The amplitude of the noise

generated on the inactive line is directly related to the edge

rates of the signal on the active line, the proximity of the two

lines and the distance that the two lines are adjacent.

Crosstalk has two basic causes. Forward crosstalk,

Figure 16, is caused by the wavefront propagating down the

printed circuit trace at two different velocities. This difference

in velocities is due to the difference in the dielectric constants

of air (

= 1) and epoxy glass (

= 4.7). As the wave

r

propagates down the trace, this difference in velocities will

cause one edge to reach the end before the other. This delay

is the cause of forward crosstalk; it increases with longer trace

length, so consequently the magnitude of forward crosstalk

will increase with distance.

Reverse crosstalk, Figure 17, is caused by the mutual

inductance and capacitance between the lines which is a

MOTOROLA

22

LCX DATA

BR1339 — REV 3

Design Considerations

V

CC

L2

L3

I

R1

CL

RL

L1

Figure 18. Output Model

0.0 V

TIME (ns) (5.0 ns/DIV)

Figure 17. Reverse Crosstalk on PCB Traces

Key

Vertical Scale Horizontal Scale

Active Driver

Forward Crosstalk

Active Receiver

1.0 V/Div

0.2 V/Div

1.0 V/Div

50 ns/Div

5.0 ns/Div

Figure 19. Output Voltage

This figure shows traces taken on a test fixture designed to exaggerate the

amplitude of crosstalk pulses.

Ground Bounce

Ground bounce occurs as a result of the intrinsic

characteristics of the leadframes and bondwires of the

packages used to house CMOS devices. As edge rates and

drivecapabilityincreaseinadvancedlogicfamilies, theeffects

of these intrinsic electrical characteristics become more

pronounced.

Figure 20. Output Current

Figure 18 shows a simple circuit model for a device in a

leadframe driving a standard test load. The inductor L1

represents the parasitic inductance in the ground lead of the

package; inductor L2 represents the parasitic inductance in

the power lead of the package; inductor L3 represents the

parasitic inductance in the output lead of the package; the

resistor R1 represents the output impedance of the device

output, andthecapacitorandresistorC andR representthe

standard test load on the output of the device.

L

Figure 21. Inductor Voltage

LCX DATA

23

MOTOROLA

BR1339 — REV 3

Design Considerations

The three waveforms shown in Figure 19 through

Figure 21 depict how ground bounce is generated. The first

waveform shows the voltage (V) across the load as it is

switched from a logic HIGH to a logic LOW. The output slew

rate is dependent upon the characteristics of the output

Observing either one of the following rules is sufficient to

avoid running into any of the problems associated with ground

bounce:

First, use caution when driving asynchronous

TTL–level inputs from CMOS octal outputs, or

Second, use caution when running control lines (set,

reset, load, clock, chipselect)whichareglitch–sensitive

through the same devices that drive data or address

lines.

transistor, the inductors L1 and L3, and C , the load

L

capacitance. The second waveform shows the current that is

L ^{• dV/dt]. The}

generated as the capacitor discharges [I = C

third waveform shows the voltage that is induced across the

inductance in the ground lead due to the changing currents

When it is not possible to avoid the above conditions, there

are simple precautions available which can minimize ground

bounce noise. These are:

[V = –L • (dI/dt)].

gb

There are many factors which affect the amplitude of the

ground bounce. Included are:

• Locate these outputs as close to the ground pin as possible.

• Number of outputs switching simultaneously: more outputs

• Use the lowest V

possible or separate the power

CC

result in more ground bounce.

supplies.

• Type of output load: capacitive loads generate two to three

times more ground bounce than typical system traces.

Increasing the capacitive load to approximately 60–70 pF

increases ground bounce. Beyond 70 pF, ground bounce

drops off due to the filtering effect of the load. Moving the

load away from the output reduces the ground bounce.

• Use board design practices which reduce any additive

noise sources, such as crosstalk, reflections, etc.

Design Rules

The set of design rules listed below are recommended to

ensure reliable system operation by providing the optimum

power supply connection to the devices. Most designers will

recognize these guidelines as those they have employed with

advanced bipolar logic families.

• Location of the output pin: outputs closer to the ground pin

exhibit less ground bounce than those further away.

• Voltage: lowering V

CC

reduces ground bounce.

• Use multi–layer boards with V

and ground planes, with

CC

• Test fixtures: standard test fixtures generate 30 to 50%

more ground bounce than a typical system since they use

capacitive loads which both increase the AC load and form

LCR tank circuits that oscillate.

the device power pins soldered directly to the planes to

ensure the lowest power line impedances possible.

• Use decoupling capacitors for every device, usually 0. 1 µF

shouldbeadequate. Thesecapacitorsshouldbelocatedas

close to the ground pin as possible.

Ground bounce produces several symptoms:

• Do not use sockets or wirewrap boards whenever possible.

• Altered device states. LCX does not exhibit this symptom.

• Do not connect capacitors from the outputs directly to

• Propagation delay degradation. LCX devices are

characterized not to degrade more than 200ps per

additional output switching.

ground.

Decoupling Requirements

• Undershoot on active outputs. The worst–case undershoot

will be approximately equal to the worst–case quiet output

noise.

Motorola’s LCX family, as with other high–performance,

high–drive logic families, has special decoupling and printed

circuit board layout requirements. Adhering to these

requirements will ensure the maximum advantages are

gained with LCX products.

• Quiet output noise. The LCX worst case quiet output has

been characterized to be typically 800mV. It will be much

less in well designed systems.

0.1″

V

CC

1/16″

0.1″

GLASS–EPOXY

GROUND PLANE

GND

A) 50 Ω V

CC

V

0.1″

CC

IMPEDANCE

1/16” BOARD

B) 100 Ω V

CC

IMPEDANCE

V

GND

1/16″ BOARD

CC

0.04”

V

GND

.032

CC

V

GND

1/16″ BOARD

C) 68 Ω V

IMPEDANCE

CC

EPOXY GLASS

E) 2.0 Ω V

IMPEDANCE

D) 100 Ω V

IMPEDANCE

CC

Figure 22. Power Distribution Impedances

MOTOROLA

24

LCX DATA

BR1339 — REV 3

Design Considerations

Local high frequency decoupling is required to supply

powertothechipwhenitistransitioningfromaLOWtoaHIGH

value. This power is necessary to charge the loadcapacitance

the part. This limits the available voltage swing at the local

node, unless some form of decoupling is used. This drooping

of rails will cause the rise and fall times to become elongated.

Consider the example described in Figure 23 to calculate the

amount of decoupling necessary. This circuit utilizes an

LCX240 driving a 150Ω bus from a point somewhere in the

middle.

or drive a line impedance. Figure 22 displays various V

and

CC

ground layout schemes along with associated impedances.

For most power distribution networks, the typical impedance

is between 100 and 150Ω. This impedance appears in series

with the load impedance and will cause a droop in the V

at

CC

Buffer Output Sees Net 75Ω Load.

75Ω Load Line on I –V Characteristic

DATA BUS

OH OH

Shows Low–to–High Step of Approx. 2.8V

2.9 V

150Ω

V

OUT

0.1V

BUFFER

GROUND

4.0ns

PLANE

1 OF 8

37mA

I

OH

0

Worst–Case Octal Drain = 8 × 37mA = 0.3 Amp.

100 V

Figure 23. Octal Buffer Driving a 150Ω Bus

Being in the middle of the bus, the driver will see two 150Ω

loads in parallel, or an effective impedance of 75Ω. To switch

the line from rail to rail, a drive of 37mA is needed; about

300mA will be required if all eight lines switch at once. This

instantaneous current requirement will generate a voltage

across the impedance of the power lines, causing the actual

In this example, if the V droop is to be kept below 30mV

CC

and the edge rate equals 4 ns, a 0.04µF capacitor is needed.

It is good practice to distribute decoupling capacitors

evenly through the logic, placing one capacitor for every

package.

V

at the chip to droop. This droop limits the voltage swing

CC

available to the driver. The net effect of the voltage droop will

lengthen device rise and fall times and slow system operation.

A local decoupling capacitor is required to act as a low

impedance supply for the driver chip during high current

conditions. It will maintain the voltage within acceptable limits

and keep rise and fall times to a minimum. The necessary

values for decoupling capacitors can be calculated with the

formula given in Figure 24.

Capacitor Types

Decoupling capacitors need to be of the high K ceramic

type with low equivalent series resistance (ESR), consisting

primarily of series inductance and series resistance.

Capacitors using 5ZU dielectric have suitable properties and

make a good choice for decoupling capacitors; they offer

minimum cost and effective performance.

V

CC

BUS

Z

CC

Q = CV

V

CC

I = C∆V/∆t

I = 0.3A

C

B

C = I∆t/∆V

–9

∆t = 4 × 10

BYPASS CAPACITORS

SPECIFY V DROOP = 30mV MAX.

CC

–9

0.30 × 4 × 10

–9

= 40 × 10 = 0.040 µF

C =

0.03

SELECT C ≥ 0.047 µF

B

Place one decoupling capacitor adjacent to each package

driving any transmission line and distribute others evenly

throughout the logic.

Figure 24. Formula for Calculating Decoupling Capacitors

LCX DATA

25

MOTOROLA

BR1339 — REV 3

SEMICONDUCTOR TECHNICAL DATA

Motorola Reliability and Quality Assurance

Reliability

Motorola has a long standing reputation for

manufacturing products of excellent Quality and

Reliability since the introduction of the first car

radio in 1928. This has helped Motorola to become

one of the largest corporations exclusively

devoted to electronics.

• Quality in time and environment

• The probability that our semiconductor devices,

which initially have satisfactory performance,

will continue to perform their intended function

for a given time in usage environments

At Motorola, our Reliability and Quality

Assurance Program is designed to generate

ongoing data for both reliability and quality for the

various product families. Both reliability and quality

monitors are performed on the different major

categories of semiconductor products. These

monitors are designed to test the product’s design

and material as well as to identify and eliminate

potential failure mechanisms to ensure reliable

device performance in a “real world” application.

Thus, the primary purpose of the program is to

identify trends from generated data, so if need be,

corrective action(s) can be taken toward improving

performance. In addition, this reliability and quality

data can be utilized by our customers for failure

rate predictions.

In today’s semiconductor marketplace, two

important elements for the success of a company

are its quality and reliability systems. They are

interrelated, reliability being quality extended over

the expected life of a product. For any

manufacturer to remain in business, its products

must meet or exceed basic quality and reliability

standards and customer needs.

At Motorola, the most stringent and demanding

definitions of quality and reliability are used.

Quality

• Reduction of variability around a target so that

conformance to customer requirements and

expectations can be achieved in a cost–effective

way

It is the explicit purpose of this communication to

inform the customer of our LCX qualification

results. In addition, we have provided a general

definition of our reliability and quality assurance

program.

• The probability that a device (equipment, parts)

will have performance characteristics within

specified limits

• Fitness for use

LCX DATA

241

MOTOROLA

BR1339 — REV 3

Reliability Information

LCX Device Description

Motorola’s LCX family, the first Low–Voltage CMOS family with 5V tolerant inputs and outputs, is

manufactured on the H4C “plus” 75% CMOS (double layer metal) process at MOS 6. The LCX family

emphasizes low power, low switching noise, and fast switching speeds. LCX devices will be assembled in

SOIC, SSOP and TSSOP packages. The H4C “plus” 75% CMOS process in MOS 6 was qualified using the

LCX family’s E76S maskset.

LCX Processing Information

PROCESSING SUMMARY — H4C “plus,” 75% CMOS (Double Layer Metal)

General

Process Type

CMOS on EPI

Effective Channel Length

Process Complexity

Gate Processing

Min. target=0.65µm

Single Poly, Double Metal

Gate Oxide Thickness

Gate Terminal

150Å

Phosphorous Doped Polysilicon (POCL)

Phosphorous & Arsenic

Boron (BF2)

N+ Source Drain Dopant

P+ Source Drain Dopant

Metallization Processing

Metal Composition

AlSiCu w/TiN Barrier (M1)

AlSiCu (M2)

Passivation Processing

Passivation Type

Double Layer, Nitride over PSG Oxide

Electrical Characteristics

Field Threshold Voltage

Punchthrough Voltage

Gate Oxide Breakdown

>12V

>14V

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Reliability Information

LCX Qualification Introduction

LCX Qualification consisted of intrinsic and extrinsic

Temperature Cycling (MIL–STD–833D–1010C)

reliability testing. Intrinsic reliability concerns device

degradation issues and is assessed via electromigration,

hot carrier injection and dielectric breakdown measures.

Extrinsic reliability addresses both processing and

packaging related issues and utilizes several tests: high

temperature bias, temperature cycling, pressure

temperature humidity, thermal shock, temperature

humidity bias, surface mount preconditioning, physical

dimensions, solderability and marking permanency.

(Included below are definitions of the aforementioned

terms.)

Temperature cycle testing accelerates the effects of

thermal expansion mismatch among the different

components within a specific die and packaging system. This

test is typically performed per MIL–STD–883D Method

1010C with the minimum and maximum temperatures being

–65°C and +150°C, respectively. During temperature cycle

testing, devices are inserted into a cycling system and held at

the cold dwell temperature for at least ten minutes. Following

this cold dwell, the devices are heated to the hot dwell where

they remain for another ten minute minimum time period. The

system employs a circulating air environment to assure rapid

stabilization at the specified temperature. The dwell at each

extreme, plus the two transition times of five minutes each

(one up to the hot dwell temperature, another down to the

cold dwell temperature), constitute one cycle.

INTRINSIC RELIABILITY

Thermal Shock (MIL–STD–833D–1010C)

Electromigration

The objective of thermal shock testing is the same as that

for temperature cycle testing, that is, to emphasize

differences in expansion coefficients for components of the

packaging system. However, thermal shock provides

additional stress, in that the device is exposed to a sudden

change in temperature due to a maximum transfer time of ten

seconds, as well as the increased thermal conductivity of a

liquid ambient. This test is typically performed per

MIL–STD–883D Method 1011C with minimum and maximum

temperatures being –65 °C to +150 °C, respectively. Devices

are placed in a bath and cooled to minimum specified

temperature. After being held in the cold chamber for five

minutes minimum, the devices are transferred to an adjacent

chamber at the maximum specified temperature for an

equivalent time. Two five minute dwells plus two ten second

transitions constitute one cycle.

Electromigration is the movement of metal in the direction

of electron flow. This is accelerated by high current densities

and temperatures which result in metal void and/or collection

(hillock) formations, and ultimately shorts. Design rules

specify minimum metal widths and maximum current

densities to circumvent electromigration issues.

Hot Carrier Injection (HCI)

Hot carrier injection is the result of electron scattering and

subsequent trapping in the gate oxide of MOS devices.

Scattering is a function of electron velocity and thus electric

fields and temperature. Ultimately, carrier mobility and

transconductance are reduced causing threshold voltage

shifts. Processing conditions are set to minimize hot carrier

generation rates and gate trapping efficiencies.

Temperature Humidity Bias (THB Motorola Std)

Dielectric Breakdown

This stress is performed to accelerate the effects of

moisture penetration, with the dominant effect being

corrosion. Conditions employed during this test are a

temperature of 85°C, humidity of 85% RH, and a nominal

bias level.

Dielectric breakdown results in the formation of a

conductive path connecting once–isolated conducting layers.

High voltage induced charge injection and trapping

accelerates this breakdown. Dielectric integrity is maximized

via uniform depositional thickness, and dielectric quality is

achieved through minimizing impurity, charge, and defect

levels.

Pressure Temperature Humidity (PTH Motorola Std)

This stress is performed to accelerate the effects of

moisture penetration, with the dominant effect being

corrosion. This test detects similar failure mechanisms as

THB but at a greatly accelerated rate. Conditions employed

during this test are a temperature of 121°C, pressure of

15psig or greater, humidity of 100% RH, unbiased.

EXTRINSIC RELIABILITY

High Temperature Bias (HTB)

High temperature bias (HTB) testing is performed to

accelerate failure mechanisms which are activated through

the application of elevated temperatures and the use of

biased operating conditions. The temperature and voltage

conditions used in the stress are dependent on the product

under stress. However, the typical ambient temperature is

145°C with the static bias applied equal to or greater than the

data sheet nominal value.

Surface Mount Preconditioning (Motorola Std)

Preconditioning tests are performed to simulate the

customer board mount process where surface mount parts

are subjected to a high temperature for a short duration.

These tests detect mold compound delamination from the die

and leadframe which can result in reliability failures. The

dominant failure mechanism is corrosion, but other

LCX DATA

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Reliability Information

stress–related problems could also occur like fractured

wirebonds, passivation cracks, smeared metal on die, etc.

operation. This test is typically performed per MIL–STD–

883D Method 2003. The test verifies the ability of these

terminations to be wetted or coated by solder, and to predict

suitable fillet when dip soldered. An accelerated aging test is

included in this method which simulates a minimum of six

months natural aging under a combination of various storage

conditions that have a deleterious effect on the solderability.

The conditions typically used are 245°C for IR reflow and

260°C for solder immersion. For small pitch packages, a

260°C oil immersion is substituted for the 260°C solder to

avoid solder bridging of the leads.

Physical Dimensions (MIL–STD–883D–2016)

The purpose of this test is to verify the external dimensions

of the device are in accordance with the case outline

specification. This test is typically performed per MIL–STD–

883D Method 2016.

Marking Permanency (Motorola Std)

The purpose of this test is to verify the device markings will

not become illegible when subjected to solvents, and the

solvents will not cause any mechanical, electrical, damage or

deterioration, of the materials or finishes. This test is typically

performed per Motorola standard.

Solderability (MIL–STD–883D–2003)

The purpose of this test is to determine the solderability of

all terminations which are normally joined by a soldering

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Reliability Information

Process Qualification Information

Dielectric Breakdown

PROCESS QUALIFICATION SUMMARY

The current conduction and QBD (charge breakdown)

data taken in MOS 6 was used to calculate an intrinsic gate

oxide lifetime of 1364 years. This estimated lifetime greatly

exceeds the expected lifetime of the device.

The H4C “plus” 75% CMOS (double layer metal)

process qualification consisted of intrinsic reliability

testing (Electromigration, Hot Carrier Injection, and

Dielectric Breakdown) and extrinsic reliability testing

(High Temperature Bias, Temperature Cycling, and

Pressure Temperature Humidity).

EXTRINSIC RELIABILITY RESULTS/DATA

PROCESS QUALIFICATION

The intrinsic reliability measures indicate no significant

degradation over the lifetime of the device. Extrinsic

reliability for the process resulted in zero failures.

The reliability testing consisted of High Temperature Bias

(145°C, 3.6V bias), Temperature Cycling (–65°C to 150°C),

and PTH (121°C, 15PSIG, & 100% RH). Samples from three

wafer lots were tested.

One wafer lot was a metal/dielectric split lot. The metal

and dielectric layers were run at the maximum and minimum

thickness specifications in order to account for step coverage

extremes.

INTRINSIC RELIABILITY RESULTS

DEVICE QUALIFICATION

The second wafer lot was a Vt/Leff split lot. The Vt and

Leff were run at minimum and maximum specifications in

order to account for extremes in leakage, speed, and

translation window.

Electromigration

Electromigration evaluation of MOS 6 metals used in the

H4C ”plus” 75% CMOS (double layer metal) process

revealed an acceptable metallization process for a minimum

lifetime of 10 years at 100°C with < .01% cumulative failures.

The remaining lot was a nominal lot. Zero process related

rejects occurred after 504 hours of op–life, 600 temp cycles,

and 240 hours of PTH. (The device failure in time (FIT) was

calculated based on HTB results at 14.4; stress temp =

145°C; activation energy = 0.7eV).

Hot Carrier Injection

HCI test (low temperature electrical stress) results indicate

less than 10% change in transconductance over the lifetime

of the transistor.

The H4C “plus” 75% CMOS (double layer metal) process

in MOS 6 was qualified and approved in light of the results of

the above intrinsic and extrinsic reliability results.

Package Qualification

MC74LCX family is being offered in SOIC, SSOP and TSSOP packaging. As the TSSOP package is a newer technology, a

qualification summary has been included in this report. All reliability tests have passed successfully, including preconditioning

tests used to simulate customer board mount processes (see below). Furthermore, based on reliability results, drypack* is not

required for this package type.

Package Qualification Summary

TSSOP

leads

Op Life

Temperature

HAST

Surface Mount

Preconditioning

Solderability

Marking

Permanency

Physical

Dimension

Cycle

14

16

20

24

48

56

PASS

PASS*

PASS

* 48 and 56 lead TSSOP packages are moisture class level 2 and require drypack. Moisture class level 1 qualification is in progress – upon

successful completion, the 48–lead and 56–lead packages will no longer require dry pack.

LCX DATA

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Reliability Information

Summary Package Information

• Package Materials

– 14, 16 and 20 Lead

Hitachi CEL 9200N

Shinetsu KMC 184

Sumitomo 7351T

– 24 Lead

– 48, 56 Lead

• Leadframe Material

• Plating

Copper

80/20 tin/lead solder plate

• Die Attach Epoxy

– 14, 16 and 20 Lead

– 24 Lead

– 48, 56 Lead

Sumitomo CRM 1033B

Ablestik 84–1 LMISR4

Ablestik 8361J

• Wire Bond Material

• Wire Bond Method

• 14–/16–Lead Flag Size

• 20–Lead Flag Size

• 24–Lead Flag Size

• 48–Lead Flag Size

• 56–Lead Flag Size

1.0 mil gold

Thermosonic Ball

83 x 93 mils

83 x 120 and 110 x 120 mils

118 x 138 mils

118 x 197 mils

137 x 177 mils

Reliability Audit Program Summary

Reliability tests are run at three sites: Mesa, Arizona

The Motorola Logic Reliability Audit Program (RAP) is

designed to monitor the ability of Logic products to exceed

minimum acceptable reliability standards. Mesa Reliability

Engineering has overall responsibility for RAP, including

updating requirements, interpreting results, offshore

administration, and monthly reporting.

(LICD); Manila, Philippines (MPI); and Taipei, Taiwan

(METL). Following mechanical and electrical testing, devices

receive standard static and functional electrical tests using

conditions and limits per applicable device specifications.

Failures

All failed devices require recorded data. Failure data and

failure verification information accompany all rejects to a

product analysis lab where root cause failure analysis is

performed on all occurrences observed at that site. All

information regarding failed units is logged into a tracking

database.

Testing

RAP is a system of mechanical, environmental, and

electrical tests performed periodically on randomly selected

samples of standard products. Each sample receives

minimum standard tests covering all wafer fab sites,

assembly sites, and packages. Within each family, devices

are chosen to represent the range of die sizes and functional

complexity.

A review is called if any sample has a failure. The findings

are analyzed relative to past performance to determine if

customers are at risk for abnormally high failure rates.

Customer notification may then be required and, if needed, is

prepared and distributed. Following the completion of testing

and data review, the local reliability engineering group enters

all data into the Reliability Audit Program Database.

In addition to standard tests, each package type also

receives special pre–conditioning tests, the frequency of

which is intended to sample every package type and

assembly site once per month.

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Reliability Information

packages generally require less board space than their

through hole counterparts so that designs incorporating SMD

technologies have a higher thermal density. To optimize the

thermal management of a system it is imperative that the

user understand all of the variables which contribute to the

junction temperature of the device.

Thermal Considerations

Prepared by: Lance K. Packer

LCX Application Engineering

Reliability of Plastic Packages

The variables involved in determining the junction

temperature of a device are both supplier and user defined.

The supplier, through lead frame design, mold compounds,

die size and die attach, can positively impact the thermal

resistance and the junction temperature of a device. Motorola

continually experiments with new package designs and

assembly techniques in an attempt to further enhance the

thermal performance of its products.

Although today’s plastic packages are as reliable as

ceramic packages under most environmental conditions, as

the junction temperature increases a failure mode unique to

plastic packages becomes a significant factor in the long

term reliability of the device.

Modern plastic package assembly utilizes gold wire

bonded to aluminum bonding pads throughout the

electronics industry. As the temperature of the silicon

(junction temperature) increases, an intermetallic compound

forms between the gold and aluminum interface. This

intermetallic formation results in a significant increase in the

impedance of the wire bond and can lead to performance

failure of the affected pin. With this relationship between

intermetallic formation and junction temperature established,

it is incumbent on the designer to ensure that the junction

temperature for which a device will operate is consistent with

the long term reliability goals of the system.

It can be argued that the user has the greatest control of

the variables which commonly impact the thermal

performance of a device. Depending on the environment in

which an IC is placed, the user could control over 75% of the

current that flows through the device. Ambient temperature,

air flow and related cooling techniques are the obvious user

controlled variables, however, PCB substrate material, layout

density, size of the air–gap between the board and the

package, amount of exposed copper interconnect, use of

thermally–conductive epoxies and number of boards in a box

and output loading can all have significant impacts on the

thermal performance of a system.

Reliability studies were performed at elevated ambient

temperatures (125°C) from which an Arrhenius Equation

(Eq 1), relating junction temperature to bond failure, was

established. The application of this equation yields the values

in 1. . This table relates the junction temperature of a device

in a plastic package to the continuous operating time before

0.1% bond failure (1 failure per 1000 bonds).

PCB substrates all have different thermal characteristics,

these characteristics should be considered when exploring

the PCB alternatives. The user should also account for the

different power dissipations of the different devices in his

system and space them on the PCB accordingly. In this way,

the heat load is spread across a larger area and “hot spots”

do not appear in the layout. Copper interconnect traces act

as heat radiators, therefore, significant thermal dissipation

can be achieved through the addition of interconnect traces

on the top layer of the board. Finally, the use of thermally

conductive epoxies can accelerate the transfer of heat from

the device to the PCB where it can more easily be passed to

the ambient.

11554.267

( Eq 1 )

–9

T = 6.376 × 10

e

273.15 + T

J

Where:

T = Time to 0.1% bond failure

1. . Tj vs Time to 0.1% Bond Failure

Junction

Temp. (°C)

Time (hours)

Time (yrs.)

The advent of SMD packaging and the industry push

towards smaller, denser designs makes it incumbent on the

designer to provide for the removal of thermal energy from

the system. Users should be aware that they control many of

the variables which impact the junction temperatures and,

thus, to some extent, the long term reliability of their designs.

80

90

1,032,200

419,300

178,700

79,600

37,000

17,800

8,900

117.8

47.9

20.4

9.1

4.2

2.0

100

110

120

130

140

1.0

Calculating Junction Temperature

The following equation can be used to estimate the

junction temperature of a device in a given environment:

Thermal Management

As in any system, proper thermal management is

essential to establish the appropriate trade–off between

performance, density, reliability and cost. In particular, the

designer should be aware of the reliability implication of

continuously operating semiconductor devices at high

junction temperatures.

T = T + P Θ

D JA

J

A

where:

T

= Junction Temperature

= Ambient Temperature

= Power Dissipation

= Avg Pkg Thermal Resistance (Junction Ambient)

J

The increasing popularity of surface mount devices (SMD)

is putting a greater emphasis on the need for better thermal

management of a system. This is due to the fact that SMD

T

A

P

Θ

D

JA

LCX DATA

247

MOTOROLA

BR1339 — REV 3

Reliability Information

1

2

s

[

]

n

P

V

C V

P CC

F

V

I

D

CC

OUT

CC

i

1

3

4

s

h

V

OH

(V

V

)

(V

V

)

C F

CC

OH

OL

L OUT

i

R

D

i

1

i

1

i

5

6

s

l

(V

)

OL

CC

)

(V

)

OL

C F

L OUT

OL

OH

i

R

U

i

1

i

1

i

Power Dissipation Equation

The power dissipation equation is made up of five major

factors controlled by the user which contribute to increased

power dissipation:

s

(V

V

)

C F

L OUT

OH

OL

i

1

1 Frequency of operation (output switching frequency)

2 Input voltage levels

3 Output loading (capacitive and resistive)

V

–V is the voltage swing of the output. C is the output

OH OL L

load (this could vary from output to output). F

frequency which can also vary from output to output.

is theoutput

OUT

4 V

5 Duty cycle

level

CC

The fourth term stems from current through the upper

structure due to an external resistive load to ground.

Each of these five factors are addressed in the estimating

equation except duty cycle. Duty cycle can be addressed by

“weighting” the power dissipation equation terms

appropriately.

As the output frequency increases, the measured current

approaches that of static High outputs.

h

V

OH

The first current term is I

, with the device unloaded. It

is caused by the internal switching of the device. Static I is

CCD

R

D

i

1

i

CC

so small for LCX, that when estimating power dissipation, it is

ignored.

R

is an external pull–down resistor. A different value load

D

could be applied to each output.

s

The fifth current term is determined by the output

capacitive load and the output frequency on the lower

structure of the device. If this load exists than this term is also

significant.

C V

P CC

F

out

i

1

This term represents the I

current with absolutely no

CC

load. This measurement is taken without the output pins

connected to the board. The C for a device is calculated by:

s

P

(V

V

)

OL

C F

L OUT

OH

i

1

I

(@50MHz)

I

(@1MHz)

CC

(49MHz)s

C

P

All variables are the same as with the third term with the

exception that this is current flowing through the lower

V

CC

“s” is the number of outputs switching. C may vary slightly

P

from part to part within a product family.

structure of the IC. This current is not I , but rather current

that is “sinked” from an external source.

CC

The next term is from current due to holding the CMOS

The final term is due to an external load connected to V

This term includes both switching and static Low outputs.

.

CC

inputs at V –0.6V rather than at the rail voltages. This term

CC

becomes insignificant as load and frequency increase.

l

(V

V

)

OL

CC

∆I

CC

n

R

U

i

1

i

∆I

CC

is the through current when holding the input High of a

As with term five, this is current that flows through the lower

structure of the IC. This current too is not I

device to V –0.6V. This value is typically 300µA or less. “n”

CC

.

is the number of inputs held at this level.

CC

The third term is current through the upper structure of the

device. It is caused by the external capacitive load and the

output frequency. If a capacitive load exists then this term can

become very significant.

Example of Thermal Calculations

Junction temperature can be estimated using the following

equation:

MOTOROLA

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LCX DATA

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Reliability Information

T = (Θ × P ) + T

JA A

= 52mA + 0 = 52mA

These terms are not I

J

D

where:

currents, but rather currents

CC

“sinked” by the lower structure of the device. The total current

from all terms is 153.2mA.

T

Θ

P

= Junction Temperature (°C)

= Thermal Resistance (Junction–to–Ambient)

J

JA

D

= Power Dissipation at a T

= Ambient Temperature (°C)

J

2. Finding PD (V x I)

T

A

When calculating the total power dissipation of the device,

the first two terms are multiplied by V , which in this

example is

CC

Example of LCX T Calculation

J

1. Calculate Current Consumption:

3V(15.6mA) = 46.8mW

For example, the LCX244’s C is 25pF. Let V

= 3V;

P

OUT

CC

= 50MHz; for 4 outputs

operating temperature = 85°C; F

The third and fourth terms are multiplied by the voltage

dropacrosstheupperstructureofthedevice, V –V

is approximately 0.2V.

switching; hold 2 inputs LOW and 2 inputs HIGH (at V

–

.This

CC

CC OH

0.6V); C = 100pF; 500Ω pull–down; no pull–up.

L

1

2

0.2V(85.6mA) = 17.1mW

The fifth and sixth terms are multiplied by the voltage drop

4

25pF 3V

50MHz

0.3mA(2)

i

1

across the lower structure of the device, V

.

OL

=15mA + 0.6mA = 15.6mA

These unloaded terms contribute only 10% of the total I

0.2V(52mA) = 10.4mW

CC

The total estimated power dissipation of an LCX 244 with 4

outputs switching, at 85°C, with V =3V, with 2 outputs held

static Low, and 2 inputs at 2.4V with 100pF capacitive loads,

500Ω pull–downs, and 50MHz switching frequency is:

current.

CC

3

4

6

2.8V

500

1

(2.8V 0.2V)

100pF(50MHz)

i

1

i

74.3 mW

= 52mA + 33.6mA = 85.6mA

In this example, terms three and four contribute over 55%

3. Θ

Value

JA

The θ

for a 20–pin TSSOP is approximately 128°C/W.

JA

of the total I

current. This part of I

is entirely due to

CC

external loading.

4. Final Calculations for T for the LCX244

J

T = (P × Θ ) + T = (0.0743W × 128°C/W) + 85°C =

5

6

J

D

JA

A

4

6

94.5°C. LCX runs cool — well below the point for reliability

worries. Using the Arrhenius Equation (Eq 1 on page 247),

the time to 0.1% bond failures is approximately 30 years.

3V 0.2V

(2.8V 0.2V)

100pF(50MHz)

I

1

I

1

LCX DATA

249

MOTOROLA

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Reliability Information

• Metal (copper) traces on PC boards conduct heat away

from the package and dissipate it to the ambient; thus the

larger the trace area the lower the thermal resistance.

System Considerations

The manner in which an IC package is mounted and

positioned in its surrounding environment will have

significant effects on operating junction temperatures.

These conditions are under the control of the system

designer and are worthy of serious consideration in PC

board layout and system ventilation and airflow.

• Package stand–off has a small effect on Θ . Boards with

JA

higher thermal conductivity (ceramic) may show the most

pronounced benefit.

• The use of thermally conductive adhesive under SO

packages can lower thermal resistance by providing a

direct heat flow path from the package to board. Naturally

high thermal conductivity board material and/or cool board

temperatures amplify this effect.

Forced–air cooling will significantly reduce Θ . Air flow

JA

parallel to the long dimension of the package is generally a

few percent more effective than air flow perpendicular to the

long dimension of the package. In actual board layouts, other

components can provide air flow blocking and flow

turbulence, which may reflect the net reduction of Θ

specific component.

• High thermal conductive board material will decrease

thermal resistance. A change in board material from epoxy

laminate to ceramic will help reduce thermal resistance.

of a

JA

Conclusion

Thermal management remains a major concern of

External heat sinks applied to an IC package can improve

thermal resistance by increasing heat flow to the ambient

environment. Heat sink performance will vary by size,

material, design, and system air flow. Heat sinks can provide

a substantial improvement.

producers and users of IC’s. An increase in Θ is the major

JA

trade–off one must accept for package miniaturization. When

the user considers all of the variables that affect the IC

junction temperature, he is then prepared to take maximum

advantage of the tools, materials and data that are available.

Package mounting can affect thermal resistance. Surface

mount packages dissipate significant amounts of heat

through the leads. Improving heat flow from package leads to

ambient will decrease thermal resistance.

References

1. “High Performance ECL Data – ECLinPS and ECLinPS Lite,” Motorola, pp. 4–32.

2. “Thermal Considerations for Advanced Logic Families; AN241,” Philips

Semiconductors

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SEMICONDUCTOR TECHNICAL DATA

Device Nomenclature

MC 74 XXXX YYYYYY ZZ

Motorola

Package Type

Circuit Identifier

• D

= Plastic Narrow JECDEC SOIC

• DW = Plastic Wide JEDEC SOIC

• M = Plastic EIAJ SOIC

• SD = Plastic SSOP

• DT = Plastic TSSOP

Temperature Range

• 74 = –40 to +85°C

Family Identifier

• LCX = 5V–Tolerant Low–Voltage CMOS

• LVX = Low–Voltage CMOS

• LVXC = Configurable Low–Voltage CMOS

Function Type

• A = Modified LCX Spec

LCX DATA

BR1339 — REV 3

251

MOTOROLA

Case Outlines

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

–A–

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

14

1

8

7

P 7 PL

–B–

M

0.25 (0.010)

B

MILLIMETERS

INCHES

MIN MAX

G

F

R X 45°

DIM MIN

MAX

8.75

4.00

1.75

0.49

1.25

C

A

B

C

D

F

G

J

K

M

P

8.55

3.80

1.35

0.35

0.40

0.337 0.344

0.150 0.157

0.054 0.068

0.014 0.019

0.016 0.049

0.050 BSC

J

M

SEATING

PLANE

K

D 14 PL

1.27 BSC

0.19

0.10

0°

0.25

7°

0.008 0.009

0.004 0.009

M

S

0.25 (0.010)

T

B

A

0°

7°

5.80

0.25

6.20

0.50

0.228 0.244

0.010 0.019

R

M SUFFIX

PLASTIC SOIC EIAJ PACKAGE

CASE 965–01

ISSUE O

NOTES:

1

DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2

3

CONTROLLING DIMENSION: MILLIMETER.

DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

L

E

14

8

7

Q

1

E H

4

5

TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

E

M

THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

L

1

DETAIL P

Z

D

VIEW P

e

MILLIMETERS

INCHES

A

DIM MIN

MAX

MIN

---

MAX

0.081

c

A

---

2.05

A

0.05

0.35

0.18

0.20 0.002 0.008

0.50 0.014 0.020

0.27 0.007

1

b

c

0.011

D

E

e

9.90 10.50 0.390 0.413

b

A

1

5.10

5.45 0.201 0.215

M

1.27 BSC

0.050 BSC

8.20 0.291 0.323

0.85 0.020 0.033

1.50 0.043 0.059

0.13 (0.005)

0.10 (0.004)

H

7.40

0.50

1.10

0

0.70

---

E

L

E

M

Q

10

0.90 0.028 0.035

1.42 --- 0.056

0

10

1

Z

MOTOROLA

252

LCX DATA

BR1339 — REV 3

Case Outlines

(continued)

SD SUFFIX

PLASTIC SSOP PACKAGE

CASE 940A–03

NOTES:

ISSUE B

6

DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

14X K REF

7

8

CONTROLLING DIMENSION: MILLIMETER.

DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

M

S

0.12 (0.005)

T U

V

0.25 (0.010)

N

9

DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

14

8

L/2

M

N

10 DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION/INTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN

EXCESS OF K DIMENSION AT MAXIMUM

MATERIAL CONDITION. DAMBAR INTRUSION

SHALL NOT REDUCE DIMENSION K BY MORE

THAN 0.07 (0.002) AT LEAST MATERIAL

CONDITION.

B

L

F

PIN 1

IDENT

1

7

DETAIL E

–U–

11 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

12 DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

A

–V–

K

J

J1

M

S

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

0.20 (0.008)

T U

A

B

C

D

F

6.07

5.20

1.73

0.05

0.63

6.33 0.238 0.249

5.38 0.205 0.212

1.99 0.068 0.078

0.21 0.002 0.008

0.95 0.024 0.037

K1

SECTION N–N

G

H

J

J1

K

K1

L

0.65 BSC

0.026 BSC

1.22 0.042 0.048

0.20 0.003 0.008

0.16 0.003 0.006

0.38 0.010 0.015

0.33 0.010 0.013

1.08

0.09

0.25

7.65

0

–W–

C

0.076 (0.003)

SEATING

PLANE

–T–

7.90 0.301

0.311

8

D

G

M

8

0

DETAIL E

H

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

NOTES:

1

14X K REF

DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

M

S

0.10 (0.004)

T U

V

2

3

CONTROLLING DIMENSION: MILLIMETER.

DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

S

0.15 (0.006) T U

N

0.25 (0.010)

14

4

5

8

7

2X L/2

M

B

L

N

–U–

PIN 1

IDENT.

F

1

6

7

TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

DETAIL E

K

S

0.15 (0.006) T U

A

MILLIMETERS

DIM MIN MAX

INCHES

MIN MAX

K1

–V–

A

B

4.90

4.30

–––

5.10 0.193 0.200

4.50 0.169 0.177

J J1

C

1.20

––– 0.047

D

F

G

H

J

J1

K

K1

L

0.05

0.50

0.65 BSC

0.50

0.09

0.19

0.15 0.002 0.006

0.75 0.020 0.030

SECTION N–N

0.026 BSC

0.60 0.020 0.024

0.20 0.004 0.008

0.16 0.004 0.006

0.30 0.007 0.012

0.25 0.007 0.010

–W–

C

0.10 (0.004)

6.40 BSC

0.252 BSC

SEATING

PLANE

–T–

H

G

M

0

8

0

8

DETAIL E

D

LCX DATA

BR1339 — REV 3

253

MOTOROLA


型号：	MC74LCX05SD
厂家：	ONSEMI
描述：	LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SSOP-14 输入元件光电二极管
文件：	总37页 (文件大小：339K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC74LCX05SD [ONSEMI]

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