MC74HCT74ANG [ONSEMI]
Dual D Flip−Flop with Set and Reset with LSTTL Compatible Inputs; 双D触发器与设置，并与LSTTL兼容输入复位
| 型号： | MC74HCT74ANG |
| 厂家： | 
ONSEMI |
| 描述： | Dual D Flip−Flop with Set and Reset with LSTTL Compatible Inputs |
| 文件： | 总6页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT74A
Dual D Flip−Flop with Set
and Reset with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
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MARKING
DIAGRAMS
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
14
PDIP−14
N SUFFIX
CASE 646
MC74HCT74AN
AWLYYWWG
14
1
1
Features
14
• Output Drive Capability: 10 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 136 FETs or 34 Equivalent Gates
• Pb−Free Packages are Available
SOIC−14
D SUFFIX
CASE 751A
HCT74AG
AWLYWW
14
1
1
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
= Pb−Free Package
G
PIN ASSIGNMENT
LOGIC DIAGRAM
RESET 1
DATA 1
1
2
14
13 RESET 2
12
V
CC
1
RESET 1
3
4
CLOCK 1
SET 1
DATA 2
5
6
2
3
DATA 1
Q1
Q1
11 CLOCK 2
10 SET 2
Q1
Q1
5
6
7
CLOCK 1
9
8
Q2
Q2
4
SET 1
GND
PIN 14 = V
CC
PIN 7 = GND
13
RESET 2
FUNCTION TABLE
9
12
11
Inputs
Outputs
DATA 2
Q2
8
Set Reset Clock Data
Q
Q
CLOCK 2
Q2
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*
H
L
L
H
H*
L
10
SET 2
Design Criteria
Internal Gate Count†
Value
34
Units
ea.
ns
H
L
H
No Change
No Change
No Change
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
1.5
5.0
mW
pJ
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredict-
able if Set and Reset go high simultaneously.
.0075
†Equivalent to a two−input NAND gate.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 10
MC74HCT74A/D
MC74HCT74A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
– 0.5 to V + 0.5
V
out
CC
I
± 20
± 25
± 50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
D
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
CC
V , V
in out
V
V
CC
T
A
– 55
0
+ 125
500
_C
ns
t , t
r
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
2.0
V
v 85_C v 125_C
Symbol
Parameter
Test Conditions
Unit
V
V
Minimum High−Level Input
V
= 0.1 V or V – 0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
IH
out
CC
Voltage
|I | v 20 mA
2.0
out
V
V
V
Maximum Low−Level Input
V
out
= 0.1 V or V – 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
IL
CC
Voltage
|I | v 20 mA
out
V
Minimum High−Level Output
V
in
= V or V
IL
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
OH
IH
Voltage
|I | v 20 mA
out
V
in
= V or V
IH IL
|I | v 4.0 mA
4.5
3.98
3.84
3.7
out
V
V
Maximum Low−Level Output
Voltage
V
= V or V
IL
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
OL
in
IH
|I | v 20 mA
out
V
in
= V or V
IH IL
|I | v 4.0 mA
4.5
5.5
5.5
0.26
± 0.1
2.0
0.33
± 1.0
20
0.4
± 1.0
80
out
I
Maximum Input Leakage Current
V
in
= V or GND
mA
mA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
V
in
= V or GND
CC
CC
I
= 0 mA
out
DI
Additional Quiescent Supply
Current
V
V
l
= 2.4 V, Any One Input
≥−55_C
25_C to 125_C
CC
in
in
= V or GND, Other Inputs
CC
= 0 mA
2.9
2.4
out
5.5
mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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2
MC74HCT74A
AC ELECTRICAL CHARACTERISTICS (V = 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
CC
L
r
f
Guaranteed Limit
– 55 to
25_C
v 85_C
v 125_C
Symbol
Parameter
Unit
f
30
24
24
15
10
24
20
36
36
22
10
MHz
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
max
30
30
19
10
ns
ns
ns
pF
t
t
t
,
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
PLH
t
PHL
,
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
PLH
t
PHL
,
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
TLH
t
THL
C
in
Maximum Input Capacitance
2. For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
32
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
pF
2
3. Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see Chapter 2 of the
D
PD CC
CC CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (V = 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
CC
L
r
f
Guaranteed Limit
– 55 to
25_C
v 85_C
v 125_C
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Fig.
3
Units
ns
t
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
15
3
19
3
22
3
su
t
3
ns
h
t
Minimum Recovery Time, Set or Reset Inactive to Clock
Minimum Pulse Width, Clock
2
6
8
9
ns
rec
t
t
1
15
15
19
19
22
22
ns
w
w
Minimum Pulse Width, Set or Reset
Maximum Input Rise and Fall Times
2
ns
t , t
r
1
500
500
500
ns
f
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT74AN
PDIP−14
25 Units / Rail
55 Units / Rail
MC74HCT74ANG
PDIP−14
(Pb−Free)
MC74HCT74AD
SOIC−14
MC74HCT74ADG
SOIC−14
(Pb−Free)
MC74HCT74ADR2
MC74HCT74ADR2G
SOIC−14
2500 / Tape & Reel
SOIC−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MC74HCT74A
SWITCHING WAVEFORMS
t
w
3 V
t
r
t
f
1.3 V
SET OR
3 V
2.7 V
1.3 V
0.3 V
GND
RESET
CLOCK
t
PHL
GND
Q OR Q
1.3 V
t
w
1/f
max
t
PLH
t
t
PHL
1.3 V
PLH
Q OR Q
CLOCK
90%
1.3 V
10%
t
rec
Q OR Q
3 V
1.3 V
t
t
GND
TLH
THL
Figure 1.
Figure 2.
VALID
TEST POINT
OUTPUT
3 V
1.3 V
t
DATA
GND
DEVICE
UNDER
TEST
t
h
su
C *
L
3 V
1.3 V
GND
CLOCK
*Includes all probe and jig capacitance
Figure 3.
Figure 5.
4, 10
2, 12
SET
5, 9
DATA
Q
3, 11
CLOCK
6, 8
Q
1, 13
RESET
Figure 4. Expanded Logic Diagram
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4
MC74HCT74A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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5
MC74HCT74A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74HCT74A/D
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