MC33074ADR2G
更新时间：2024-09-18 12:15:35
品牌：ONSEMI
描述：Single Supply 3.0 V to 44 V Operational Amplifiers
概述
数据手册
替代型号MC33074ADR2G 概述
Single Supply 3.0 V to 44 V Operational Amplifiers 单电源3.0 V至44 V运算放大器 运算放大器
MC33074ADR2G 数据手册
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PDF下载MC34071,2,4,A
MC33071,2,4,A,
NCV33072,4,A
Single Supply 3.0 V to 44 V
Operational Amplifiers
Quality bipolar fabrication with innovative design concepts are
employed for the MC33071/72/74, MC34071/72/74, NCV33072/74A
series of monolithic operational amplifiers. This series of operational
amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/ms slew rate
and fast settling time without the use of JFET device technology.
Although this series can be operated from split supplies, it is
particularly suited for single supply operation, since the common
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PDIP−8
P SUFFIX
CASE 626
8
1
mode input voltage range includes ground potential (V ). With a
EE
SOIC−8
Darlington input stage, this series exhibits high input resistance, low
input offset voltage and high gain. The all NPN output stage,
characterized by no deadband crossover distortion and large output
voltage swing, provides high capacitance drive capability, excellent
phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33071/72/74, MC34071/72/74, NCV33072/74,A series of
devices are available in standard or prime performance (A Suffix)
grades and are specified over the commercial, industrial/vehicular or
military temperature ranges. The complete series of single, dual and
quad operational amplifiers are available in plastic DIP, SOIC, QFN
and TSSOP surface mount packages.
D SUFFIX
CASE 751
8
1
WQFN10
MT SUFFIX
CASE 510AJ
PDIP−14
P SUFFIX
CASE 646
Features
14
• Wide Bandwidth: 4.5 MHz
• High Slew Rate: 13 V/ms
• Fast Settling Time: 1.1 ms to 0.1%
• Wide Single Supply Operation: 3.0 V to 44 V
1
SOIC−14
D SUFFIX
CASE 751A
14
1
• Wide Input Common Mode Voltage Range: Includes Ground (V
EE)
• Low Input Offset Voltage: 3.0 mV Maximum (A Suffix)
• Large Output Voltage Swing: −14.7 V to +14 V (with 15 V
TSSOP−14
DTB SUFFIX
CASE 948G
Supplies)
14
• Large Capacitance Drive Capability: 0 pF to 10,000 pF
• Low Total Harmonic Distortion: 0.02%
1
• Excellent Phase Margin: 60°
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
• Excellent Gain Margin: 12 dB
• Output Short Circuit Protection
• ESD Diodes/Clamps Provide Input Protection for Dual and Quad
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 20 of this data sheet.
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
August, 2012 − Rev. 18
MC34071/D
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
PIN CONNECTIONS
CASE 646/CASE 751A/CASE 948G
CASE 510AJ
CASE 626/CASE 751
VCC
1
2
3
4
8
7
6
5
1
Offset Null
Inputs
NC
V
Output 1
Inputs 1
14
13
Output 4
Inputs 4
10
-
+
CC
2
3
4
1
9
8
7
6
1
4
3
Output 2
NC
Output 1
NC
-
+
-
+
Output
12
11
2
V
EE
Offset Null
V
CC
V
EE
3
4
In 2
In 1
(Single, Top View)
5
6
10
9
2
+
-
+
-
Inputs 2
Output 2
Inputs 3
Output 3
In + 1
In + 2
1
2
3
4
8
7
6
5
Output 1
Inputs 1
V
CC
5
Output 2
-
7
8
+
VEE/GND
(Top View)
-
+
Inputs 2
(Quad, Top View)
V
EE
(Dual, Top View)
V
CC
Q3
Q8
Q4
Q6
Q5
Q7
Q1
Q17
Q2
R2
R1
C1
D2
Q18
Bias
R6
R7
Q11
Q9
Q10
Output
-
R8
Inputs
+
C2
D3
Q19
Q15
Q16
Q13
Q14
Base
Current
Cancellation
Q12
D1
Current
Limit
R5
R3
R4
V
EE
/GND
Offset Null
(MC33071, MC34071 only)
Figure 1. Representative Schematic Diagram
(Each Amplifier)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage (from V to V
)
V
S
+44
V
V
EE
CC
Input Differential Voltage Range
Input Voltage Range
V
IDR
(Note 1)
(Note 1)
Indefinite
+150
V
IR
V
Output Short Circuit Duration (Note 2)
Operating Junction Temperature
Storage Temperature Range
t
Sec
°C
°C
SC
T
J
T
stg
−60 to +150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both input voltages should not exceed the magnitude of V or V
.
CC
EE
2. Power dissipation must be considered to ensure maximum junction temperature (T ) is not exceeded (see Figure 2).
J
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2
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
ELECTRICAL CHARACTERISTICS (V = +15 V, V = −15 V, R = connected to ground, unless otherwise noted. See Note 3 for
CC
EE
L
T = T
to T
)
A
low
high
A Suffix
Typ
Non−Suffix
Characteristics
Input Offset Voltage (R = 100 W, V
Symbol
Min
Max
Min
Typ
Max
Unit
= 0 V, V = 0 V)
V
IO
mV
S
CM
O
−
−
−
−
−
−
V
CC
V
CC
V
CC
= +15 V, V = −15 V, T = +25°C
0.5
0.5
−
3.0
3.0
5.0
1.0
1.5
−
5.0
5.0
7.0
EE
A
= +5.0 V, V = 0 V, T = +25°C
EE
A
= +15 V, V = −15 V, T = T
to T
high
EE
A
low
Average Temperature Coefficient of Input Offset
Voltage
DV /DT
−
10
−
−
10
−
mV/°C
IO
R
= 10 W, V = 0 V, V = 0 V,
CM O
S
T = T
to T
A
low
high
Input Bias Current (V
= 0 V, V = 0 V)
I
nA
nA
CM
O
IB
T = +25°C
−
−
100
−
500
700
−
−
100
−
500
700
A
T = T
to T
A
low
high
Input Offset Current (V
= 0 V, V = 0V)
I
IO
CM
O
T = +25°C
−
−
6.0
−
50
300
−
−
6.0
−
75
300
A
T = T
to T
A
low
high
Input Common Mode Voltage Range
V
ICR
V
V
EE
V
EE
to (V −1.8)
V
V
to (V −1.8)
T = +25°C
CC
EE
EE
CC
A
to (V −2.2)
to (V −2.2)
T = T
to T
CC
CC
A
low
high
Large Signal Voltage Gain (V
=
10 V, R = 2.0 kW)
A
VOL
V/mV
V
O
L
T = +25°C
50
25
100
−
−
−
25
20
100
−
−
−
A
T = T
to T
A
low
high
Output Voltage Swing (V
=
1.0 V)
V
OH
ID
V
CC
V
CC
V
CC
= +5.0 V, V = 0 V, R = 2.0 kW, T = +25°C
3.7
13.6
13.4
4.0
14
−
−
−
−
3.7
13.6
13.4
4.0
14
−
−
−
−
EE
L
A
= +15 V, V = −15 V, R = 10 kW, T = +25°C
EE
L
A
= +15 V, V = −15 V, R = 2.0 kW,
EE
L
T = T
to T
A
low
high
V
V
V
= +5.0 V, V = 0 V, R = 2.0 kW, T = +25°C
V
OL
0.1
−14.7
−
0.3
−14.3
−13.5
−
−
−
0.1
−14.7
−
0.3
−14.3
−13.5
V
CC
EE
L
A
−
−
−
= +15 V V = −15 V, R = 10 kW, T = +25°C
CC
CC
,
EE
L
A
= +15 V, V = −15 V, R = 2.0 kW,
EE
L
T = T to T
A
low
high
Output Short Circuit Current (V = 1.0 V, V = 0 V,
I
mA
ID
O
SC
T = 25°C)
Source
Sink
A
10
20
30
30
−
−
10
20
30
30
−
−
Common Mode Rejection
CMR
PSR
80
97
−
70
97
−
dB
dB
R
≤ 10 kW, V = V , T = 25°C
CM ICR A
S
Power Supply Rejection (R = 100 W)
80
97
−
70
97
−
S
V /V = +16.5 V/−16.5 V to +13.5 V/−13.5 V,
CC EE
T = 25°C
A
Power Supply Current (Per Amplifier, No Load)
I
D
mA
V
CC
V
CC
V
CC
= +5.0 V, V = 0 V, V = +2.5 V, T = +25°C
−
−
−
1.6
1.9
−
2.0
2.5
2.8
−
−
−
1.6
1.9
−
2.0
2.5
2.8
EE
O
A
= +15 V, V = −15 V, V = 0 V, T = +25°C
EE
O
A
= +15 V, V = −15 V, V = 0 V,
EE
O
T = T
to T
A
low
high
3. T
=
=
=
−40°C for MC33071,2,4,/A, NCV33074
0°C for MC34071,2,4,/A
T
=
=
=
+85°C for MC33071,2,4,/A, NCV33074
+70°C for MC34071,2,4,/A
low
high
−40°C for MC34072,4/V, NCV33072,4A
+125°C for MC34072,4/V, NCV33072,4A
Case 510AJ T /T
guaranteed by product characterization.
low high
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3
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
AC ELECTRICAL CHARACTERISTICS (V = +15 V, V = −15 V, R = connected to ground. T = +25°C, unless otherwise noted.)
CC
EE
L
A
A Suffix
Typ
Non−Suffix
Characteristics
Slew Rate (V = −10 V to +10 V, R = 2.0 kW, C = 500 pF)
Symbol
Min
Max
Min
Typ
Max
Unit
SR
V/ms
in
L
L
A = +1.0
A = −1.0
V
8.0
−
10
13
−
−
8.0
−
10
13
−
−
V
Setting Time (10 V Step, A = −1.0)
t
s
ms
V
To 0.1% (+1/2 LSB of 9−Bits)
To 0.01% (+1/2 LSB of 12−Bits)
−
−
1.1
2.2
−
−
−
−
1.1
2.2
−
−
Gain Bandwidth Product (f = 100 kHz)
Power Bandwidth
GBW
BW
3.5
4.5
−
−
3.5
4.5
−
−
MHz
kHz
−
160
−
160
A = +1.0, R = 2.0 kW, V = 20 V , THD = 5.0%
V
L
O
pp
Phase margin
f
Deg
dB
m
R = 2.0 kW
−
−
60
40
−
−
−
−
60
40
−
−
L
R = 2.0 kW, C = 300 pF
L
L
Gain Margin
A
m
R = 2.0 kW
R = 2.0 kW, C = 300 pF
L
−
−
12
4.0
−
−
−
−
12
4.0
−
−
L
L
Equivalent Input Noise Voltage
= 100 W, f = 1.0 kHz
e
i
−
−
−
−
−
32
−
−
−
−
−
−
−
−
−
−
32
−
−
−
−
−
nV/√Hz
n
R
S
Equivalent Input Noise Current
f = 1.0 kHz
0.22
150
2.5
0.22
150
2.5
pA/√Hz
MW
n
Differential Input Resistance
R
C
in
in
V
CM
= 0 V
Differential Input Capacitance
= 0 V
pF
V
CM
Total Harmonic Distortion
THD
0.02
0.02
%
A = +10, R = 2.0 kW, 2.0 V ≤ V ≤ 20 V , f = 10 kHz
V
L
pp
O
pp
Channel Separation (f = 10 kHz)
−
−
−
120
30
−
−
−
−
120
30
−
−
dB
W
Open Loop Output Impedance (f = 1.0 MHz)
|Z |
O
Single Supply
Split Supplies
3.0 V to 44 V
V
CC
+|V |≤44 V
EE
V
CC
V
CC
V
CC
7
2
3
-
+
1
2
V
CC
1
6
5
1
2
4
3
4
3
4
10 k
V
EE
V
EE
Offset nulling range is approximately 80 mV with a 10 k
potentiometer (MC33071, MC34071 only).
V
EE
V
EE
Figure 2. Power Supply Configurations
Figure 3. Offset Null Circuit
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4
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
2400
2000
1600
1200
800
400
0
V
CC
V
EE
V
CM
= +15 V
= -15 V
= 0
4.0
2.0
8 & 14 Pin Plastic Pkg
SOIC-14 Pkg
0
-2.0
-4.0
SOIC-8 Pkg
-55 -40 -20
0
20 40 60 80 100 120 140 160
-55
-25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 4. Maximum Power Dissipation versus
Temperature for Package Types
Figure 5. Input Offset Voltage versus
Temperature for Representative Units
1.3
V
CC
V
CC
V
EE
V
CM
= +15 V
= -15 V
= 0
V
CC
V /V = +1.5 V/ -1.5 V to +22 V/ -22 V
CC EE
1.2
1.1
1.0
0.9
V
V
V
-0.8
-1.6
-2.4
CC
CC
CC
V
EE
+0.01
0.8
0.7
V
EE
V
EE
-55
-25
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 6. Input Common Mode Voltage
Range versus Temperature
Figure 7. Normalized Input Bias Current
versus Temperature
50
40
30
20
10
0
1.4
1.2
R Connected
L
V
V
= +15 V
= -15 V
CC
to Ground T = 25°C
A
EE
T = 25°C
A
R = 10 k
R = 2.0 k
L
L
1.0
0.8
0.6
-12
-8.0
-4.0
0
4.0
8.0
12
0
5.0
10
15
20
25
V , INPUT COMMON MODE VOLTAGE (V)
IC
V , |V |, SUPPLY VOLTAGE (V)
CC EE
Figure 8. Normalized Input Bias Current versus
Input Common Mode Voltage
Figure 9. Split Supply Output Voltage
Swing versus Supply Voltage
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MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
V
CC
V
CC
V
V /V = +4.5 V/ -4.5 V to +22 V/ -22 V
CC EE
CC
Source
V
V
-1.0
-2.0
CC
V
V
-2.0
-4.0
CC
−40
25
125
V
= +15 V
CC
R = GND
T = 25°C
A
L
CC
CC
V
EE
V
EE
+2.0
+1.0
0.2
0.1
0
Sink
25
85
GND
125
V
EE
0
5.0
10
LOAD CURRENT ( mA)
15
20
100
1.0 k
10 k
100 k
I
L,
R , LOAD RESISTANCE TO GROUND (W)
L
Figure 10. Split Supply Output Saturation
versus Load Current
Figure 11. Single Supply Output Saturation
versus Load Resistance to Ground
0
60
50
40
30
20
V
CC
-0.4
-0.8
Sink
Source
2.0
1.0
V
= +15 V
CC
R to V
T = 25°C
A
L
CC
V
V
= +15 V
= -15 V
CC
EE
10
0
R ≤ 0.1 W
L
GND
DV = 1.0 V
in
100
1.0 k
10 k
100 k
-55
-25
0
25
50
75
100
125
R , LOAD RESISTANCE TO V (W)
T , AMBIENT TEMPERATURE (°C)
A
L
CC
Figure 12. Single Supply Output Saturation
versus Load Resistance to VCC
Figure 13. Output Short Circuit Current
versus Temperature
50
40
30
20
28
24
V
V
V
= +15 V
= -15 V
= 0
CC
EE
CM
V
V
= +15 V
= -15 V
CC
EE
A = +1.0
V
V = 0
O
20
16
12
R = 2.0 k
L
DI
=
0.5 mA
O
THD ≤ 1.0%
T = 25°C
A
T = 25°C
A
A = 1000
V
A = 100
V
A = 10
V
A = 1.0
V
8.0
4.0
10
0
0
1.0 k
10 k
100
f, FREQUENCY (Hz)
1.0 M
10 M
3.0 k
10 k
30 k
100 k
300 k
1.0 M 3.0 M
f, FREQUENCY (Hz)
Figure 14. Output Impedance
versus Frequency
Figure 15. Output Voltage Swing
versus Frequency
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6
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
4.0
0.4
0.3
V
V
= +15 V
= -15 V
CC
A = 1000
V
EE
R = 2.0 k
T = 25°C
A
3.0
2.0
1.0
0
L
A = 1000
V
V
V
= +15 V
= -15 V
CC
EE
V = 2.0 V
O
pp
0.2
0.1
0
R = 2.0 k
T = 25°C
A
L
A = 100
V
A = 100
V
A = 10
V
A = 10
V
A = 1.0
V
A = 1.0
V
10
100
1.0 k
10 k
100 k
0
4.0
8.0
12
16
20
f, FREQUENCY (Hz)
V , OUTPUT VOLTAGE SWING (V )
O
pp
Figure 16. Total Harmonic Distortion
versus Frequency
Figure 17. Total Harmonic Distortion
versus Output Voltage Swing
100
116
112
108
104
100
96
0
V
V
= +15 V
= -15 V
CC
80
60
40
20
0
Gain
EE
45
90
135
Phase
V = -10 V to +10 V
O
R = 10 k
f ≤ 10Hz
L
Phase
Margin
= 60°
V
V
= +15 V
= -15 V
CC
EE
V = 0 V
O
R = 2.0 k
T = 25°C
A
L
180
-55
-25
0
25
50
75
100
125
1.0
10
100 1.0 k
10 k 100 k 1.0 M 10 M 100 M
T , AMBIENT TEMPERATURE (°C)
A
f, FREQUENCY (Hz)
Figure 18. Open Loop Voltage Gain
versus Temperature
Figure 19. Open Loop Voltage Gain and
Phase versus Frequency
20
10
1.15
1.1
1
100
120
140
160
180
Phase
Margin = 60°
V
V
= +15 V
= -15 V
CC
EE
Gain
Margin = 12 dB
R = 2.0 k
L
0
1.05
-10
-20
-30
-40
1.0
1. Phase R = 2.0 k
2. Phase R = 2.0 k, C = 300 pF
3. Gain R = 2.0 k
4. Gain R = 2.0 k, C = 300 pF
L
L
L
3
0.95
L
L
L
4
V
V
= +15 V
= 15 V
CC
0.9
2
EE
V = 0 VꢁꢁꢁꢁꢁT = 25°C
O
A
0.85
1.0
2.0
3.0 5.0
7.0 10
20
30
-55
-25
0
25
50
75
100
125
f, FREQUENCY (MHz)
T , AMBIENT TEMPERATURE (°C)
A
Figure 20. Open Loop Voltage Gain and
Phase versus Frequency
Figure 21. Normalized Gain Bandwidth
Product versus Temperature
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MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
70
60
100
80
V
V
= +15 V
= -15 V
V
V
= +15 V
= -15 V
CC
EE
CC
EE
R = 2.0 k
A = +1.0
V
L
50
40
30
20
10
0
V = -10 V to +10 V
T = 25°C
A
R = 2.0 k to R
O
T = 25°C
A
O
L
V = -10 V to +10 V
60
40
20
0
10
100
1.0 k
10 k
10
100
1.0 k
10 k
C , LOAD CAPACITANCE (pF)
L
C , LOAD CAPACITANCE (pF)
L
Figure 22. Percent Overshoot versus
Load Capacitance
Figure 23. Phase Margin versus
Load Capacitance
14
12
80
V
V
= +15 V
= -15 V
CC
C = 10 pF
L
EE
C = 100 pF
A = +1.0
L
60
40
20
0
V
10
8.0
6.0
4.0
2.0
0
R = 2.0 k to ∞
L
V = -10 V to +10 V
O
V
V
= +15 V
= -15 V
T = 25°C
A
CC
EE
A = +1.0
V
R = 2.0 k to ∞
L
V = -10 V to +10 V
C = 1,000 pF
L
O
C = 10,000 pF
L
10
100
1.0 k
10 k
-55
-25
0
25
50
75
100
125
C , LOAD CAPACITANCE (pF)
L
T , AMBIENT TEMPERATURE (°C)
A
Figure 24. Gain Margin versus Load Capacitance
Figure 25. Phase Margin versus Temperature
70
60
50
40
30
20
10
16
12
8.0
4.0
0
12
V
= +15 V
= -15 V
CC
10
8.0
6.0
4.0
2.0
0
Gain
C = 10 pF
L
V
EE
R
A = +1.0
1
V
V
O
-
+
R = 2.0 k to ∞
L
V = -10 V to +10 V
O
C = 100 pF
L
R
2
V
V
= +15 V
= -15 V
R = R + R
A = +100
V = 0 V
CC
EE
C = 10,000 pF
L
T
1
2
C = 1,000 pF
L
Phase
V
O
T = 25°C
A
0
-55
-25
0
25
50
75
100
125
1.0
10
100
1.0 k
10 k
100 k
T , AMBIENT TEMPERATURE (°C)
A
R , DIFFERENTIAL SOURCE RESISTANCE (W)
T
Figure 26. Gain Margin versus Temperature
Figure 27. Phase Margin and Gain Margin
versus Differential Source Resistance
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8
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
10
1.15
1.1
V
CC
V
EE
= +15 V
= -15 V
V
V
= +15 V
= -15 V
CC
EE
1.0 mV
10 mV
1.0 mV
A = +1.0
V
A = -1.0
5.0
0
V
R = 2.0 k
L
T = 25°C
A
1.05
1.0
C = 500 pF
L
Compensated
Uncompensated
0.95
1.0 mV
-5.0
10 mV
0.9
1.0 mV
0.85
-10
-55
-25
0
25
50
75
100
125
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
T , AMBIENT TEMPERATURE (°C)
A
t , SETTLING TIME (ms)
s
Figure 28. Normalized Slew Rate
versus Temperature
Figure 29. Output Settling Time
V
CC
V
EE
= +15 V
= -15 V
A = +1.0
V
R = 2.0 k
L
C = 300 pF
L
T = 25°C
A
0
0
V
CC
V
EE
= +15 V
= -15 V
A = +1.0
V
R = 2.0 k
L
C = 300 pF
L
T = 25°C
A
2.0 ms/DIV
1.0 ms/DIV
Figure 30. Small Signal Transient Response
Figure 31. Large Signal Transient Response
100
80
100
80
T = 125°C
A
V
V
= +15 V
= -15 V
V
CC
V
EE
V
CM
= +15 V
= -15 V
= 0 V
CC
EE
T = 25°C
A
T = 25°C
A
DV
=
1.5 V
DV
DV
T = -55°C
CC
CM
A
(DV = +1.5 V)
-
DM
+
CC
60
40
20
0
60
A
DV
O
EE
+PSR
-
A
+
40
20
0
DV /A
O
DM
DM
DV
CM
DV
O
+PSR = 20 Log
DV
CC
DV
CM
DV /A
O
DM
-PSR
(DV = +1.5 V)
CMR = 20 Log
x A
DM
-PSR = 20 Log
1.0
DV
O
DV
EE
EE
0.1
1.0
10
100
1.0 k 10 k 100 k 1.0 M 10 M
0.1
10
100
1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 32. Common Mode Rejection
versus Frequency
Figure 33. Power Supply Rejection
versus Frequency
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9
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
105
9.0
8.0
7.0
-PSR (DV = +1.5 V)
EE
V
CC
V
EE
= +15 V
= -15 V
T = -55°C
A
95
85
75
65
(DV = +1.5 V)
+PSR
CC
T = 25°C
A
DV
CC
6.0
DV /A
O
DM
T = 125°C
A
-
A
+
+PSR = 20 Log
-PSR = 20 Log
DV
CC
DM
DV
O
5.0
4.0
DV /A
O
DM
DV
EE
DV
EE
Quad device
0
5.0
10
15
20
25
-55
-25
0
25
50
75
100
125
V , |V |, SUPPLY VOLTAGE (V)
CC EE
T , AMBIENT TEMPERATURE (°C)
A
Figure 34. Supply Current versus
Supply Voltage
Figure 35. Power Supply Rejection
versus Temperature
2.8
120
100
80
60
40
20
0
70
V
V
V
= +15 V
= -15 V
= 0
CC
EE
CM
60
50
40
30
20
10
0
2.4
2.0
1.6
1.2
0.8
0.4
V
V
= +15 V
= -15 V
CC
EE
T = 25°C
A
T = 25°C
A
Voltage
Current
0
10
20
30
50
70
100
200
300
10
100
1.0 k
f, FREQUENCY (kHz)
10 k
100 k
f, FREQUENCY (kHz)
Figure 36. Channel Separation versus Frequency
Figure 37. Input Noise versus Frequency
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
up to approximately 5.0 mA of current from V through
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
If one or both inputs exceed the upper common mode
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
EE
Since the input common mode voltage range of this input
stage includes the V potential, single supply operation is
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
The input stage also allows differential input voltages up
to 44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
Since the input capacitance associated with the small
geometry input device is substantially lower (2.5 pF) than
the typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling D−to−A current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
EE
between V and V supply voltages as shown by the
EE
CC
maximum rating table. In practice, although not
recommended, the input voltages can exceed the V
CC
voltage by approximately 3.0 V and decrease below the V
EE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
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10
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
values of feedback resistances (lower current DACs). This
Because the PNP output emitter−follower transistor has
been eliminated, the MC34071 series offers a 20 mA
minimum current sink capability, typically to an output
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 2.0 kW of feedback
resistance, the MC34071 series can settle to within 1/2 LSB
of 8−bits in 1.0 ms, and within 1/2 LSB of 12−bits in 2.2 ms
for a 10 V step. In a inverting unity gain fast settling
configuration, the symmetrical slew rate is 13 V/ms. In the
classic noninverting unity gain configuration, the output
positive slew rate is +10 V/ms, and the corresponding
negative slew rate will exceed the positive slew rate as a
function of the fall time of the input waveform.
Since the bipolar input device matching characteristics
are superior to that of JFETs, a low untrimmed maximum
offset voltage of 3.0 mV prime and 5.0 mV downgrade can
be economically offered with high frequency performance
characteristics. This combination is ideal for low cost
precision, high speed quad op amp applications.
voltage of (V +1.8 V). In single supply applications the
EE
output can directly source or sink base current from a
common emitter NPN transistor for fast high current
switching applications.
In addition, the all NPN transistor output stage is
inherently fast, contributing to the bipolar amplifier’s high
gain bandwidth product and fast settling capability. The
associated high frequency low output impedance (30 W typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
10,000 pF without oscillation in the unity closed loop gain
configuration. The 60° phase margin and 12 dB gain margin
as well as the general gain and phase characteristics are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The
high frequency characteristics of the MC34071 series also
allow excellent high frequency active filter capability,
especially for low voltage single supply applications.
Although the single supply specifications is defined at
5.0 V, these amplifiers are functional to 3.0 V @ 25°C
although slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 kW load resistance can swing within 1.0 V of the
positive rail (V ), and within 0.3 V of the negative rail
CC
(V ), providing a 28.7 V swing from 15 V supplies.
EE
pp
This large output swing becomes most noticeable at lower
supply voltages.
The positive swing is limited by the saturation voltage of
If power to this integrated circuit is applied in reverse
polarity or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
the current source transistor Q , and V of the NPN pull up
7
BE
transistor Q , and the voltage drop associated with the short
17
Special static precautions are not necessary for these
bipolar amplifiers since there are no MOS transistors on the
die.
circuit resistance, R . The negative swing is limited by the
7
saturation voltage of the pull−down transistor Q , the
16
voltage drop I R , and the voltage drop associated with
L
6
As with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input−output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
resistance R , where I is the sink load current. For small
valued sink currents, the above voltage drops are negligible,
allowing the negative swing voltage to approach within
7
L
millivolts of V . For large valued sink currents (>5.0 mA),
EE
diode D3 clamps the voltage across R , thus limiting the
6
negative swing to the saturation voltage of Q , plus the
16
forward diode drop of D3 (≈V +1.0 V). Thus for a given
EE
supply voltage, unprecedented peak−to−peak output voltage
swing is possible as indicated by the output swing
specifications.
If the load resistance is referenced to V instead of
CC
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to V during the positive swing and the output
CC
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However, under
such conditions, it is important not to allow the device to
exceed the maximum junction temperature rating. Typically
for 15 V supplies, any one output can be shorted
continuously to ground without exceeding the maximum
temperature rating.
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull up
capability.
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11
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
(Typical Single Supply Applications VCC = 5.0 V)
V
CC
5.1 M
V
O
3.7 V
pp
0
0
+
3.7 V
pp
V
CC
100 k
1.0 M
20 k
C
in
C
+
O
V
O
68 k
MC34071
36.6 mV
C
in
-
pp
MC34071
-
10 k
V
O
100 k
C
O
V
in
10 k
10 k
R
100 k
R
L
L
V 370 mV
in
pp
1.0 k
A = 101
V
BW (-3.0 dB) = 45 kHz
A = 10 BW (-3.0 dB) = 450 kHz
V
Figure 38. AC Coupled Noninverting Amplifier
Figure 39. AC Coupled Inverting Amplifier
V
O
V
CC
4.75 V
pp
2.63 V
91 k
5.1 k
R
L
5.1 k
100 k
2.5 V
+
MC34071
V
O
0
0 to 10,000 pF
Cable
-
+
MC34071
V
in
MC54/74XX
1.0 M
A = 10
-
TTL Gate
V
V
in
BW (-3.0 dB) = 450 kHz
Figure 40. DC Coupled Inverting Amplifier
Maximum Output Swing
Figure 41. Unity Gain Buffer TTL Driver
C
R3
0.047
2.2 k
R1
-
MC34071
V
in
1.1 k
V
O
C
0.047
+
R2
5.6 k
V
CC
f = 30 kHz
o
V
≥ 0.2 Vdc
in
V
O
H = 10
H = 1.0
o
-
MC34071
o
0.4 V
R2 =
CC
R
R
+
Given f = Center Frequency
V
in
o
16 k
16 k
A = Gain at Center Frequency
O
C
0.01
Choose Value f , Q, A , C
o
o
Then:
Q
R3
R1 = ꢁ
2H
R1 R3
2
R3 =
ꢁ
f = 1.0 kHz
pf C
o
4Q R1-R3
o
o
2.0 R
32 k
Q f
o o
1
< 0.1
f =
o
For less than 10% error from operational amplifier
GBW
4pRC
where f and GBW are expressed in Hz.
2.0 C
0.02
2.0 C
0.02
o
GBW = 4.5 MHz Typ.
Figure 43. Active Bandpass Filter
Figure 42. Active High−Q Notch Filter
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12
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
V
in
C
F
2.0 V
R
F
V
in
+
MC34071
-
V
O
t
5.0 k
5.0 k
5.0 k
-
V
O
2.0 k
MC34071
V
O
R
+
L
10 k
10 k
10 k
V
CC
0.2 ms
Delay
1.0 V
4.0 V
0.1
Bit
Switches
13 V/ms
25 V/ms
(R-2R) Ladder Network
t
Delay
Settling Time
1.0 ms
1.0 ms (8-Bits, 1/2 LSB)
Figure 44. Low Voltage Fast D/A Converter
Figure 45. High Speed Low Voltage Comparator
V
CC
“ON"
V < V
in
ref
V
CC
V
CC
+
MC34071
V
in
R
L
-
+
MC34071
+
MC34071
V
ref
-
-
“ON"
R
L
V > V
in
ref
(A) PNP
(B) NPN
Figure 46. LED Driver
Figure 47. Transistor Driver
I
Load
R
F
+
MC34071
V
O
-
Ground Current
Sense Resistor
-
MC34071
R
S
I
Cell
V
O
R1
+
R1
R2
R2
V
O
= I
R
1+
Load S
For V > 0.1V
O
V
Cell
= 0 V
R2
R1+R2
V
O
= I
R
Cell F
BW ( -3.0 dB) = GBW
V > 0.1 V
O
Figure 48. AC/DC Ground Current Monitor
Figure 49. Photovoltaic Cell Amplifier
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13
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
V
O
Hysteresis
R2
V
V
V
OH
ref
R1
I
out
+
MC34071
OL
V
in
-
V
in
+
MC34071
V
in
V
inL
V
inH
R1
V
ref
-
V
=
=
(V -V )+V
OL ref
inL
ref
R1+R2
R1
V
inH
(V -V )+V
OH ref
ref
R1+R2
R
V
V
R1
in IO
V =
H
(V -V
)
OL
I
=
OH
out
R1+R
R
Figure 50. Low Input Voltage Comparator
with Hysteresis
Figure 51. High Compliance Voltage to
Sink Current Converter
R1
R2
+V
R4
ref
R
F
-
MC34072
R3
1/2
R
R
-
MC34072
V
O
1/2
+
+V1
-
MC34071
V
O
+
+V2
R
+
R = DR
R2
R1
R4
R3
=
(Critical to CMRR)
DR R
F
R4
R3
R4
V
O
= V
ref
V = 1
O
+
V2-V1
2
2R
R
F
R3
DR < < R
R > > R
For (V2 ≥ V1), V > 0
(V ≥ 0.1 V)
F
O
Figure 52. High Input Impedance
Differential Amplifier
Figure 53. Bridge Current Amplifier
0.85
f
^
OSC
+
I
B
RC
+
SC
V
I
V
t
P
0
-
t
V
in
Base Charge
Removal
+
V
+
= V (pk)
in
O
MC34071
-
I
out
R
-
MC34072
+
1/2
MC34072
1/2
R
V
P
10,000 pF
C
L
+
-
I
B
V+
100 k
Pulse Width
Control Group
100 k
V
P
V
in
47 k
V
P
OSC
Comparator
High Current
Output
t
Figure 54. Low Voltage Peak Detector
Figure 55. High Frequency Pulse
Width Modulation
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MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = 15.0 V
R1
46.1 k
C2
0.02
C2
0.05
C1
1.0
-
R2
5.6 k
R1
560
R3
510
MC34071
C1
1.0
f = 100 Hz
o
R2
1.1 k
-
+
H = 20
o
MC34071
C1
0.44
f = 1.0 kHz
H = 10
o
o
+
H +0.5
o
Then: R1 =
R2 =
Choose: f , H , C1
o
o
Ǹ
pf C1
o
2
Choose: f , H , C2
o
o
Ǹ
2
Then: C1 = 2C2 (H +1)
o
2pf C1 (1/H +2)
o
o
Ǹ
2
R2
R2
C
R2 =
C2 =
R3 =
R1 =
4pf C2
o
H +1
o
H
H
o
o
Figure 56. Second Order Low−Pass Active Filter
Figure 57. Second Order High−Pass Active Filter
C *
F
V = 10 V
O
Step
R
F
2.0 k
+
-
MC34071
V
O
R1
MC34071
V
O
-
R
L
+
I
V
in
R2
t = 1.0 ms
s
Uncompensated
to 1/2 LSB (8-Bits)
t = 2.2 ms
s
V
High Speed
DAC
R2
R1
O
R1
R1 +R2
Compensated
=
BW (-3.0 dB) = GBW
to 1/2 LSB (12-Bits)
V
in
SR = 13 V/ms
*Optional Compensation
SR = 13 V/ms
Figure 58. Fast Settling Inverter
Figure 59. Basic Inverting Amplifier
+
MC34071
V
O
-
V
in
+
V
in
R2
MC34071
V
O
R
L
-
R1
V
V
O
R2
R1
=
1 +
in
BW = 200 kHz
p
R1
V = 20 V
O
pp
BW (-3.0 dB) = GBW
SR = 10 V/ms
R1 +R2
Figure 60. Basic Noninverting Amplifier
Figure 61. Unity Gain Buffer (AV = +1.0)
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15
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
+
R
R
MC34074
-
R
R
-
MC34074
V
O
R
E
+
-
R
Example:
Let: R = R = 12 k
MC34074
E
R
Then: A = 3.0
BW = 1.5 MHz
A = 1 +ꢀ2
V
V
+
R
E
R
Figure 62. High Impedance Differential Amplifier
+V
O
+
+
+
MC34074
R
100 k
L
-
10
10
+10
-
MC34074
220 pF
+
100 k
100 k
-10
+
+
R
L
+
10
MC34074
R
+V
-V
O
L
O
10
-
18.93 -18.78
∞
10 k
18
-18
-V
O
5.0 k
15.4
-15.4
Figure 63. Dual Voltage Doubler
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16
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
ORDERING INFORMATION
Op Amp
Operating
Temperature Range
†
Shipping
Function
Device
Package
MC34071PG
MC34071APG
MC34071DG
PDIP−8
(Pb−Free)
50 Units / Rail
50 Units / Rail
PDIP−8
(Pb−Free)
SOIC−8
(Pb−Free)
98 Units / Rail
T = 0° to +70°C
A
MC34071DR2G
MC34071ADG
MC34071ADR2G
MC33071PG
SOIC−8
(Pb−Free)
2500 / Tape & Reel
98 Units / Rail
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
2500 / Tape & Reel
50 Units / Rail
Single
PDIP−8
(Pb−Free)
MC33071APG
MC33071DG
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−8
(Pb−Free)
98 Units / Rail
T = −40° to +85°C
A
MC33071DR2G
MC33071ADG
MC33071ADR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
98 Units / Rail
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
2500 / Tape & Reel
http://onsemi.com
17
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
ORDERING INFORMATION (continued)
Op Amp
Function
Operating
Temperature Range
†
Shipping
Device
Package
MC34072PG
MC34072APG
MC34072DG
MC34072ADG
PDIP−8
(Pb−Free)
50 Units / Rail
98 Units / Rail
PDIP−8
(Pb−Free)
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
T = 0° to +70°C
A
MC34072DR2G
MC34072ADR2G
MC34072AMTTBG
MC33072PG
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
3000 Units / Tape & Reel
SOIC−8
(Pb−Free)
WQFN10
(Pb−Free)
PDIP−8
(Pb−Free)
50 Units / Rail
98 Units / Rail
MC33072APG
MC33072DG
PDIP−8
(Pb−Free)
Dual
SOIC−8
(Pb−Free)
T = −40° to +85°C
A
MC33072ADG
MC33072DR2G
MC33072ADR2G
MC34072VDG
MC34072VDR2G
MC34072VPG
NCV33072DR2G*
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
2500 / Tape & Reel
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
98 Units / Rail
SOIC−8
(Pb−Free)
2500 / Tape & Reel
T = −40° to +125°C
A
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−8
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix for automotive and other applications requiring unique site and control change requirements; AEC−Q100 qualified and PPAP
capable.
http://onsemi.com
18
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
ORDERING INFORMATION (continued)
Op Amp
Function
Operating
Temperature Range
†
Shipping
Device
Package
MC34074PG
MC34074APG
MC34074DG
MC34074ADG
PDIP−14
(Pb−Free)
25 Units / Rail
55 Units / Rail
PDIP−14
(Pb−Free)
SOIC−14
(Pb−Free)
T = 0° to +70°C
A
SOIC−14
(Pb−Free)
MC34074ADR2G
MC34074DR2G
MC33074PG
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
25 Units / Rail
SOIC−14
(Pb−Free)
PDIP−14
(Pb−Free)
MC33074APG
PDIP−14
(Pb−Free)
MC33074DG
SOIC−14
(Pb−Free)
55 Units / Rail
MC33074ADG
SOIC−14
(Pb−Free)
MC33074DR2G
MC33074ADR2G
MC33074DTBG
MC33074DTBR2G
MC33074ADTBG
MC33074ADTBR2G
NCV33074DR2G*
MC34074VDG
SOIC−14
(Pb−Free)
Quad
2500 / Tape & Reel
SOIC−14
(Pb−Free)
T = −40° to +85°C
A
TSSOP−14
(Pb−Free)
96 Units / Rail
2500 / Tape & Reel
96 Units / Rail
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
55 Units / Rail
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
MC34074VDR2G
MC34074VPG
SOIC−14
(Pb−Free)
2500 / Tape & Reel
25 Units / Rail
T = −40° to +125°C
A
PDIP−14
(Pb−Free)
NCV33074ADTBR2G*
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix for automotive and other applications requiring unique site and control change requirements; AEC−Q100 qualified and PPAP
capable.
http://onsemi.com
19
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
MARKING DIAGRAMS
PDIP−8
P SUFFIX
CASE 626
8
1
8
1
8
1
8
1
8
1
MC3x071P
AWL
MC3x071AP
AWL
MC3x072P
AWL
MC3x072AP
AWL
MC34072VP
AWL
YYWWG
YYWWG
YYWWG
YYWWG
YYWWG
SOIC−8
D SUFFIX
CASE 751
8
8
8
8
8
3x071
ALYWA
ꢀ
3x072
ALYW
ꢀ
34072
ALYWV
ꢀ
3x071
ALYW
ꢀ
3x072
ALYWA
ꢀ
1
1
1
1
1
PDIP−14
P SUFFIX
CASE 646
14
14
14
MC3x074P
AWLYYWWG
MC3x074AP
AWLYYWWG
MC34074VP
AWLYYWWG
1
1
1
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DTB SUFFIX
CASE 948G
14
14
14
14
14
14
MC3x074DG
AWLYWW
MC3x074ADG
AWLYWW
MC34074VDG
AWLYWW
MC33
074
ALYWꢀ
ꢀ
MC33
074A
ALYWꢀ
ꢀ
NCV3
074A
ALYWꢀ
ꢀ
1
1
1
1
1
1
WQFN10
MT SUFFIX
CASE 510AJ
4072
AAYW
ꢀ
x
= 3 or 4
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or = Pb−Free Package
ꢀ
(Note: Microdot may be in either location)
http://onsemi.com
20
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE M
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME
A
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RE-
STRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
D1
E
8
5
4
INCHES
NOM
−−−− 0.210
MILLIMETERS
E1
DIM MIN
−−−−
A1 0.015
b
C
D
MAX
MIN
NOM
−−−−
MAX
5.33
A
−−−−
0.38
0.35
0.20
9.02
0.13
7.62
6.10
1
−−−− −−−−
−−−− −−−−
0.014 0.018 0.022
0.008 0.010 0.014
0.355 0.365 0.400
0.46
0.25
0.56
0.36
NOTE 5
9.27 10.02
F
c
D1 0.005
0.300 0.310 0.325
E1 0.240 0.250 0.280
−−−− −−−−
−−−− −−−−
E
7.87
6.35
8.26
7.11
E2
TOP VIEW
END VIEW
E2
E3
e
0.300 BSC
−−−− 0.430
0.100 BSC
7.62 BSC
NOTE 3
−−−−
−−−−
−−−− 10.92
2.54 BSC
3.30 3.81
e/2
L
0.115 0.130 0.150
2.92
A
L
A1
SEATING
PLANE
C
E3
e
8X
b
M
0.010
C A
END VIEW
SIDE VIEW
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
B
7
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10 ꢁ
0.039
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10 ꢁ
1.01
−T−
SEATING
PLANE
J
K
0.015
D 14 PL
H
G
M
M
0.13 (0.005)
http://onsemi.com
21
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
INCHES
K1
DIM MIN
MAX
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
J J1
−−− 0.047
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0 ꢁ
8 ꢁ
0 ꢁ
8 ꢁ
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
22
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X−
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45ꢁ
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
M
J
H
D
0
0.25
5.80
8
0
8
ꢁ
ꢁ
ꢁ
ꢁ
0.50 0.010
6.20 0.228
0.020
0.244
M
S
S
0.25 (0.010)
Z
Y
X
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
23
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
0.25
B
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
0.25
C A
B
DETAIL A
h
X 45ꢁ
A
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0 ꢁ
M
A1
e
M
7ꢁ
0 ꢁ
7ꢁ
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
24
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
PACKAGE DIMENSIONS
WQFN10
CASE 510AJ
ISSUE A
NOTES:
L
L
D
B
E
A
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM
A
MIN
0.70
0.00
0.20 REF
0.20
MAX
0.80
0.05
0.15
C
A1
A3
b
EXPOSED Cu
MOLD CMPD
0.15
C
TOP VIEW
0.30
D
2.60 BSC
E
2.60 BSC
0.50 BSC
A3
DETAIL B
e
0.10
0.08
C
C
DETAIL B
L
0.45
0.00
0.55
0.55
0.15
0.65
ALTERNATE
L1
L2
A
CONSTRUCTIONS
A1
NOTE 4
SEATING
PLANE
SOLDERING FOOTPRINT*
C
SIDE VIEW
2.90
DETAIL A
5
9X
L
1
0.50
PITCH
2.90
4
1
6
9
10X
0.30
e
10X
0.73
10
L2
DIMENSIONS: MILLIMETERS
10X b
0.10
C
A
B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
0.05
C
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC34071/D
MC33074ADR2G CAD模型
引脚图
封装焊盘图
MC33074ADR2G 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| MC33074ADG | ONSEMI | Single Supply 3.0 V to 44 V Operational Amplifiers | 完全替代 |
|
| MC33074APG | ONSEMI | Single Supply 3.0 V to 44 V Operational Amplifiers | 完全替代 |
|
| NCV33074ADR2G | ONSEMI | Single Supply 3.0 V to 44 V Operational Amplifiers | 完全替代 |
|
MC33074ADR2G 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MC33074ADTB | ONSEMI | High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers | 获取价格 |
|
| MC33074ADTBG | ONSEMI | Single Supply 3.0 V to 44 V Operational Amplifiers | 获取价格 |
|
| MC33074ADTBR2 | ONSEMI | High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers | 获取价格 |
|
| MC33074ADTBR2G | ONSEMI | Single Supply 3.0 V to 44 V Operational Amplifiers | 获取价格 |
|
| MC33074AP | ONSEMI | High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers | 获取价格 |
|
| MC33074AP | MOTOROLA | HIGH BANDWIDTH SINGLE SUPPLY OPERATIONAL AMPLIFIERS | 获取价格 |
|
| MC33074AP | FREESCALE | High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers | 获取价格 |
|
| MC33074APG | ONSEMI | Single Supply 3.0 V to 44 V Operational Amplifiers | 获取价格 |
|
| MC33074AU | MOTOROLA | High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers | 获取价格 |
|
| MC33074AU | FREESCALE | High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers | 获取价格 |
|
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