MC14526BDWG [ONSEMI]
Presettable 4-Bit Down Counters; 可预置4位计数器
| 型号： | MC14526BDWG |
| 厂家： | 
ONSEMI |
| 描述： | Presettable 4-Bit Down Counters |
| 文件： | 总10页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS P−channel
and N−channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide−by−N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide−by−N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
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MARKING
DIAGRAMS
This complementary MOS counter can be used in frequency
synthesizers, phase−locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
MC14526BCP
AWLYYWWG
1
1
PDIP−16
P SUFFIX
CASE 648
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge−Clocked Design: Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
• Asynchronous Preset Enable
14526B
AWLYWWG
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• These Devices are Pb−Free and are RoHS Compliant
1
SOIC−16 WB
DW SUFFIX
CASE 751G
1
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
= Pb−Free Package
MAXIMUM RATINGS
G
Rating
Symbol
Value
Unit
V
DC Supply Voltage Range
V
DD
−0.5 to +18.0
Input or Output Voltage Range
(DC or Transient)
V ,
out
−0.5 to V + 0.5
V
in
DD
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
V
Input or Output Current
(DC or Transient) per Pin
I , I
in out
10
mA
Power Dissipation per Package (Note 1)
Operating Temperature Range
Storage Temperature Range
P
500
mW
°C
D
T
A
−55 to +125
−65 to +150
260
T
stg
°C
Lead Temperature
(8−Second Soldering)
T
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2013 − Rev. 7
MC14526B/D
MC14526B
FUNCTION TABLE
Inputs
Output
“0”
Preset Cascade
Enable Feedback
Resulting
Function
Clock Reset Inhibit
X
X
X
H
H
H
X
X
X
L
H
X
L
L
H
L
H
H
Asynchronous reset*
Asynchronous reset
Asynchronous reset
X
L
X
H
H
X
L
Asynchronous preset
L
L
L
L
X
X
L
L
Decrement inhibited
Decrement inhibited
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
No change** (inactive edge)
No change** (inactive edge)
Decrement**
H
H
Decrement**
X = Don’t Care
NOTES:
** Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.
PIN DESCRIPTIONS
Preset Enable (Pin 3) — If Reset is low, a high level on the
Preset Enable input asynchronously loads the counter with
the programmed values on P0, P1, P2, and P3.
other than all zeroes, the “0” output is valid after the rising
edge of Preset Enable (when Cascade Feedback is high). See
the Function Table.
Inhibit (Pin 4) — A high level on the Inhibit input pre−
vents the Clock from decrementing the counter. With Clock
(pin 6) held high, Inhibit may be used as a negative edge clock
input.
Clock (Pin 6) — The counter decrements by one for each
rising edge of Clock. See the Function Table for level
requirements on the other inputs.
Cascade Feedback (Pin 13) — If the Cascade Feedback
input is high, a high level is generated at the “0” output when
the count is all zeroes. If Cascade Feedback is low, the “0”
output depends on the Preset Enable input level. See the
Function Table.
P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset
data inputs. P0 is the LSB.
Reset (Pin 10) — A high level on Reset asynchronously
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is
high, causes the “0” output to go high.
Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the
synchronous counter outputs. Q0 is the LSB.
V
SS
(Pin 8) — The most negative power supply potential.
“0” (Pin 12) — The “0” (Zero) output issues a pulse one
clock period wide when the counter reaches terminal count
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and
Preset Enable is low. When presetting the counter to a value
This pin is usually ground.
V
DD
(Pin 16) — The most positive power supply potential.
V
DD
may range from 3.0 to 18 V with respect to V .
SS
STATE DIAGRAM
MC14526B
0
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
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2
MC14526B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS
)
V
DD
−55°C
25°C
125°C
Vdc
Characteristic
Symbol
Min
Max
Min
Typ
Max
Min
Max
Unit
(Note 2)
Output Voltage
“0” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
“1” Level
“0” Level
V
= 0 or V
in
DD
Output Voltage
V
5.0
10
15
4.95
9.95
−
−
−
4.95
9.95
5.0
10
15
−
−
−
4.95
9.95
−
−
−
Vdc
Vdc
OH
V
in
= V or 0
DD
14.95
14.95
14.95
“1” Level
“0” Level
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
O
O
(V = 9.0 or 1.0 Vdc)
(V = 13.5 or 1.5 Vdc)
“1” Level
(V = 0.5 or 4.5 Vdc)
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Input Voltage
(V = 4.5 or 0.5 Vdc)
“0” Level
“1” Level
V
IH
Vdc
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
(V = 0.5 or 4.5 Vdc)
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
−3.0
−0.64
−1.6
−
−
−
−
–2.4
–0.51
–1.3
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
15
–4.2
–3.4
–2.4
OH
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
(V = 0.4 Vdc)
OL
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
I
15
−
−
0.1
−
−
ꢀ0.00001
0.1
7.5
−
−
1.0
mAdc
in
Input Capacitance
C
−
−
5.0
−
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
mAdc
Total Supply Current (Notes 3, 4)
5.0
10
15
I = (1.7 mA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent, Per Package)
I = (3.4 mA/kHz) f + I
T
(C = 50 pF on all outputs, all buffers
I = (5.1 mA/kHz) f + I
L
T
switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in mA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001.
T
L
DD
SS
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3
MC14526B
SWITCHING CHARACTERISTICS (C = 50 pF, T = 25_C) (Note 5)
L
A
Typ
(Note 6)
Characteristic
Output Rise and Fall Time
Symbol
V
Min
Max
Unit
DD
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH THL
L
THL
, t
= (0.75 ns/pF) C + 12.5 ns
(Figures 4, 5)
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
TLH THL
L
Propagation Delay Time (Inhibit Used as Negative
Edge Clock)
Clock or Inhibit to Q
t
,
ns
PLH
t
PHL
(Figures 4, 5, 6)
5.0
10
15
−
−
−
550
225
160
1100
450
320
t
t
t
, t
= (1.7 ns/pF) C + 465 ns
PLH PHL L
, t
= (0.66 ns/pF) C + 197 ns
L
PLH PHL
, t
= (0.5 ns/pF) C + 135 ns
PLH PHL
L
Clock or Inhibit to “0”
t
t
t
, t
= (1.7 ns/pF) C + 155 ns
PLH PHL L
5.0
10
15
−
−
−
240
130
100
480
260
200
, t
= (0.66 ns/pF) C + 87 ns
L
PLH PHL
, t
= (0.5 ns/pF) C + 65 ns
PLH PHL
L
Propagation Delay Time
Pn to Q
t
,
5.0
10
15
−
−
−
260
120
100
520
240
200
ns
ns
PLH
t
PHL
(Figures 4, 7)
Propagation Delay Time
Reset to Q
t
5.0
10
15
−
−
−
250
110
80
500
220
160
PHL
(Figure 8)
Propagation Delay Time
Preset Enable to “0”
t
,
5.0
10
15
−
−
−
220
100
80
440
200
160
ns
PHL
t
PLH
(Figures 4, 9)
Clock or Inhibit Pulse Width
t
5.0
10
15
250
100
80
125
50
40
−
−
−
ns
w
(Figures 5, 6)
Clock Pulse Frequency (with PE = low)
Clock or Inhibit Rise and Fall Time
f
5.0
10
15
−
−
−
2.0
5.0
6.6
1.5
3.0
4.0
MHz
ms
max
(Figures 4, 5, 6)
t ,
5.0
10
15
−
−
−
−
−
−
15
5
4
r
t
f
(Figures 5, 6)
Setup Time
t
5.0
10
15
90
50
40
40
15
10
−
−
−
ns
su
Pn to Preset Enable
(Figure 1)
Hold Time
t
5.0
10
15
30
30
30
– 15
– 5
0
−
−
−
ns
h
Preset Enable to Pn
(Figure 2)
Preset Enable Pulse Width
Reset Pulse Width
t
5.0
10
15
250
100
80
125
50
−
−
−
ns
w
(Figure 3)
40
t
w
5.0
10
15
350
250
200
175
125
100
−
−
−
ns
(Figure 8)
Reset Removal Time
t
5.0
10
15
10
20
30
– 110
– 30
– 20
−
−
−
ns
rem
(Figure 8)
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14526B
V
OL
V
OH
V
DD
= V
GS
V
DD
= -V
GS
CF
PE
P0
P1
P2
P3
Q0
Q1
CF
PE
P0
P1
P2
P3
Q0
Q1
Q2
Q2
I
OL
I
OH
RESET Q3
INHIBIT
RESET Q3
INHIBIT
CLOCK “0”
CLOCK “0”
EXTERNAL
POWER
SUPPLY
EXTERNAL
POWER
SUPPLY
V
SS
V
SS
Figure 1. Typical Output Source
Characteristics Test Circuit
Figure 2. Typical Output Sink
Characteristics Test Circuit
V
DD
Q0
Q1
CF
PE
P0
P1
Q2
Q3
“0”
P2
P3
C
L
TEST POINT
RESET
INHIBIT
CLOCK
C
L
C
L
Q or “0”
C
L
DEVICE
UNDER
TEST
V
SS
C
L
C *
L
PULSE
GENERATOR
20 ns
20 ns
V
DD
90%
10%
VARIABLE
WIDTH
CLOCK
50%
V
SS
*Includes all probe and jig capacitance.
50% DUTY CYCLE
Figure 3. Power Dissipation
Figure 4. Test Circuit
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5
MC14526B
SWITCHING WAVEFORMS
t
r
t
f
t
f
t
r
V
V
V
DD
DD
90%
50%
10%
90%
50%
10%
CLOCK
INHIBIT
V
SS
SS
t
w
t
w
1/f
max
1/f
max
t
t
PHL
t
t
PHL
PLH
PLH
90%
50%
10%
90%
50%
10%
ANY Q
OR “0”
ANY Q
OR “0”
t
t
t
t
TLH
THL
TLH
THL
Figure 5.
Figure 6.
t
w
V
V
DD
RESET
50%
SS
t
r
t
f
t
PHL
V
DD
90%
50%
10%
ANY P
ANY Q
50%
V
SS
t
t
PHL
PLH
t
rem
V
V
DD
ANY Q
50%
CLOCK
50%
SS
Figure 7.
Figure 8.
VALID
t
t
f
V
V
r
DD
V
ANY P
DD
50%
90%
50%
10%
PRESET
ENABLE
SS
GND
t
h
t
su
t
t
PLH
PHL
V
DD
PRESET
ENABLE
50%
“0”
50%
V
SS
t
w
Figure 9.
Figure 10.
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6
MC14526B
MC14526B LOGIC DIAGRAM
(Binary Down Counter)
P0
Q0
P1
11
Q1
P2
14
Q2
P3
Q3
5
7
9
15
2
1
R
R
R
R
Q
Q
Q
Q
Q
Q
D
C
T
D
D
D
C
T
C
T
C
T
Q
PE
PE
PE
PE
V
DD
V
DD
13
CF
3
4
PE
INHIBIT
12
“0”
CLOCK
RESET
6
10
APPLICATIONS INFORMATION
Divide−By−N, Single Stage
Cascaded, Presettable Divide−By−N
Figure 11 shows a single stage divide−by−N application.
To initialize counting a number, N is set on the parallel
inputs (P0, P1, P2, and P3) and reset is taken high
asynchronously. A zero is forced into the master and slave
of each bit and, at the same time, the “0” output goes high.
Because Preset Enable is tied to the “0” output, preset is
enabled. Reset must be released while the Clock is high so
the slaves of each bit may receive N before the Clock goes
low. When the Clock goes low and Reset is low, the “0”
output goes low (if P0 through P3 are unequal to zero).
The counter downcounts with each rising edge of the
Clock. When the counter reaches the zero state, an output
pulse occurs on “0” which presets N. The propagation delays
from the Clock’s rising and falling edges to the “0” output’s
rising and falling edges are about equal, making the “0”
output pulse approximately equal to that of the Clock pulse.
The Inhibit pin may be used to stop pulse counting. When
this pin is taken high, decrementing is inhibited.
Figure 12 shows a three stage cascade application. Taking
Reset high loads N. Only the first stage’s Reset pin (least
significant counter) must be taken high to cause the preset
for all stages, but all pins could be tied together, as shown.
When the first stage’s Reset pin goes high, the “0” output
is latched in a high state. Reset must be released while Clock
is high and time allowed for Preset Enable to load N into all
stages before Clock goes low.
When Preset Enable is high and Clock is low, time must
be allowed for the zero digits to propagate a Cascade
Feedback to the first non−zero stage. Worst case is from the
most significant bit (M.S.B.) to the L.S.B., when the L.S.B.
is equal to one (i.e. N = 1).
After N is loaded, each stage counts down to zero with
each rising edge of Clock. When any stage reaches zero and
the leading stages (more significant bits) are zero, the “0”
output goes high and feeds back to the preceding stage.
When all stages are zero, the Preset Enable automatically
loads N while the Clock is high and the cycle is renewed.
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MC14526B
P0
P1
P2
P3
Q0
Q1
Q2
Q3
N
BUFFER
V
DD
f
in
CF
RESET
INHIBIT
“0”
N
V
SS
f
in
CLOCK
PE
Figure 11. ÷ N Counter
LSB
N0 N1 N2 N3
MSB
N8 N9 N10 N11
N4 N5 N6 N7
V
DD
P0 P1 P2 P3 Q0 Q1 Q2 Q3
CLOCK
P0 P1 P2 P3 Q0 Q1 Q2 Q3
CLOCK
P0 P1 P2 P3 Q0 Q1 Q2 Q3
CLOCK
f
in
CF
CF
CF
INHIBIT
RESET
INHIBIT
RESET
INHIBIT
RESET
V
SS
“0”
PE
“0”
PE
V
SS
“0”
PE
V
SS
V
DD
LOAD
N
BUFFER
10
KW
V
SS
f
in
N
Figure 12. 3 Stages Cascaded
ORDERING INFORMATION
†
Device
Package
Shipping
MC14526BCPG
PDIP−16
500 Units / Rail
47 Units / Rail
(Pb−Free)
MC14526BDWG
SOIC−16
(Pb−Free)
MC14526BDWR2G
SOIC−16
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
MC14526B
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G−03
ISSUE D
NOTES:
A
D
q
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
1
8
A
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
B
16X B
M
S
S
B
0.25
T A
0.25
0.50
0
0.75
0.90
7
_
_
14X
e
C
SEATING
PLANE
T
SOLDERING FOOTPRINT
16X
0.58
11.00
1
16X
1.62
1.27
PITCH
DIMENSIONS: MILLIMETERS
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9
MC14526B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
M
S
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T A
0
10
_
_
_
_
0.020 0.040
0.51
1.01
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