MC14069UBCPDG_技术文档

The MC14069UB hex inverter is constructed with MOS P–channel

and N–channel enhancement mode devices in a single monolithic

structure. These inverters find primary use where low power

dissipation and/or high noise immunity is desired. Each of the six

inverters is a single stage to minimize propagation delays.

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• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

• Triple Diode Protection on All Inputs

• Pin–for–Pin Replacement for CD4069UB

• Meets JEDEC UB Specifications

MARKING

DIAGRAMS

14

PDIP–14

P SUFFIX

CASE 646

MC14069UBCP

AWLYYWW

1

14

SOIC–14

D SUFFIX

CASE 751A

14069U

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)

SS

Symbol

Parameter

Value

Unit

V

1

V

DD

DC Supply Voltage Range

–0.5 to +18.0

14

V , V

Input or Output Voltage Range

(DC or Transient)

–0.5 to V + 0.5

V

in out

DD

TSSOP–14

DT SUFFIX

CASE 948G

14

069U

ALYW

I , I

in out

Input or Output Current

(DC or Transient) per Pin

±10

mA

1

P

Power Dissipation,

per Package (Note 3.)

500

mW

14

1

D

SOEIAJ–14

F SUFFIX

CASE 965

MC14069U

AWLYWW

T

A

Ambient Temperature Range

Storage Temperature Range

–55 to +125

–65 to +150

260

°C

T

stg

T

Lead Temperature

L

(8–Second Soldering)

A

= Assembly Location

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

ORDERING INFORMATION

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

Device

Package

PDIP–14

SOIC–14

Shipping

high–impedancecircuit. For proper operation, V and V should be constrained

in

out

MC14069UBCP

MC14069UBD

MC14069UBDR2

MC14069UBDT

2000/Box

2750/Box

to the range V

(V or V

)

V

DD

.

SS

in

out

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V or V ). Unused outputs must be left open.

SS

DD

SOIC–14 2500/Tape & Reel

96/Rail

TSSOP–14

MC14069UBDTEL TSSOP–14 2000/Tape & Reel

MC14069UBDTR2 TSSOP–14 2500/Tape & Reel

MC14069UBF

SOEIAJ–14

See Note 1.

MC14069UBFEL SOEIAJ–14

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

Semiconductor Components Industries, LLC, 2000

1

Publication Order Number:

March, 2000 – Rev. 3

MC14069UB/D

MC14069UB

PIN ASSIGNMENT

IN 1

OUT 1

IN 2

1

2

3

4

5

6

7

14

V

DD

13 IN 6

12 OUT 6

11 IN 5

OUT 2

IN 3

10 OUT 5

OUT 3

9

8

IN 4

V

SS

OUT 4

LOGIC DIAGRAM

CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN)

1

3

2

V

DD

V

= PIN 14

= PIN 7

DD

4

SS

5

6

INPUT*

OUTPUT

9

8

11

13

10

12

V

SS

*Double diode protection on all

inputs not shown.

20 ns

V

DD

V

DD

90%

14

OUTPUT

50%

10%

INPUT

PULSE

GENERATOR

V

SS

INPUT

t

PLH

PHL

C

L

V

OH

7

V

SS

90%

50%

10%

OUTPUT

V

OL

t

TLH

THL

Figure 1. Switching Time Test Circuit and Waveforms

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2

MC14069UB

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

– 55 C

25 C

125 C

Max

Symbo

l

V

DD

Vdc

(4.)

Characteristic

Unit

Min

Max

Min

Typ

Max

Min

Output Voltage

“0” Level

“1” Level

“0” Level

V

5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

OL

V

in

= V

DD

V

OH

5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

V

in

= 0

Input Voltage

(V = 4.5 Vdc)

V

IL

5.0

10

15

—

1.0

2.0

2.5

—

2.25

4.50

6.75

1.0

2.0

2.5

—

1.0

2.0

2.5

O

(V = 9.0 Vdc)

O

(V = 13.5 Vdc)

O

“1” Level

V

IH

Vdc

(V = 0.5 Vdc)

5.0

10

15

4.0

8.0

12.5

—

4.0

8.0

12.5

2.75

5.50

8.25

—

4.0

8.0

12.5

—

O

(V = 1.0 Vdc)

O

(V = 1.5 Vdc)

O

Output Drive Current

I

mAdc

OH

(V = 2.5 Vdc)

Source

Sink

5.0

10

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

OH

(V = 4.6 Vdc)

OH

(V = 9.5 Vdc)

OH

(V = 13.5 Vdc)

OH

15

(V = 0.4 Vdc)

I

OL

5.0

10

15

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

OL

(V = 0.5 Vdc)

OL

(V = 1.5 Vdc)

OL

Input Current

Input Capacitance

I

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

in

C

—

5.0

7.5

—

pF

in

(V = 0)

in

Quiescent Current

(Per Package)

I

5.0

10

15

—

0.25

0.5

1.0

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

7.5

15

30

µAdc

ns

DD

(5.) (6.)

Total Supply Current

I

T

5.0

10

15

I = (0.3 µA/kHz) f + I /6

T DD

I = (0.6 µA/kHz) f + I /6

T DD

I = (0.9 µA/kHz) f + I /6

T

(Dynamic plus Quiescent,

Per Gate) (C = 50 pF)

L

DD

(5.)

Output Rise and Fall Times

t

,

TLH

(C = 50 pF)

t

5.0

10

15

—

100

50

40

200

100

80

—

L

THL

t

, t

= (1.35 ns/pF) C + 33 ns

TLH THL

L

, t

= (0.60 ns/pF) C + 20 ns

TLH THL

L

, t

= (0.40 ns/pF) C + 20 ns

TLH THL

L

(5.)

Propagation Delay Times

(C = 50 pF)

t

,

ns

PLH

L

PHL

t

, t

= (0.90 ns/pF) C + 20 ns

= (0.36 ns/pF) C + 22 ns

L

5.0

10

15

—

65

40

30

125

75

55

—

PLH PHL

L

, t

PLH PHL

, t

= (0.26 ns/pF) C + 17 ns

PLH PHL

L

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25 C.

6. To calculate total supply current at loads other than 50 pF:

I (C ) = I (50 pF) + (C – 50) Vfk

T

L

T

L

where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.002.

T

L

DD

SS

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3

MC14069UB

PACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

14

1

8

7

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

B

INCHES

DIM MIN MAX

0.770 18.16

MILLIMETERS

A

F

MIN

MAX

18.80

6.60

4.69

0.53

1.78

A

B

C

D

F

0.715

0.240

0.145

0.015

0.040

0.260

0.185

0.021

0.070

6.10

3.69

0.38

1.02

L

N

C

G

H

J

K

L

0.100 BSC

2.54 BSC

0.052

0.008

0.115

0.290

–––

0.095

0.015

0.135

0.310

10

1.32

0.20

2.92

7.37

–––

2.41

0.38

3.43

7.87

10

–T–

SEATING

PLANE

J

K

M

N

0.015

0.039

0.38

1.01

D 14 PL

H

G

M

0.13 (0.005)

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4

MC14069UB

PACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

–A–

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

14

1

8

7

–B–

P 7 PL

M

0.25 (0.010)

B

MILLIMETERS

DIM MIN MAX

INCHES

G

MIN

MAX

0.344

0.157

0.068

0.019

0.049

F

R X 45

C

A

B

C

D

F

8.55

3.80

1.35

0.35

0.40

8.75 0.337

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

–T–

SEATING

PLANE

J

M

G

J

K

M

P

1.27 BSC

0.050 BSC

K

D 14 PL

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

M

S

0.25 (0.010)

T B

A

7

0

5.80

0.25

6.20 0.228

0.50 0.010

0.244

0.019

R

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5

MC14069UB

PACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

14X K REF

M

S

Y14.5M, 1982.

0.10 (0.004)

T U

V

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS. MOLD

FLASH OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT

EXCEED

S

0.15 (0.006) T U

N

0.25 (0.010)

14

8

2X L/2

M

B

–U–

0.25 (0.010) PER SIDE.

L

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

N

PIN 1

IDENT.

F

7

1

DETAIL E

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE –W–.

S

K

0.15 (0.006) T U

A

MILLIMETERS

MAX

INCHES

K1

DIM MIN

MIN

5.10 0.193

4.50 0.169

–––

0.15 0.002

0.75 0.020

MAX

0.200

0.177

0.047

0.006

0.030

–V–

A

B

C

4.90

4.30

–––

J J1

1.20

D

F

0.05

0.50

SECTION N–N

G

H

J

J1

K

K1

L

0.65 BSC

0.026 BSC

0.50

0.09

0.19

0.60 0.020

0.20 0.004

0.16 0.004

0.30 0.007

0.25 0.007

0.024

0.008

0.006

0.012

0.010

–W–

C

6.40 BSC

0.252 BSC

0.10 (0.004)

M

0

8

0

8

SEATING

PLANE

–T–

H

G

DETAIL E

D

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6

MC14069UB

PACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

L

E

14

8

Q

1

H

E

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

E

M

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

L

7

1

DETAIL P

Z

D

VIEW P

MILLIMETERS

INCHES

A

e

DIM MIN

MAX

2.05

MIN

–––

MAX

0.081

0.008

0.020

0.011

0.413

0.215

c

A

1

–––

0.05

0.35

0.18

9.90

5.10

A

0.20 0.002

0.50 0.014

0.27 0.007

10.50 0.390

5.45 0.201

b

c

D

E

e

H

E

0.50

A

b

1

M

1.27 BSC

0.050 BSC

0.13 (0.005)

0.10 (0.004)

7.40

0.50

1.10

0

8.20 0.291

0.85 0.020

1.50 0.043

10

0.90 0.028

1.42 –––

0.323

0.033

0.059

10

0.035

0.056

L

E

M

0

Q

Z

0.70

–––

1

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7

MC14069UB

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

CENTRAL/SOUTH AMERICA:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

001–800–4422–3781

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

Email: ONlit–asia@hibbertco.com

EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–german@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549

Phone: 81–3–5740–2745

French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)

Email: ONlit–french@hibbertco.com

English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, England, Ireland

MC14069UB/D

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8


型号：	MC14069UBCPDG
厂家：	ONSEMI
描述：	IC 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDIP14, GREEN, PLASTIC, DIP-14, Gate
文件：	总8页 (文件大小：175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC14069UBCPDG [ONSEMI]

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