MC14051B_06 [ONSEMI]
Analog Multiplexers/Demultiplexers; 模拟多路复用器/多路解复用器
| 型号： | MC14051B_06 |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexers/Demultiplexers |
| 文件： | 总12页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally−controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
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MARKING
DIAGRAMS
Features
16
1
• Triple Diode Protection on Control Inputs
• Switch Function is Break Before Make
MC1405xBCP
AWLYYWWG
PDIP−16
P SUFFIX
CASE 648
1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (V − V ) = 3.0 to 18 V
DD
EE
Note: V must be v V
EE
SS
• Linearized Transfer Characteristics
16
1
• Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin−for−Pin Replacement for CD4051, CD4052, and CD4053
• For 4PDT Switch, See MC14551B
1405xBG
AWLYWW
SOIC−16
D SUFFIX
CASE 751B
1
• For Lower R , Use the HC4051, HC4052, or HC4053 High−Speed
ON
CMOS Devices
• Pb−Free Packages are Available*
16
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
14
05xB
ALYWG
G
Symbol
Parameter
Value
Unit
TSSOP−16
DT SUFFIX
CASE 948F
V
DC Supply Voltage Range
−0.5 to +18.0
V
DD
1
(Referenced to V , V ≥ V )
EE
SS
EE
1
V ,
Input or Output Voltage Range
(DC or Transient) (Referenced to V for
−0.5 to V + 0.5
V
in
out
DD
V
SS
Control Inputs and V for Switch I/O)
EE
16
1
I
Input Current (DC or Transient)
per Control Pin
+10
mA
in
MC1405xB
ALYWG
SOEIAJ−16
F SUFFIX
CASE 966
I
Switch Through Current
25
500
mA
mW
°C
SW
1
P
T
Power Dissipation per Package (Note 1)
Ambient Temperature Range
D
−55 to +125
−65 to +150
260
A
T
stg
Storage Temperature Range
°C
x
A
= 1, 2, or 3
= Assembly Location
= Wafer Lot
T
Lead Temperature (8−Second Soldering)
°C
L
WL, L
Y
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From
65_C To 125_C
= Year
WW, W = Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
G or G
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
ORDERING INFORMATION
See detailed ordering and shipping information in the package
high−impedance circuit. For proper operation, V and V should be constrained to
in
out
the range V v (V or V ) v V
.
SS
in
out
DD
dimensions section on page 9 of this data sheet.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
V
, V or V ). Unused outputs must be left open.
SS EE
DD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 10
MC14051B/D
MC14051B, MC14052B, MC14053B
MC14051B
MC14052B
MC14053B
8−Channel Analog
Multiplexer/Demultiplexer
Dual 4−Channel Analog
Multiplexer/Demultiplexer
Triple 2−Channel Analog
Multiplexer/Demultiplexer
6
11
10
9
INHIBIT
A
6
CONTROLS 10
INHIBIT
A
6
11
10
9
INHIBIT
A
14
15
X
Y
CONTROLS
CONTROLS
X
Y
13
B
C
9
12
14
15
B
X0
B
C
COMMONS
OUT/IN
X1
X2
X3
Y0
Y1
Y2
Y3
X0
X1
13
14
15
12
1
X0
X1
X2
X3
X4
X5
X6
X7
12
13
2
COMMONS
OUT/IN
X
3
COMMON
SWITCHES
IN/OUT
SWITCHES
IN/OUT
11
1
Y0
Y1
Z0
Z1
SWITCHES
IN/OUT
1
5
OUT/IN
3
Z
4
5
5
2
3
2
4
4
V
= PIN 16
= PIN 8
= PIN 7
V
= PIN 16
= PIN 8
= PIN 7
V
DD
= PIN 16
= PIN 8
= PIN 7
DD
DD
V
V
V
SS
EE
SS
EE
SS
EE
V
V
V
Note: Control Inputs referenced to V , Analog Inputs and Outputs reference to V . V must be ≤ V
SS
.
SS
EE
EE
PIN ASSIGNMENT
MC14052B
MC14051B
MC14053B
X4
X6
X
1
2
3
4
5
6
7
8
16
V
DD
Y0
Y2
Y
1
2
3
4
5
6
7
8
16
V
DD
Y1
Y0
Z1
Z
1
2
3
4
5
6
7
8
16
15
14
V
Y
X
DD
15 X2
14 X1
13 X0
12 X3
15 X2
14 X1
X7
X5
INH
Y3
Y1
INH
13
X
13 X1
12 X0
12 X0
11 X3
Z0
INH
11
10
9
A
B
C
11
10
9
A
B
C
V
V
10
9
A
B
V
EE
EE
EE
V
V
V
SS
SS
SS
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2
MC14051B, MC14052B, MC14053B
ELECTRICAL CHARACTERISTICS
− 55_C
Min Max Min
25_C
Typ
125_C
Max Min Max
Characteristic
Symbol
V
Test Conditions
Unit
DD
(Note 2)
SUPPLY REQUIREMENTS (Voltages Referenced to V
)
EE
Power Supply Voltage
Range
V
−
3.0
18
3.0
−
18
3.0
18
V
V
– 3.0 ≥ VSS ≥ V
EE
DD
DD
Quiescent Current Per
Package
I
5.0 Control Inputs:
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mA
DD
10
15
V
= V or V
,
DD
in
SS
Switch I/O: V v V
v
EE
I/O
v
V
, and DV
DD
switch
500 mV (Note 3)
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
I
5.0 T = 25_C only (The
mA
D(AV)
A
(0.07 mA/kHz) f + I
(0.20 mA/kHz) f + I
(0.36 mA/kHz) f + I
DD
DD
DD
10
15
channel component,
Typical
(V – V )/R , is
in out on
not included.)
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to V
)
SS
Low−Level Input Voltage
High−Level Input Voltage
V
5.0
10
15
R
= per spec,
= per spec
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
V
V
IL
IH
in
on
I
off
V
5.0
10
15
R
on
= per spec,
= per spec
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
I
off
Input Leakage Current
Input Capacitance
I
15
−
V
in
= 0 or V
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mA
DD
C
pF
in
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to V
)
EE
Recommended
Peak−to−Peak Voltage
Into or Out of the Switch
V
−
Channel On or Off
0
V
0
0
−
−
V
0
0
V
V
PP
I/O
DD
DD
DD
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 5)
DV
−
Channel On
0
600
600
300
mV
switch
Output Offset Voltage
ON Resistance
V
−
V
= 0 V, No Load
−
−
−
10
−
−
−
mV
OO
in
R
5.0 DV
10
15
v 500 mV
(Note 3) V = V or V
in IL IH
(Control), and V
−
−
−
800
400
220
−
−
−
250
120
80
1050
500
280
−
−
−
1200
520
300
W
on
switch
=
in
0 to V (Switch)
DD
DON Resistance Between
Any Two Channels in the
Same Package
DR
5.0
10
15
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W
on
Off−Channel Leakage
Current (Figure 10)
I
15
V
= V or V
IH
−
100
−
0.05
100
−
1000 nA
off
in
IL
(Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O
C
C
−
−
Inhibit = V
Inhibit = V
−
−
−
10
−
−
−
pF
pF
I/O
DD
Capacitance, Common O/I
O/I
DD
(MC14051B)
(MC14052B)
(MC14053B)
−
−
−
−
−
−
−
−
−
60
32
17
−
−
−
−
−
−
−
−
−
Capacitance, Feedthrough
(Channel Off)
C
I/O
−
−
Pins Not Adjacent
Pins Adjacent
−
−
−
−
−
−
0.15
0.47
−
−
−
−
−
−
pF
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DV ) > 600 mV ( > 300 mV at high temperature), excessive V current may be drawn, i.e. the
switch
DD
current out of the switch may contain both V and switch input components. The reliability of the device will be unaffected unless the
DD
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
MC14051B, MC14052B, MC14053B
ELECTRICAL CHARACTERISTICS (Note 4) (C = 50 pF, T = 25_C) (V v V unless otherwise indicated)
L
A
EE
SS
Characteristic
Symbol
V
– V
Typ (Note 5)
Max
Unit
DD
EE
Vdc
All Types
Propagation Delay Times (Figure 6)
t
, t
ns
PLH PHL
Switch Input to Switch Output (R = 10 kW)
L
MC14051
t
t
t
, t
= (0.17 ns/pF) C + 26.5 ns
5.0
10
15
35
15
12
90
40
30
PLH PHL
L
, t
= (0.08 ns/pF) C + 11 ns
PLH PHL
L
, t
= (0.06 ns/pF) C + 9.0 ns
L
PLH PHL
MC14052
ns
ns
ns
t
t
t
, t
= (0.17 ns/pF) C + 21.5 ns
5.0
10
15
30
12
10
75
30
25
PLH PHL
L
, t
= (0.08 ns/pF) C + 8.0 ns
PLH PHL
L
, t
= (0.06 ns/pF) C + 7.0 ns
L
PLH PHL
MC14053
t
t
t
, t
= (0.17 ns/pF) C + 16.5 ns
5.0
10
15
25
8.0
6.0
65
20
15
PLH PHL
L
, t
= (0.08 ns/pF) C + 4.0 ns
PLH PHL
L
, t
= (0.06 ns/pF) C + 3.0 ns
L
PLH PHL
Inhibit to Output (R = 10 kW, V = V
)
SS
t
, t
,
L
EE
PHZ PLZ
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
MC14051B
t
, t
PZH PZL
5.0
10
15
350
170
140
700
340
280
MC14052B
MC14053B
5.0
10
15
300
155
125
600
310
250
ns
ns
ns
5.0
10
15
275
140
110
550
280
220
Control Input to Output (R = 10 kW, V = V
)
SS
t
, t
L
EE
PLH PHL
MC14051B
5.0
10
15
360
160
120
720
320
240
MC14052B
5.0
10
15
325
130
90
650
260
180
ns
ns
MC14053B
5.0
10
15
300
120
80
600
240
160
Second Harmonic Distortion
−
10
0.07
−
%
(R = 10KW, f = 1 kHz) V = 5 V
L
in
PP
Bandwidth (Figure 7)
BW
10
17
−
MHz
(R = 1 kW, V = 1/2 (V −V ) p−p, C = 50pF
L
in
DD
EE
L
20 Log (V /V ) = − 3 dB)
out in
Off Channel Feedthrough Attenuation (Figure 7)
R = 1KW, V = 1/2 (V − V ) p−p
−
10
– 50
−
dB
L
in
DD
EE
f
f
f
= 4.5 MHz — MC14051B
= 30 MHz — MC14052B
= 55 MHz — MC14053B
in
in
in
Channel Separation (Figure 8)
(R = 1 kW, V = 1/2 (V −V ) p−p,
−
−
10
10
– 50
75
−
−
dB
L
in
DD
EE
f
= 3.0 MHz
in
Crosstalk, Control Input to Common O/I (Figure 9)
mV
(R = 1 kW, R = 10 kW
1
L
Control t
= t
= 20 ns, Inhibit = V
)
SS
TLH
THL
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
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4
MC14051B, MC14052B, MC14053B
V
DD
V
V
DD
DD
IN/OUT
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
V
EE
Figure 1. Switch Circuit Schematic
16
V
V
TRUTH TABLE
DD
Control Inputs
Select
INHꢀꢀ6
BINARY TO 1−OF−8
DECODER WITH
INHIBIT
ON Switches
Aꢀ11
Bꢀ10
Cꢀꢀ9
LEVEL
CONVERTER
C*
B
A
MC14051B MC14052B
MC14053B
Inhibit
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
Y0
Y1
Y2
Y3
X0
X1
X2
X3
Z0 Y0 X0
Z0 Y0 X1
Z0 Y1 X0
Z0 Y1 X1
8
V
7
SS
EE
X0ꢀ13
X1ꢀ14
X2ꢀ15
X3ꢀ12
X4ꢀꢀ1
X5ꢀꢀ5
X6ꢀꢀ2
X7ꢀꢀ4
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X4
X5
X6
X7
Z1 Y0 X0
Z1 Y0 X1
Z1 Y1 X0
Z1 Y1 X1
3ꢀX
1
x
x
x
None
None
None
*Not applicable for MC14052
x = Don’t Care
Figure 2. MC14051B Functional Diagram
16
V
DD
16
V
DD
INHꢀꢀ6
Aꢀ10
BINARY TO 1−OF−4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
INHꢀꢀ6
Aꢀ11
Bꢀ10
BINARY TO 1−OF−2
DECODER WITH
INHIBIT
LEVEL
CONVERTER
Bꢀꢀ9
Cꢀꢀ9
8
V
7
V
EE
SS
X0ꢀ12
X1ꢀ14
X2ꢀ15
X3ꢀ11
Y0ꢀꢀ1
Y1ꢀꢀ5
Y2ꢀꢀ2
Y3ꢀꢀ4
8
V
7
V
EE
SS
13ꢀX
3ꢀꢀY
X0ꢀ12
X1ꢀ13
Y0ꢀꢀ2
Y1ꢀꢀ1
Z0ꢀꢀ5
Z1ꢀꢀ3
14ꢀX
15ꢀY
4ꢀꢀZ
Figure 3. MC14052B Functional Diagram
Figure 4. MC14053B Functional Diagram
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5
MC14051B, MC14052B, MC14053B
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
A
B
C
PULSE
GENERATOR
V
out
LOAD
V
C
L
INH
R
L
SOURCE
V
V
V
V
DD
DD
EE
EE
Figure 5. DV Across Switch
Figure 6. Propagation Delay Times,
Control and Inhibit to Output
A, B, and C inputs used to turn ON
or OFF the switch under test.
R
L
A
B
C
A
B
C
ON
V
out
INH
C = 50 pF
L
R
L
V
SS
OFF
INH
V
out
V
in
R
L
C = 50 pF
L
V
− V
2
DD
EE
V
− V
2
DD
EE
V
in
Figure 7. Bandwidth and Off−Channel
Feedthrough Attenuation
Figure 8. Channel Separation
(Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST
V
V
DD
EE
A
B
C
CONTROL
SECTION
OF IC
OTHER
CHANNEL(S)
V
V
V
EE
DD
out
R
L
INH
C = 50 pF
L
R1
V
V
EE
DD
COMMON
Figure 9. Crosstalk, Control Input to
Common O/I
Figure 10. Off Channel Leakage
NOTE: See also Figures 7 and 8 in the MC14016B data sheet.
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6
0
−
−
1
8.0
6.0 −ꢂ4.0 −ꢂ2.0
0
0.2 4.0
6.0 8.0
10
0
0.2 4.0 6.0 8.0 10
0
−
−
1
8.0
6.0 −ꢂ4.0 −ꢂ2.0
0
0.2 4.0
6.0 8.0
10
MC14051B, MC14052B, MC14053B
V
DD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kW
RANGE
X−Y
PLOTTER
V
DD
V
= V
SS
EE
Figure 11. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS
350
350
300
300
250
200
150
250
200
150
100
50
T = 125°C
A
T = 125°C
A
100
25°C
25°C
−ꢂ55°C
−ꢂ55°C
50
0
−
0
−ꢂ10 −ꢂ8.0 −ꢂ6.0 −ꢂ4.0 −ꢂ2.0
V , INPUT VOLTAGE (VOLTS)
in
V , INPUT VOLTAGE (VOLTS)
in
Figure 12. VDD = 7.5 V, VEE = − 7.5 V
Figure 13. VDD = 5.0 V, VEE = − 5.0 V
350
300
700
600
T = 25°C
A
250
200
150
100
500
400
300
200
100
V
= 2.5 V
DD
T = 125°C
5.0 V
A
7.5 V
25°C
50
0
−ꢂ55°C
0
−
−ꢂ10 −ꢂ8.0 −ꢂ6.0 −ꢂ4.0 −ꢂ2.0
0
0.2 4.0 6.0 8.0 10
V , INPUT VOLTAGE (VOLTS)
in
V , INPUT VOLTAGE (VOLTS)
in
Figure 15. Comparison at 25°C, VDD = −ꢀVEE
Figure 14. VDD = 2.5 V, VEE = − 2.5 V
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7
MC14051B, MC14052B, MC14053B
APPLICATIONS INFORMATION
Figure A illustrates use of the on−chip level converter
detailed in Figures 2, 3, and 4. The 0−to−5 V Digital Control
signal is used to directly control a 9 V analog signal.
peak. If voltage transients above V and/or below V are
DD EE
anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure B. These diodes should be
small signal types able to absorb the maximum anticipated
current surges during clipping.
p−p
The digital control logic levels are determined by V
DD
and V . The V voltage is the logic high voltage; the V
SS
DD
SS
voltage is logic low. For the example, V = + 5 V = logic
The absolute maximum potential difference between
DD
high at the control inputs; V = GND = 0 V = logic low.
V
and V is 18.0 V. Most parameters are specified up to
DD EE
SS
The maximum analog signal level is determined by V
15 V which is the recommended maximum difference
between V and V
DD
and V . The V
voltage determines the maximum
.
EE
EE
DD
DD
recommended peak above
V
. The V
SS
voltage
Balanced supplies are not required. However, V must
EE
SS
determines the maximum swing below V . For the
be greater than or equal to V . For example, V = + 10
SS
EE
DD
example, V
− V = 5 V maximum swing above V
;
V, V = + 5 V, and V – 3 V is acceptable. See the Table
DD
SS
SS
SS EE
V
− V = 5 V maximum swing below V . The example
below.
SS
EE
SS
shows a 4.5 V signal which allows a 1/2 volt margin at each
+5 V
−5 V
V
V
V
EE
DD
SS
+4.5 V
9 V
SWITCH
I/O
p−p
+5 V
9 V
ANALOG SIGNAL
COMMON
O/I
p−p
GND
MC14051B
MC14052B
MC14053B
ANALOG SIGNAL
EXTERNAL
CMOS
DIGITAL
−4.5 V
0−TO−5 V DIGITAL
CONTROL SIGNALS
INHIBIT,
A, B, C
CIRCUITRY
Figure A. Application Example
V
V
DD
DD
D
D
D
X
X
X
X
ANALOG
I/O
COMMON
O/I
D
V
V
EE
EE
Figure B. External Germanium or Schottky Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS
Control Inputs
Logic High/Logic Low
In Volts
V
V
V
EE
In Volts
Maximum Analog Signal Range
In Volts
DD
SS
In Volts
In Volts
+ 8
0
0
– 8
+ 8/0
+ 5/0
+ 8 to – 8 = 16 V
p–p
+ 5
– 12
0
+ 5 to – 12 = 17 V
p–p
+ 5
0
+ 5/0
+ 5 to 0 = 5 V
p–p
+ 5
0
– 5
+ 5/0
+ 5 to – 5 = 10 V
+ 10 to – 5 = 15 V
p–p
+ 10
+ 5
– 5
+ 10/ + 5
p–p
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8
MC14051B, MC14052B, MC14053B
ORDERING INFORMATION
†
Device
MC14051BCP
Package
Shipping
PDIP−16
500 Units / Rail
500 Units / Rail
MC14051BCPG
PDIP−16
(Pb−Free)
MC14051BD
SOIC−16
48 Units / Rail
48 Units / Rail
MC14051BDG
SOIC−16
(Pb−Free)
MC14051BDR2
SOIC−16
2500 / Tape & Reel
2500 / Tape & Reel
MC14051BDR2G
SOIC−16
(Pb−Free)
MC14051BDTR2
MC14051BDTR2G
MC14051BF
TSSOP−16*
TSSOP−16*
SOEIAJ−16
2500 / Tape & Reel
2500 / Tape & Reel
50 Units / Rail
MC14051BFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14051BFEL
SOEIAJ−16
2000 / Tape & Reel
2000 / Tape & Reel
MC14051BFELG
SOEIAJ−16
(Pb−Free)
MC14052BCP
PDIP−16
500 Units / Rail
500 Units / Rail
MC14052BCPG
PDIP−16
(Pb−Free)
MC14052BD
SOIC−16
48 Units / Rail
48 Units / Rail
MC14052BDG
SOIC−16
(Pb−Free)
MC14052BDR2
SOIC−16
2500 / Tape & Reel
2500 / Tape & Reel
MC14052BDR2G
SOIC−16
(Pb−Free)
MC14052BDTR2
MC14052BDTR2G
MC14052BF
TSSOP−16*
TSSOP−16*
SOEIAJ−16
2500 / Tape & Reel
2500 / Tape & Reel
50 Units / Rail
MC14052BFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14052BFEL
SOEIAJ−16
2000 / Tape & Reel
2000 / Tape & Reel
MC14052BFELG
SOEIAJ−16
(Pb−Free)
MC14053BCP
PDIP−16
500 Units / Rail
500 Units / Rail
MC14053BCPG
PDIP−16
(Pb−Free)
MC14053BD
SOIC−16
48 Units / Rail
48 Units / Rail
MC14053BDG
SOIC−16
(Pb−Free)
MC14053BDR2
SOIC−16
2500 / Tape & Reel
2500 / Tape & Reel
MC14053BDR2G
SOIC−16
(Pb−Free)
MC14053BDTR2
MC14053BDTR2G
MC14053BF
TSSOP−16*
TSSOP−16*
SOEIAJ−16
2500 / Tape & Reel
2500 / Tape & Reel
50 Units / Rail
MC14053BFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14053BFEL
SOEIAJ−16
2000 / Tape & Reel
2000 / Tape & Reel
MC14053BFELG
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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9
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
G
0.21
0.38
3.30
7.74
10
D 16 PL
2.80
7.50
0
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
5.80
0.25
0.25
0.25
7
6.20
0.50
0.008
0.004
0
0.229
0.010
0.009
0.009
7
0.244
0.019
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
D
16 PL
M
S
S
0.25 (0.010)
T B
A
http://onsemi.com
10
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
D
F
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
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11
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE A
NOTES:
ꢃꢀ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢃꢀ2. CONTROLLING DIMENSION: MILLIMETER.
ꢃꢀ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
16
9
E
Q
1
H
E
E
M
_
ꢃꢀ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
ꢃꢀ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
A
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
c
A
A
−−−
0.05
0.35
0.10
9.90
5.10
1
0.002
0.008
0.020
0.011
0.413
0.215
b
c
0.014
0.007
0.390
0.201
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
0
0.70
−−−
10
10
0.035
−−− 0.031
M
Q
0
0.028
_
_
_
_
0.90
0.78
1
Z
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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For additional information, please contact your local
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MC14051B/D
相关型号：
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