MC10H644FN [ONSEMI]
68030/040 PECL to TTL Clock Driver; 68030/040 PECL到TTL时钟驱动器
| 型号： | MC10H644FN |
| 厂家： | 
ONSEMI |
| 描述： | 68030/040 PECL to TTL Clock Driver |
| 文件： | 总6页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10H644, MC100H644
68030/040 PECL to TTL
Clock Driver
The MC10H/100H644 generates the necessary clocks for the
68030, 68040 and similar microprocessors. The device is functionally
equivalent to the H640, but with fewer outputs in a smaller outline
20−lead PLCC package. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of
part−to−partskew, within−part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H644 also uses differential ECL internally to achieve its
superior skew characteristic.
The H644 includes divide−by−two and divide−by−four stages, both
to achieve the necessary duty cycle and skew to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Symbol).
The 10H version is compatible with MECL™ 10H ECL logic levels,
while the 100H version is compatible with 100K levels (referenced
to +5.0 V).
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MARKING
DIAGRAM
1
10H644
PLCC−20
FN SUFFIX
CASE 775
AWLYYWW
A
= Assembly Location
= Wafer Lot
= Year
WL
YY
WW
= Work Week
• Generates Clocks for 68030/040
• Meets 68030/040 Skew Requirements
• TTL or PECL Input Clock
• Extra TTL and ECL Power/Ground Pins
• Within Device Skew on Similar Paths is 0.5 ns
• Asynchronous Reset
ORDERING INFORMATION
Device
Package
Shipping
MC10H644FN
MC100H644FN
PLCC−20
37 Units/Rail
37 Units/Rail
PLCC−20
• Single +5.0 V Supply
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q
outputs HIGH.
Synchronized Outputs: The device is designed to have the POS
edges of the ÷2 and ÷4 outputs synchronized.
Select (SEL): LOW selects the PECL input source (DE/DE). HIGH
selects the TTL input source (DT).
The H644 also contains circuitry to force a stable state of the PECL
input differential pair, should both sides be left open. In this case, the
DE side of the input is pulled LOW, and DE goes HIGH.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC10H644/D
MC10H644, MC100H644
Q4 VT
18 17
Q5 GT
16 15
R
Table 1. PIN DESCRIPTION
14
PIN
FUNCTION
19
20
1
13
12
11
10
9
GT
Q3
GT
Q2
GT
VE
DE
V
GT
VT
VE
GE
TTL Ground (0 V)
TTL V (+5.0 V)
CC
ECL V (+5.0 V)
CC
ECL Ground (0 V)
DE, DE
ECL Signal Input (positive ECL)
BB
V
V
Reference Output
BB
BB
DT
TTL Signal Input
Signal Outputs (TTL)
Input Select (TTL)
Reset (TTL)
2
DE
GE
Qn, Qn
SEL
R
3
4
5
6
7
8
*Skews are specified for Identical Edges
Q1 VT
Q0 SEL DT
Figure 1. Pinout: PLCC−20 (Top View)
TTL OUTPUTS
Q0
VBB
DE
(ECL)
DE
(ECL)
Q1
Q2
÷2
2:1 MUX
DT
(TTL)
Q3
Q4
Q5
SEL
(TTL)
÷4
R
(TTL)
Figure 2. Logic Diagram
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2
MC10H644, MC100H644
Table 2. 10H PECL DC CHARACTERISTICS (V = V = 5.0 V ±5%)
T
E
0°C
25°C
85°C
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Condition
Unit
I
I
Input HIGH Current
Input LOW Current
255
175
175
mA
INH
INL
0.5
0.5
0.5
V
*
Input HIGH Voltage
Input LOW Voltage
V
V
= 5.0 V
= 5.0 V
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
3.94
3.05
4.28
3.55
V
IH
IL
E
E
V *
V
*
BB
Output Reference Voltage
3.62
3.73
3.65
3.75
3.69
3.81
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 3. 100H PECL DC CHARACTERISTICS (V = V = 5.0 V ±5%)
T
E
0°C
25°C
85°C
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Condition
Unit
I
I
Input HIGH Current
Input LOW Current
255
175
175
mA
INH
INL
0.5
0.5
0.5
V
*
Input HIGH Voltage
Input LOW Voltage
V
V
= 5.0 V
= 5.0 V
3.835
3.19
4.12
3.835
3.19
4.12
3.835
3.19
4.12
V
IH
IL
E
E
V *
3.525
3.525
3.525
V
*
BB
Output Reference Voltage
3.62
3.74
3.62
3.74
3.62
3.74
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*PECL levels are referenced to V and will vary 1:1 with the power supply. The values shown are for V = 5.0 V.
CC
CC
Only corresponds to ECL Clock Inputs.
Table 4. DC CHARACTERISTICS (V = V = 5.0 V ±5%)
T
E
0°C
25°C
85°C
Min Max
Min
Max
65
Min
Max
Symbol
Characteristic
Power Supply Current
Condition
Pin
Unit
mA
mA
I
I
ECL
TTL
V
65
85
65
85
EE
CC
E
Total all V pins
85
T
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. TTL DC CHARACTERISTICS (V = V = 5.0 V ±5%)
T
E
0°C
25°C
85°C
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Input HIGH Voltage
Condition
Unit
V
V
2.0
2.0
2.0
V
IH
IL
Input LOW Voltage
0.8
0.8
0.8
I
Input HIGH Current
V
V
= 2.7 V
= 7.0 V
20
100
20
100
20
100
mA
IH
IN
IN
I
Input LOW Current
V
= 0.5 V
−0.6
−0.6
−0.6
mA
V
IL
IN
V
Output HIGH Voltage
I
= −3.0 mA
= −24 mA
2.5
2.0
2.5
2.0
2.5
2.0
OH
OH
OH
I
V
V
Output LOW Voltage
I
= 24 mA
OL
0.5
0.5
0.5
V
V
OL
IK
Input Clamp Voltage
I
= −18 mA
−1.2
−1.2
−1.2
IN
I
Output Short Circuit Current
V
= 0 V
OUT
−100 −225 −100 −225 −100 −225
mA
OS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC10H644, MC100H644
Table 6. AC CHARACTERISTICS (V = V = 5.0 V ±5%)
T
E
0°C
Min Max
25°C
85°C
Min
Max
Min
Max
Symbol
Characteristic
Condition
Unit
t
Propagation Delay ECL
D to Output
All Outputs
CL = 50 pF
5.8
6.8
5.7
6.7
6.1
7.1
ns
PLH
t
Propagation Delay TTL
D to Output
CL = 50 pF
5.7
6.7
5.7
6.7
6.0
7.0
ns
PLH
t
t
t
t
t
*
*
*
Within−Device Skew
Within−Device Skew
Within−Device Skew
Part−to−Part Skew
Q0, 1, 4, 5
Q2, Q3
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
−
−
0.5
0.5
1.5
1.0
7.3
−
−
0.5
0.5
1.5
1.0
7.3
−
−
0.5
0.5
1.5
1.0
7.5
ns
ns
ns
ns
ns
skwd
skwd
skwd
All Outputs
Q0, 1, 4, 5
All Outputs
−
−
−
*
−
−
−
skp−p
Propagation Delay
R to Output
4.3
4.3
4.5
PD
t
t
Output Rise/Fall Time
All Outputs
CL = 50 pF
CL = 50 pF
−
1.6
−
1.6
−
1.6
ns
R
F
0.8 V − 2.0 V
f
Maximum Input Frequency
Minimum Pulse Width Reset
Reset Recovery Time
135
1.5
−
−
135
1.5
−
−
135
1.5
−
−
MHz
ns
max
TW
t
1.25
9.5
−
1.25
9.5
−
1.25
9.5
−
ns
rr
T
Pulse Width Out High or Low @ f
= 100 MHz and CL = 50 pF
Q0, 1
CL = 50 pF
Relative 1.5 V
10.5
10.5
10.5
ns
PW
in
T
Setup Time
ns
ns
S
SEL to DE, DT
2.0
2.0
−
−
2.0
2.0
−
−
2.0
2.0
−
−
TH
Hold Time
SEL to DE, DT
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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4
MC10H644, MC100H644
PACKAGE DIMENSIONS
PLCC−20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775−02
ISSUE D
S
S
0.007 (0.180) M
T
L−M
N
B
Y BRK
−N−
M
S
S
N
0.007 (0.180)
T
L−M
U
D
D
−L−
−M−
Z
W
20
1
S
S
S
N
0.010 (0.250)
T
L−M
G1
X
V
VIEW D−D
S
S
S
S
0.007 (0.180) M
0.007 (0.180) M
T
L−M
L−M
N
N
A
R
Z
T
S
S
N
0.007 (0.180) M
T
L−M
H
C
K1
E
K
0.004 (0.100)
G
−T− SEATING
PLANE
J
M
S
S
N
0.007 (0.180)
T
L−M
F
VIEW S
G1
VIEW S
S
S
S
0.010 (0.250)
T
L−M
N
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
INCHES
MILLIMETERS
DIM MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
A
B
C
E
F
0.385
0.385
0.165
0.090
0.013
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.350
0.350
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
−−−
2
0.81
−−−
−−−
9.04
9.04
1.21
1.21
1.42
0.50
10
K
R
U
V
W
X
Y
Z
0.356
0.356
0.048
0.048
0.056
−−− 0.020
10
2
_
_
_
_
G1 0.310
K1 0.040
0.330
−−−
7.88
1.02
8.38
−−−
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5
MC10H644, MC100H644
MECL is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC10H644/D
相关型号：
MC10H644FNR2
10H SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC20, PLASTIC, LCC-20
MOTOROLA
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