MC10H642FNR2 [ONSEMI]
68030/040 PECL to TTL Clock Driver; 68030/040 PECL到TTL时钟驱动器
| 型号： | MC10H642FNR2 |
| 厂家： | 
ONSEMI |
| 描述： | 68030/040 PECL to TTL Clock Driver |
| 文件： | 总10页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10H642, MC100H642
68030/040 PECL to TTL
Clock Driver
Description
The MC10H/100H642 generates the necessary clocks for the
68030, 68040 and similar microprocessors. It is guaranteed to meet the
clock specifications required by the 68030 and 68040 in terms of
part−to−partskew, within−part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H642 also uses differential PECL internally to achieve its
superior skew characteristic.
The H642 includes divide−by−two and divide−by−four stages, both
to achieve the necessary duty cycle skew and to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Diagram).
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
The 10H version is compatible with MECL 10H™ ECL logic levels,
while the 100H version is compatible with 100K levels (referenced to
+5.0 V).
1
MCxxxH642G
AWLYYWW
Features
• Generates Clocks for 68030/040
• Meets 030/040 Skew Requirements
• TTL or PECL Input Clock
• Extra TTL and PECL Power/Ground Pins
• Asynchronous Reset
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Single +5.0 V Supply
• Pb−Free Packages are Available*
Function
Reset(R): LOW on RESET forces all Q outputs LOW.
Select(SEL): LOW selects the ECL input source (DE/DE). HIGH
selects the TTL input source (DT).
*For additional marking information, refer to
Application Note AND8002/D.
The H642 also contains circuitry to force a stable input state of the
ECL differential input pair, should both sides be left open. In this Case,
the DE side of the input is pulled LOW, and DE goes HIGH.
Power Up: The device is designed to have positive edges of the ÷2
and ÷4 outputs synchronized at Power Up.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 8
MC10H642/D
MC10H642, MC100H642
VT VT Q1
GT GT
22 21
Q0
20
VT
19
TTL Outputs
25
24
23
Q7
Q6
18
17
16
15
14
13
12
Q2 26
GT 27
GT 28
V
BB
DE
DE
VE
R
TTL/ECL Clock Inputs
V
Q5
Q4
Q3
BB
DE
DE
Q3
1
÷4
MUX
VT
VT
2
3
4
DT
GE
DT
SEL
Q2
Q4
5
6
7
8
9
10
11
TTL Control Inputs
Q1
Q0
÷2
Q5
GT GT
Q6 Q7
VT
SEL
Figure 1. Pinout: PLCC−28
R
(Top View)
Figure 2. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Symbol
Description
Pin
Symbol
Description
81
82
83
84
85
86
87
88
89
10
11
12
13
14
Q3
VT
VT
Q4
Q5
GT
GT
Q6
Q7
VT
SEL
DT
GE
R
Signal Output (TTL)**
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VE
DE
DE
BB
VT
Q0
GT
GT
Q1
VT
VT
Q2
GT
GT
ECL V (+5.0 V)
CC
TTL V (+5.0 V)
ECL Signal Input (Non−Inverting)
CC
TTL V (+5.0 V)
ECL Signal Input (Inverting)
CC
Signal Output (TTL)**
Signal Output (TTL)**
TTL Ground (0 V)
V
V
Reference Output
CC
BB
TTL V (+5.0 V)
Signal Output (TTL)*
TTL Ground (0 V)
TTL Ground (0 V)
Signal Output (TTL)*
TTL Ground (0 V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL V (+5.0 V)
TTL V (+5.0 V)
CC
CC
Input Select (TTL)
TTL Signal Input
ECL Ground (0 V)
Reset (TTL)
TTL V (+5.0 V)
CC
Signal Output (TTL)**
TTL Ground (0 V)
TTL Ground (0 V)
* Divide by 2
**Divide by 4
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2
MC10H642, MC100H642
Table 2. 10H PECL CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
T
A
= 0°C
T
A
= 25°C
T = 85°C
A
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Condition
Unit
I
I
Input HIGH Current
Input LOW Current
255
175
175
mA
INH
INL
0.5
0.5
0.5
V
V
Input HIGH Voltage (Note 1)
Input LOW Voltage (Note 1)
V
= 5.0 V
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
3.94
3.05
4.28
V
V
IH
IL
EE
3.555
V
Output Reference Voltage (Note 1)
3.62
3.73
3.65
3.75
3.69
3.81
BB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. PECL LEVELS are referenced to V and will vary 1:1 with the power supply. The VALUES shown are for V = 5.0 V.
CC
CC
Table 3. 100H PECL CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
T
A
= 0°C
T
A
= 25°C
T = 85°C
A
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Condition
Unit
I
I
Input HIGH Current
Input LOW Current
255
175
175
mA
INH
INL
0.5
0.5
0.5
V
V
Input HIGH Voltage (Note 2)
Input LOW Voltage (Note 2)
V
= 5.0 V
EE
3.835
3.190
4.120
3.525
3.835
3.190
4.120
3.525
3.835
3.190
4.120
3.525
V
V
IH
IL
V
Output Reference Voltage (Note 2)
3.620
3.740
3.620
3.740
3.620
3.740
BB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. PECL LEVELS are referenced to V and will vary 1:1 with the power supply. The VALUES shown are for V = 5.0 V.
CC
CC
Table 4. 10H/100H DC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
T
A
= 0°C
T
A
= 25°C
T = 85°C
A
Symbol
Characteristic
Power Supply Current
Condition
Min
Max
Min
Max
Min
Max
Unit
mA
mA
mA
I
PECL
TTL
VE Pin
57
30
30
57
30
30
57
30
30
EE
I
I
Total All VT Pins
CCH
CCL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC10H642, MC100H642
Table 5. 10H/100H TTL DC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
T
A
= 0°C
T
A
= 25°C
T = 85°C
A
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Input HIGH Voltage
Condition
Unit
V
2.0
2.0
2.0
V
IH
IL
V
Input LOW Voltage
0.8
0.8
0.8
I
Input HIGH Current
V
V
= 2.7 V
= 7.0 V
20
100
20
100
20
100
mA
IH
IN
IN
I
Input LOW Current
V
= 0.5 V
−0.6
−0.6
−0.6
mA
V
IL
IN
V
Output HIGH Voltage
I
I
= −3.0 mA
= −15 mA
2.5
2.0
2.5
2.0
2.5
2.0
OH
OH
OH
V
V
Output LOW Voltage
I
I
= 24 mA
0.5
0.5
0.5
V
V
OL
IK
OL
Input Clamp Voltage
= −18 mA
−1.2
−225
−1.2
−225
−1.2
−225
IN
I
Output Short Circuit Current
V
= 0 V
OUT
−100
−100
−100
mA
OS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS (V = V = 5.0 V ± 5%)
T
E
T
A
= 0°C
T = 25°C
A
T = 85°C
A
Symbol
Characteristic
Condition
CL = 25 pF
Min
Max
Min
Max
Min
Max
Unit
t
Propagation Delay
Q2−Q7
C ECL
C TTL
ns
PLH
D to Output
4.70
4.70
5.70
5.70
4.75
4.75
5.75
5.75
4.60
4.50
5.60
5.50
tskpp
Part−to−Part Skew
Within−Device Skew
1.0
0.5
1.0
0.5
1.0
0.5
ns
ns
ns
tskwd*
t
Propagation Delay
D to Output
Q0, Q1
C ECL
C TTL
CL = 25 pF
CL = 25 pF
PLH
4.30
4.30
5.30
5.30
4.50
4.50
5.50
5.50
4.25
4.25
5.25
5.25
tskpp
tskwd
Part−to−Part Skew
All
Outputs
2.0
2.0
2.0
ns
Within−Device Skew
CL = 25 pF
CL = 25 pF
1.0
6.3
1.0
6.0
1.0
6.5
ns
ns
t
Propagation Delay
R to Output
All
Outputs
4.3
4.0
4.5
PD
t
t
Output Rise/Fall Time
0.8 V to 2.0 V
All
Outputs
CL = 25 pF
CL = 25 pF
2.5
2.5
2.5
2.5
2.5
2.5
ns
R
F
f
**
Maximum Input Frequency
Reset Pulse Width
100
1.5
100
1.5
100
1.5
MHz
ns
MAX
RPW
RRT
Reset Recovery Time
1.25
1.25
1.25
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
* Within−Device Skew defined as identical transactions on similar paths through a device.
**MAX Frequency is 135 MHz.
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4
MC10H642, MC100H642
10/100H642 − DUTY CYCLE CONTROL
To maintain a duty cycle of ±5% at 50 MHz, limit the load capacitance and/or power supply variation as shown in Figures
1 and 2. For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature.
Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up.
Best duty cycle control is obtained with a single mP load and minimum line length.
11
11
4.75
10
4.75
10
5.00
5.25
5.00
5.25
9
0
10
20
30
40
50
60
9
0
10
20
30
40
50
60
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 3. MC10H642 Positive PW versus Load
Figure 4. MC10H642 Negative PW versus Load
@ ±5% VCC, TA = 25°C
@ ±5% VCC, TA = 25°C
10.8
10.6
10.4
10.2
10.0
9.8
10.6
10.4
10.2
10.0
9.8
4.875
5.00
4.875
5.00
5.125
5.125
9.6
9.6
9.4
9.4
9.2
0
10
20
30
40
50
60
0
10
20 30
CAPACITIVE LOAD (pF)
40
50
60
CAPACITIVE LOAD (pF)
Figure 6. MC10H642 Negative PW versus Load
Figure 5. MC10H642 Positive PW versus Load
@ ±2.5% VCC, TA = 25°C
@ ±2.5% VCC, TA = 25°C
10.5
10.4
10.2
10.0
9.8
10.3
10.1
9.9
0 pF
0 pF
25 pF
50 pF
25 pF
50 pF
9.7
9.6
9.5
9.4
0
20
40
60
80
100
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. MC10H642 Positive PW versus Temperature,
CC = 5.0 V
Figure 8. MC10H642 Negative PW versus
Temperature, VCC = 5.0 V
V
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5
MC10H642, MC100H642
6.2
6.0
5.8
5.6
5.4
5.2
4.75
5.00
5.25
0
10
20
30
40
50
60
CAPACITIVE (pF)
Figure 9. MC10H642 + Tpd versus Load, VCC ±5%, TA = 25°C
(Overshoot at 50 MHz with no load makes graph non linear)
DT
RESET, R
R
t
rec
R
t
pw
Q0
Q2
Q1
Q7
MC10/100H642
Figure 10. Clock Phase and Reset Recovery Time After Reset Pulse
MC10/100H642
D
in
Q0.Q1
Q4 & Q5
Q2
Q7
After Power Up
Figure 11.
Outputs
Q2
Q7 will Synchronize with Pos Edges of Din & Q0
Q1
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6
MC10H642, MC100H642
Switching Circuit PECL:
PECL
USE 0.1 mF CAPACITORS
V
EE
V
& V
CCO
CC
TTL
FOR DECOUPLING.
+7 V
OPEN
50 W COAX
DEVICE
UNDER
TEST
IN
OUT
ALL
OTHERS
PULSE
GENERATOR
450 W
t , t
PZL PLZ
R1
500 W
DEVICE
UNDER
TEST
R2
500 W
50 pF
CH A
CH B
USE OSCILLOSCOPE
INTERNAL 50 W LOAD
FOR TERMINATION.
OSCILLOSCOPE
Figure 12. Switching Circuit and Waveforms
PECL/TTL
PECL/TTL
50%/1.5 V
V
in
80%/2.0 V
20%/0.8 V
V
out
T
T
pd−−
pd++
50%/1.5 V
T
rise
T
fall
V
out
Figure 14. Waveforms: Rise and Fall Times
Figure 13. Propagation Delay — Single−Ended
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7
MC10H642, MC100H642
ORDERING INFORMATION
Device
†
Package
Shipping
MC10H642FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10H642FNG
PLCC−28
(Pb−Free)
MC10H642FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10H642FNR2G
PLCC−28
(Pb−Free)
MC100H642FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100H642FNG
PLCC−28
(Pb−Free)
MC100H642FNR2
MC100H642FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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8
MC10H642, MC100H642
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
0.007 (0.180)
T
L−M
N
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T
L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T
L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L−M
L−M
N
M
S
S
N
0.007 (0.180)
T
L−M
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T
L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T
L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
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9
MC10H642, MC100H642
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
MECL 10H is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC10H642/D
相关型号：
MC10H643FN
10H SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLATIC, LCC-28
ROCHESTER
MC10H643FNG
10H SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD FREE, PLATIC, LCC-28
ROCHESTER
MC10H643FNR2
10H SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLATIC, LCC-28
ROCHESTER
MC10H643FNR2G
10H SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, LEAD FREE, PLATIC, LCC-28
ROCHESTER
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