MC10EP33DTG [ONSEMI]
3.3V / 5V ECL ±4 Divider; 3.3V / 5V ECL ± 4分频器型号: | MC10EP33DTG |
厂家: | ONSEMI |
描述: | 3.3V / 5V ECL ±4 Divider |
文件: | 总11页 (文件大小:165K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC10EP33, MC100EP33
3.3V / 5VꢀECL B4 Divider
Description
The MC10/100EP33 is an integrated B4 divider. The differential
clock inputs.
The V pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
BB
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differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
MARKING
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
DIAGRAMS*
CC
to 0.5 mA. When not used, V should be left open.
BB
The reset pin is asynchronous and is asserted on the rising edge.
Upon powerup, the internal flip−flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
The 100 Series contains temperature compensation.
8
1
8
8
HEP33
ALYW
KEP33
ALYW
G
1
G
SOIC−8
D SUFFIX
CASE 751
1
Features
• 320 ps Propagation Delay
• Maximum Frequency > 4 GHz Typical
8
1
8
1
8
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
1
HP33
KP33
with V = 0 V
ALYWG
ALYWG
EE
TSSOP−8
DT SUFFIX
CASE 948R
G
G
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −5.5 V
EE
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V
EE
• V Output
• Pb−Free Packages are Available
BB
1
4
1
4
DFN8
MN SUFFIX
CASE 506AA
H
K
= MC10
= MC100
A
L
= Assembly Location
= Wafer Lot
5Q = MC10
3L = MC100
Y
W
M
G
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 9
MC10EP33/D
MC10EP33, MC100EP33
Table 1. PIN DESCRIPTION
PIN
FUNCTION
ECL Clock Inputs
RESET
CLK
1
2
8
7
V
CC
CLK*, CLK*
Reset*
R
ECL Asynchronous Reset
Reference Voltage Output
ECL Data Outputs
V
BB
Q
Q
Q, Q
V
CC
Positive Supply
B4
V
EE
Negative Supply
CLK
3
4
6
5
EP
Exposed pad must be connected to a
sufficient thermal conduit. Electrically
connect to the most negative supply or
leave floating open.
V
BB
V
EE
*
Pins will default LOW when left open.
Table 2. TRUTH TABLE
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
CLK
CLK
RESET
Q
Q
X
Z
X
Z
Z
L
L
F
H
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
CLK
t
RR
RESET
Q
Figure 2. Timing Diagram
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
NA
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL−94 V−0 @ 0.125 in
91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC10EP33, MC100EP33
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
6
EE
= 0 V
−6
V
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
−6
V
V
EE
I
CC
V ꢁ V
CC
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
BB
Sink/Source
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
JA
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
41 to 44
°C/W
JC
JA
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
265
°C/W
°C
JC
T
sol
Wave Solder
<2 to 3 sec @ 248°C
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
JA
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. 10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Min
Typ
26
Max
40
Min
18
Max
40
Min
18
Max
40
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
18
26
26
V
V
V
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
2165
1365
2090
1365
1790
2.0
2290
1490
2415
1615
2415
1690
1990
3.3
2230
1430
2155
1430
1855
2.0
2355
1555
2480
1680
2480
1755
2055
3.3
2290
1490
2215
1490
1915
2.0
2415
1615
2540
1740
2540
1815
2115
3.3
OH
OL
IH
IL
1890
1955
2015
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 4)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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3
MC10EP33, MC100EP33
Table 6. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Min
Typ
26
Max
40
Min
18
Max
40
Min
18
Max
40
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
18
26
26
V
V
V
V
V
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3865
3065
3790
3065
3490
2.0
3990
3190
4115
3315
4115
3390
3690
5.0
3930
3130
3855
3130
3555
2.0
4055
3255
4180
3380
4180
3455
3755
5.0
3990
3190
3915
3190
3615
2.0
4115
3315
4240
3440
4240
3515
3815
5.0
OH
OL
IH
IL
3590
3655
3715
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 7)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
6. All loading with 50 W to V − 2.0 V.
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 7. 10EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 8)
CC
EE
−40°C
25°C
Typ
26
85°C
Typ
26
Min
18
Typ
Max
Min
Max
Min
Max
40
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
EE
26
40
18
40
18
VOH
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
V
V
V
V
V
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV
OL
−1210
−1935
−885 −1145
−1610 −1870
−820 −1085
−1545 −1810
−760
mV
IH
−1485 mV
IL
−1510 −1410 −1310 −1445 −1345 −1245 −1385 −1285 −1185 mV
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
.
CC
9. All loading with 50 W to V − 2.0 V.
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC10EP33, MC100EP33
Table 8. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 11)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Min
18
Typ
26
Max
40
Min
23
Max
45
Min
23
Max
45
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
26
26
V
V
V
V
V
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
2155
1355
2075
1355
1775
2.0
2280
1480
2405
1605
2420
1675
1975
3.3
OH
OL
IH
IL
1875
1875
1875
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
12.All loading with 50 W to V − 2.0 V.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 9. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 14)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Min
18
Typ
26
Max
40
Min
23
Max
45
Min
23
Max
45
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
V
I
EE
26
26
V
V
V
V
V
V
Output HIGH Voltage (Note 15)
Output LOW Voltage (Note 15)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
3855
3055
3775
3055
3475
2.0
3980
3180
4105
3305
4120
3375
3675
5.0
OH
OL
IH
IL
3575
3575
3575
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
15.All loading with 50 W to V − 2.0 V.
CC
16.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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5
MC10EP33, MC100EP33
Table 10. 100EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 17)
CC
EE
−40°C
Typ
26
25°C
Typ
26
85°C
Typ
26
Min
Max
40
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
EE
18
23
45
23
45
V
V
V
V
V
V
Output HIGH Voltage (Note 18)
Output LOW Voltage (Note 18)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
OH
OL
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
mV
IH
−1625 mV
IL
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
.
CC
18.All loading with 50 W to V − 2.0 V.
CC
19.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 11. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 20)
CC
EE
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
OPP
Output Voltage Amplitude
(See Figure 3)
mV
f
in
f
in
< 4.0 GHz
< 4.5 GHz
700
600
700
600
700
600
t
t
,
Propagation Delay to
Output Differential
CLK/Q
RESET/Q
300
370
380
420
440
470
300
370
380
420
440
470
320
400
400
450
460
500
ps
PLH
PHL
t
t
t
Set/Rest Recovery
150
550
100
480
0.2
200
550
100
480
0.2
200
550
100
480
0.2
ps
ps
RR
Minimum Pulse width
Random Clock Jitter (RMS)
RESET
PW
2
2
2
ps
JITTER
V
Input Voltage Swing
150
90
800
1200
150
100
800
1200
150
120
800
1200
mV
PP
(Differential Configuration)
t
r
t
f
Output Rise/Fall Times
(20% − 80%)
Q, Q
170
200
180
250
200
280
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
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6
MC10EP33, MC100EP33
900
800
700
600
500
400
300
200
100
0
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
f , INPUT FREQUENCY (MHz)
in
Figure 3. Input Frequency (fin) versus Output Voltage (VOPP
)
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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7
MC10EP33, MC100EP33
ORDERING INFORMATION
Device
†
Package
Shipping
MC10EP33D
SOIC−8
98 Units / Rail
98 Units / Rail
MC10EP33DG
SOIC−8
(Pb−Free)
MC10EP33DR2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
MC10EP33DR2G
SOIC−8
(Pb−Free)
MC10EP33DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC10EP33DTG
TSSOP−8
(Pb−Free)
MC10EP33DTR2
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
MC10EP33DTR2G
TSSOP−8
(Pb−Free)
MC10EP33MNR4
MC10EP33MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
MC100EP33D
SOIC−8
98 Units / Rail
98 Units / Rail
MC100EP33DG
SOIC−8
(Pb−Free)
MC100EP33DR2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
MC100EP33DR2G
SOIC−8
(Pb−Free)
MC100EP33DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC100EP33DTG
TSSOP−8
(Pb−Free)
MC100EP33DTR2
MC100EP33DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100EP33MNR4
MC100EP33MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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8
MC10EP33, MC100EP33
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MC10EP33, MC100EP33
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
http://onsemi.com
10
MC10EP33, MC100EP33
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
8 X b
0.05
C
NOTE 3
BOTTOM VIEW
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ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC10EP33/D
相关型号:
MC10EP35DG
10E SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, LEAD FREE, SOIC-8
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