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MC10231_02 [ONSEMI]

High Speed Dual Type D Master-Slave Flip-Flop; 高速双D型主从触发器
MC10231_02
型号： MC10231_02
厂家： ONSEMI    ONSEMI
描述：

High Speed Dual Type D Master-Slave Flip-Flop
高速双D型主从触发器

触发器
文件： 总8页 (文件大小：113K)
中文：  中文翻译
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MC10231  
High Speed Dual Type D  
Master-Slave Flip-Flop  
The MC10231 is a dual master–slave type D flip–flop.  
Asynchronous Set (S) and Reset (R) override Clock (C ) and Clock  
C
Enable (C ) inputs. Each flip–flop may be clocked separately by  
E
http://onsemi.com  
holding the common clock in the low state and using the enable inputs  
for the clocking function. If the common clock is to be used to clock  
the flip–flop, the Clock Enable inputs must be in the low state. In this  
case, the enable inputs perform the function of controlling the  
common clock.  
The output states of the flip–flop change on the positive transition of  
the clock. A change in the information present at the data (D) input  
will not affect the output information at any other time due to  
master–slave construction.  
MARKING  
DIAGRAMS  
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10231L  
AWLYYWW  
1
16  
• P = 270 mW typ/pkg (No Load)  
PDIP–16  
P SUFFIX  
CASE 648  
D
MC10231P  
AWLYYWW  
• t = 2 ns typ  
pd  
• t = 225 MHz typ  
Tog  
1
1
• t , t = 2.0 ns typ (20%–80%)  
r
f
PLCC–20  
FN SUFFIX  
CASE 775  
LOGIC DIAGRAM  
10231  
AWLYYWW  
S1  
D1  
5
7
6
2
3
Q1  
Q1  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
C
E1  
WW = Work Week  
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
R1  
4
9
C
C
CC2  
DIP PIN ASSIGNMENT  
V
R2 13  
EE  
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC2  
CC1  
15  
14  
Q2  
Q2  
Q1  
Q2  
Q2  
R2  
S2  
C
C 11  
E2  
D2 10  
Q1  
R1  
S1  
S2 12  
CLOCKED TRUTH TABLE  
R–S TRUTH TABLE  
C
E2  
E1  
C
L
D
X
L
Q
R
L
S
L
Q
n+1  
n+1  
D2  
D1  
Q
Q
n
n
V
C
C
EE  
H
H
L
L
H
L
H
H
H
H
L
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables  
on page 18 of the ON Semiconductor MECL Data Book  
(DL122/D).  
C = C + C . A clock H is a clock  
transition from a low to a high state.  
H
H
N.D.  
E
C
N.D. = Not Defined  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10231L  
CDIP–16  
25 Units / Rail  
MC10231P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
MC10231FN  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10231/D  
MC10231  
ELECTRICAL CHARACTERISTICS  
Test Limits  
+25°C  
Typ  
Pin  
Under  
Test  
–30°C  
Max  
72  
+85°C  
Min  
Min  
Max  
Min  
Max  
Characteristic  
Power Supply Drain Current  
Input Current  
Symbol  
Unit  
mAdc  
µAdc  
I
E
8
52  
65  
72  
I
4
5
6
7
9
650  
650  
350  
350  
460  
410  
410  
220  
220  
290  
410  
410  
220  
220  
290  
inH  
I
4, 5*  
6, 7, 9*  
0.5  
0.5  
µAdc  
Vdc  
Vdc  
Vdc  
Vdc  
ns  
inL  
Output Voltage  
Logic 1  
Logic 0  
Logic 1  
Logic 0  
V
2
2[  
–1.060  
–1.060  
–0.890  
–0.890  
–0.960  
–0.960  
–0.810  
–0.810  
–0.890  
–0.890  
–0.700  
–0.700  
OH  
Output Voltage  
V
3
3[  
–1.890  
–1.890  
–1.675  
–1.675  
–1.850  
–1.850  
–1.650  
–1.650  
–1.825  
–1.825  
–1.615  
–1.615  
OL  
Threshold Voltage  
Threshold Voltage  
V
OHA  
2
2[  
–1.080  
–1.080  
–0.980  
–0.980  
–0.910  
–0.910  
V
OLA  
3
3[  
–1.655  
–1.655  
–1.630  
–1.630  
–1.595  
–1.595  
Switching Times (50Ω Load)  
Clock Input  
Propagation Delay  
t
t
2
2
1.5  
1.5  
3.4  
3.4  
1.5  
1.5  
2.0  
2.0  
3.3  
3.3  
1.6  
1.6  
3.7  
3.7  
9+2–  
6+2+  
Rise Time  
Fall Time  
Set Input  
(20 to 80%)  
(20 to 80%)  
t
2
2
0.9  
0.9  
3.3  
3.3  
1.0  
1.0  
1.3  
1.3  
3.1  
3.1  
1.0  
1.0  
3.6  
3.6  
2+  
t
2–  
ns  
ns  
Propagation Delay  
t
2
15  
3
1.1  
1.1  
1.1  
1.1  
3.4  
3.4  
3.4  
3.4  
1.1  
1.1  
1.1  
1.1  
2.0  
2.0  
2.0  
2.0  
3.3  
3.3  
3.3  
3.3  
1.2  
1.2  
1.2  
1.2  
3.7  
3.7  
3.7  
3.7  
5+2+  
t
t
12+15+  
t
5+3–  
12+14–  
14  
Reset Input  
Propagation Delay  
t
2
15  
3
1.1  
1.1  
1.1  
1.1  
3.4  
3.4  
3.4  
3.4  
1.1  
1.1  
1.1  
1.1  
2.0  
2.0  
2.0  
2.0  
3.3  
3.3  
3.3  
3.3  
1.2  
1.2  
1.2  
1.2  
3.7  
3.7  
3.7  
3.7  
4+2–  
t
t
13+15–  
t
4+3–  
13+14+  
14  
Setup Time  
t
7
7
2
1.5  
0.9  
200  
1.0  
0.75  
200  
1.5  
0.9  
200  
ns  
ns  
setup  
Hold Time  
t
hold  
Toggle Frequency (Max)  
f
225  
MHz  
tog  
* Individually test each input; apply V  
to pin under test.  
ILmin  
V
IHmax  
[ Output level to be measured after a clock pulse has been applied to the C Input (Pin 6)  
E
V
ILmin  
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2
MC10231  
ELECTRICAL CHARACTERISTICS (continued)  
TEST VOLTAGE VALUES (Volts)  
@ Test Temperature  
V
IHmax  
V
ILmin  
V
V
V
EE  
IHAmin  
ILAmax  
–30°C  
+25°C  
+85°C  
–0.890  
–0.810  
–0.700  
–1.890  
–1.850  
–1.825  
–1.205  
–1.105  
–1.035  
–1.500  
–1.475  
–1.440  
–5.2  
–5.2  
–5.2  
Pin  
Under  
Test  
TEST VOLTAGE APPLIED TO PINS LISTED BELOW  
(V  
Gnd  
)
CC  
Characteristic  
Power Supply Drain Current  
Input Current  
Symbol  
V
V
ILmin  
V
V
V
EE  
IHmax  
IHAmin  
ILAmax  
I
E
8
8
1, 16  
I
4
5
6
7
9
4
5
6
7
9
8
8
8
8
8
1, 16  
1, 16  
1, 16  
1, 16  
1, 16  
inH  
I
inL  
4, 5*  
6, 7, 9*  
*
*
8
8
1, 16  
1, 16  
Output Voltage  
Logic 1  
Logic 0  
Logic 1  
Logic 0  
V
2
2[  
5
7
8
8
1, 16  
1, 16  
OH  
Output Voltage  
V
3
3[  
5
7
8
8
1, 16  
1, 16  
OL  
Threshold Voltage  
Threshold Voltage  
V
OHA  
2
2[  
5
7
8
8
1, 16  
1, 16  
9
9
V
OLA  
3
3[  
5
7
8
8
1, 16  
1, 16  
Switching Times  
Clock Input  
(50Ω Load)  
+1.11Vdc  
Pulse In  
Pulse Out  
–3.2 V  
+2.0 V  
Propagation Delay  
t
t
2
2
9
6
2
2
8
8
1, 16  
1, 16  
9+2–  
6+2+  
7
7
Rise Time  
Fall Time  
Set Input  
(20 to 80%)  
(20 to 80%)  
t
2+  
2
2
9
9
2
2
8
8
1, 16  
1, 16  
t
2–  
Propagation Delay  
t
2
15  
3
5
12  
5
2
15  
3
8
8
8
8
1, 16  
1, 16  
1, 16  
1, 16  
5+2+  
t
t
6
9
12+15+  
t
5+3–  
12+14–  
14  
12  
14  
Reset Input  
Propagation Delay  
t
2
15  
3
4
13  
4
2
15  
3
8
8
8
8
1, 16  
1, 16  
1, 16  
1, 16  
4+2–  
t
t
6
9
13+15–  
t
4+3–  
13+14+  
14  
13  
14  
Setup Time  
Hold Time  
t
7
7
2
6, 7  
6, 7  
6
2
2
2
8
8
8
1, 16  
1, 16  
1, 16  
setup  
t
hold  
Toggle Frequency (Max)  
f
* *  
tog  
* Individually test each input applying V or V to input under test.  
IH  
IL  
V
V
IHmax  
[ Output level to be measured after a clock pulse has been applied to the C Input (Pin 6)  
E
ILmin  
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been  
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.  
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the  
same manner.  
http://onsemi.com  
3
MC10231  
PACKAGE DIMENSIONS  
PLCC–20  
FN SUFFIX  
PLASTIC PLCC PACKAGE  
CASE 775–02  
ISSUE C  
M
S
S
0.007 (0.180)  
T
L-M  
N
B
Y BRK  
–M–  
–N–  
M
S
S
N
0.007 (0.180)  
T
L-M  
U
D
D
–L–  
Z
W
20  
1
S
S
S
0.010 (0.250)  
T
L-M  
N
G1  
X
V
A
VIEW D–D  
M
M
S
S
S
S
0.007 (0.180)  
0.007 (0.180)  
T
L-M  
L-M  
N
N
M
S
S
N
0.007 (0.180)  
T
L-M  
H
Z
T
R
K1  
K
C
E
M
S
S
N
0.007 (0.180)  
T
L-M  
F
0.004 (0.100)  
VIEW S  
G
–T– SEATING  
PLANE  
J
VIEW S  
NOTES:  
INCHES  
MILLIMETERS  
G1  
1. DATUMS -L-, -M-, AND -N- DETERMINED  
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC  
BODY AT MOLD PARTING LINE.  
2. DIMENSION G1, TRUE POSITION TO BE  
MEASURED AT DATUM -T-, SEATING PLANE.  
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD  
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)  
PER SIDE.  
DIM MIN  
MAX  
0.395  
0.395  
0.180  
0.110  
0.019  
MIN  
9.78  
9.78  
4.20  
2.29  
0.33  
MAX  
10.03  
10.03  
4.57  
S
S
S
0.010 (0.250)  
T
L-M  
N
A
B
C
E
F
0.385  
0.385  
0.165  
0.090  
0.013  
2.79  
0.48  
G
H
J
0.050 BSC  
1.27 BSC  
4. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
5. CONTROLLING DIMENSION: INCH.  
0.026  
0.020  
0.025  
0.350  
0.350  
0.042  
0.042  
0.042  
---  
0.032  
---  
---  
0.66  
0.51  
0.64  
8.89  
8.89  
1.07  
1.07  
1.07  
---  
2
0.81  
---  
---  
9.04  
9.04  
1.21  
1.21  
1.42  
0.50  
10  
K
R
U
V
W
X
Y
Z
6. THE PACKAGE TOP MAY BE SMALLER THAN THE  
PACKAGE BOTTOM BY UP TO 0.012 (0.300).  
DIMENSIONS R AND U ARE DETERMINED AT THE  
OUTERMOST EXTREMES OF THE PLASTIC BODY  
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,  
GATE BURRS AND INTERLEAD FLASH, BUT  
INCLUDING ANY MISMATCH BETWEEN THE TOP  
AND BOTTOM OF THE PLASTIC BODY.  
7. DIMENSION H DOES NOT INCLUDE DAMBAR  
PROTRUSION OR INTRUSION. THE DAMBAR  
PROTRUSION(S) SHALL NOT CAUSE THE H  
DIMENSION TO BE GREATER THAN 0.037 (0.940).  
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE  
THE H DIMENSION TO BE SMALLER THAN 0.025  
(0.635).  
0.356  
0.356  
0.048  
0.048  
0.056  
0.020  
10  
2
_
_
_
_
G1 0.310  
K1 0.040  
0.330  
---  
7.88  
1.02  
8.38  
---  
http://onsemi.com  
4
MC10231  
PACKAGE DIMENSIONS  
CDIP–16  
L SUFFIX  
CERAMIC DIP PACKAGE  
CASE 620–10  
ISSUE T  
–A–  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEAD WHEN  
FORMED PARALLEL.  
4. DIMENSION F MAY NARROW TO 0.76 (0.030)  
WHERE THE LEAD ENTERS THE CERAMIC  
BODY.  
16  
1
9
8
–B–  
C
L
INCHES  
DIM MIN MAX  
MILLIMETERS  
MIN  
19.05  
6.10  
---  
MAX  
19.93  
7.49  
5.08  
0.50  
A
B
C
D
E
F
0.750  
0.240  
---  
0.785  
0.295  
0.200  
0.020  
–T–  
SEATING  
PLANE  
0.015  
0.39  
K
N
0.050 BSC  
1.27 BSC  
0.055  
0.065  
1.40  
1.65  
G
H
K
L
0.100 BSC  
2.54 BSC  
M
E
0.008  
0.125  
0.015  
0.170  
0.21  
3.18  
0.38  
4.31  
F
J
16 PL  
G
0.300 BSC  
7.62 BSC  
M
S
T B  
0.25 (0.010)  
M
N
0
0.020  
15  
0.040  
0
_
0.51  
15  
_
1.01  
D 16 PL  
_
_
M
S
T A  
0.25 (0.010)  
PDIP–16  
P SUFFIX  
PLASTIC DIP PACKAGE  
CASE 648–08  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEADS WHEN  
FORMED PARALLEL.  
–A–  
ISSUE R  
16  
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.  
5. ROUNDED CORNERS OPTIONAL.  
INCHES  
DIM MIN MAX  
MILLIMETERS  
MIN  
18.80  
6.35  
3.69  
0.39  
1.02  
MAX  
19.55  
6.85  
4.44  
0.53  
1.77  
F
A
B
C
D
F
0.740  
0.250  
0.145  
0.015  
0.040  
0.770  
0.270  
0.175  
0.021  
0.70  
C
L
SEATING  
PLANE  
–T–  
G
H
J
0.100 BSC  
0.050 BSC  
2.54 BSC  
1.27 BSC  
K
M
0.008  
0.015  
0.130  
0.305  
10  
0.21  
0.38  
3.30  
7.74  
10  
H
J
K
L
0.110  
0.295  
0
2.80  
7.50  
0
G
D 16 PL  
M
S
_
_
_
_
0.020  
0.040  
0.51  
1.01  
M
M
0.25 (0.010)  
T A  
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5
MC10231  
Notes  
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6
MC10231  
Notes  
http://onsemi.com  
7
MC10231  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes  
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular  
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,  
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be  
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.  
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or  
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold  
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable  
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim  
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.  
PUBLICATION ORDERING INFORMATION  
Literature Fulfillment:  
JAPAN: ON Semiconductor, Japan Customer Focus Center  
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031  
Phone: 81–3–5740–2700  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada  
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada  
Email: ONlit@hibbertco.com  
Email: r14525@onsemi.com  
ON Semiconductor Website: http://onsemi.com  
For additional information, please contact your local  
Sales Representative.  
N. American Technical Support: 800–282–9855 Toll Free USA/Canada  
MC10231/D  

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OHMITE

MC102421075FE

 Fixed Resistor, Metal Glaze/thick Film, 1.5W, 10700000ohm, 5000V, 1% +/-Tol, 50ppm/Cel, 5025
OHMITE

MC102421076FE

 Fixed Resistor, Metal Glaze/thick Film, 1.5W, 107000000ohm, 5000V, 1% +/-Tol, 50ppm/Cel, 5025
OHMITE

MC102421101FE

 Fixed Resistor, Metal Glaze/thick Film, 1.5W, 1100ohm, 5000V, 1% +/-Tol, 50ppm/Cel, 5025
OHMITE
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