MC10124FN [ONSEMI]
Quad TTL to MECL Translator; 四TTL至MECL翻译
| 型号： | MC10124FN |
| 厂家： | 
ONSEMI |
| 描述： | Quad TTL to MECL Translator |
| 文件： | 总8页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10124
Quad TTL to MECL
Translator
The MC10124 is a quad translator for interfacing data and control
signals between a saturated logic section and the MECL section of
digital systems. The MC10124 has TTL compatible inputs, and
MECL complementary open–emitter outputs that allow use as an
inverting/ non–inverting translator or as a differential line driver.
When the common strobe input is at the low logic level, it forces all
true outputs to a MECL low logic state and all inverting outputs to a
MECL high logic state.
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MARKING
DIAGRAMS
16
Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.
Propagation delay of the MC10124 is typically 3.5 ns. The dc levels
are standard or Schottky TTL in, MECL 10,000 out.
CDIP–16
L SUFFIX
CASE 620
MC10124L
AWLYYWW
1
An advantage of this device is that TTL level information can be
transmitted differentially, via balanced twisted pair lines, to the MECL
equipment, where the signal can be received by the MC10115 or
MC10116 differential line receivers. The MC10124 is useful in
computers, instrumentation, peripheral controllers, test equipment,
and digital communications systems.
16
PDIP–16
P SUFFIX
CASE 648
MC10124P
AWLYYWW
1
1
• P = 380 mW typ/pkg (No Load)
D
• t = 3.5 ns typ (+ 1.5 Vdc in to 50% out)
pd
PLCC–20
FN SUFFIX
CASE 775
10124
• t , t = 2.5 ns typ (20%–80%)
r
f
AWLYYWW
LOGIC DIAGRAM
5
6
4
2
A
= Assembly Location
7
10
11
3
1
WL = Wafer Lot
YY = Year
WW = Work Week
12
15
ORDERING INFORMATION
13
14
Device
Package
Shipping
Gnd
V
=
=
=
PIN 16
(+5.0Vdc)
(-5.2Vdc)
PIN 9
PIN 8
MC10124L
CDIP–16
25 Units / Rail
CC
V
EE
MC10124P
PDIP–16
PLCC–20
25 Units / Rail
46 Units / Rail
DIP PIN ASSIGNMENT
MC10124FN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
GND
OUT
OUT
OUT
OUT
C
OUT
A
B
A
D
D
C
D
C
V
OUT
OUT
OUT
IN
A
IN
COMMON
STROBE
B
IN
IN
V
CC
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
January, 2002 – Rev. 7
MC10124/D
MC10124
ELECTRICAL CHARACTERISTICS
Test Limits
+25°C
Pin
Under
Test
–30°C
+85°C
Min
Max
Min
Typ
Max
Min
Max
Characteristic
Symbol
Unit
Negative Power Supply
Drain Current
I
E
8
72
66
72
mAdc
I
9
9
16
25
16
25
18
25
mAdc
mAdc
µAdc
Positive Power Supply
Drain Current
CCH
I
CCL
Reverse Current
I
R
6
7
200
50
200
50
200
50
Forward Current
I
6
7
–12.8
–3.2
–12.8
–3.2
–12.8
–3.2
mAdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
ns
F
Input Breakdown Voltage
Clamp Input Voltage
High Output Voltage
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
BV
6
7
5.5
5.5
5.5
5.5
5.5
5.5
in
V
6
7
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
I
V
OH
1
3
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
V
OL
1
3
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
V
1
3
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
OHA
V
1
3
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
OLA
Switching Times
Load)
(50Ω
Propagation Delay
t
t
1
1
1
1
3
3
1.5
1.0
1.5
1.0
1.5
1.0
6.8
6.0
6.8
6.0
6.8
6.0
1.0
1.0
1.0
1.0
1.0
1.0
3.5
3.5
3.5
3.5
3.5
3.5
6.0
6.0
6.0
6.0
6.0
6.0
1.0
1.5
1.0
1.5
1.0
1.5
6.0
6.8
6.0
6.8
6.0
6.8
6+1+
1
(+3.5Vdc to 50%)
6–1–
t
7+1+
t
t
t
7–1–
7+3–
7–3+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
1
1
1.0
1.0
4.2
4.2
1.1
1.1
2.5
2.5
3.9
3.9
1.1
1.1
4.3
4.3
1+
t
1–
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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2
MC10124
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
–30°C
V
V
V
V
V
F
IH
ILmax
IHA’
ILA’
+4.0
+4.0
+4.0
+0.40
+0.40
+0.40
+2.00
+1.80
+1.80
+1.10
+1.10
+0.90
+0.40
+0.40
+0.40
+25°C
+85°C
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic
Symbol
Test
V
IH
V
ILmax
V
IHA’
V
ILA’
V
F
Gnd
Negative Power Supply Drain
Current
I
E
8
16
I
9
9
5,6,7,10,11
16
Positive Power Supply Drain
Current
CCH
5,6,7,10,11,16
I
CCL
Reverse Current
I
R
6
7
5,7,10,11
6
16
16
Forward Current
I
F
6
7
5,7,10,11
6
6
7
16
16
Input Breakdown Voltage
Clamp Input Voltage
High Output Voltage
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
BV
6
7
5,7,10,11,16
6,16
in
V
I
6
7
16
16
V
OH
1
3
6,7
6,7
16
16
6,7
6,7
V
OL
1
3
16
16
V
OHA
1
3
6
6
7
7
16
16
7
7
V
OLA
1
3
6
6
16
16
Switching Times
(50Ω Load)
+6.0 V
Pulse In Pulse Out
+2.0 V
Propagation Delay
t
t
1
1
1
1
3
3
7
7
6
6
6
6
6
6
7
7
7
7
1
1
1
1
3
3
16
16
16
16
16
16
6+1+
1
(+3.5Vdc to 50%)
6–1–
t
7+1+
t
t
t
7–1–
7+3–
7–3+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
1
1
6
6
7
7
1
1
16
16
1+
t
1–
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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3
MC10124
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
(mA)
@ Test Temperature
V
R
V
CC
V
EE
I
I
I
in
–30°C
+25°C
+85°C
+2.40
+2.40
+2.40
+5.00
+5.00
+5.00
–5.2
–5.2
–5.2
–10
–10
–10
+1.0
+1.0
+1.0
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic
Symbol
V
R
V
CC
V
EE
I
I
I
in
Gnd
Negative Power Supply Drain
Current
I
E
8
9
8
16
I
9
9
9
9
8
8
16
Positive Power Supply Drain
Current
CCH
5,6,7,10,11,16
I
CCL
Reverse Current
I
R
6
7
6
7
9
9
8
8
16
16
Forward Current
I
F
6
7
9
9
8
8
16
16
Input Breakdown Voltage
Clamp Input Voltage
High Output Voltage
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
BV
6
7
9
9
8
8
6
7
5,7,10,11,16
6,16
in
V
I
6
7
9
9
8
8
6
7
16
16
V
OH
1
3
9
9
8
8
16
16
V
OL
1
3
9
9
8
8
16
16
V
OHA
1
3
9
9
8
8
16
16
V
OLA
1
3
9
9
8
8
16
16
Switching Times
(50Ω Load)
+7.0 V
–3.2 V
+2.0 V
Propagation Delay
t
t
1
1
1
1
3
3
9
9
9
9
9
9
8
8
8
8
8
8
16
16
16
16
16
16
6+1+
1
(+3.5Vdc to 50%)
6–1–
t
7+1+
t
t
t
7–1–
7+3–
7–3+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
1
1
9
9
8
8
16
16
1+
t
1–
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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4
MC10124
SWITCHING TIME TEST CIRCUIT
V
out
NAND
V
out
AND
V
in
+6.0 Vdc
V
CC
+7.0 Vdc
Coax
0.1 µF
25 µF
0.1 µF
Coax
Coax
5
6
7
4
2
Input
3
1
Pulse Generator
10
11
12
15
Unused outputs connected to a
50-ohm resistor to ground.
13
14
Input Pulse
t+ = t- = 5.5 ±0.5 ns
(10 to 90%)
16
8
0.1 µF
25 µF
0.1 µF
50-ohm termination to ground lo-
cated in each scope channel input.
-3.2 Vdc
+ 2.0 Vdc
V
EE
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TP to input pin and
in
TP to output pin.
out
NOTE: All power supply and logic levels are shown
shifted 2 volts positive.
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5
MC10124
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
M
S
S
0.007 (0.180)
T
L-M
N
B
Y BRK
–M–
–N–
M
S
S
N
0.007 (0.180)
T
L-M
U
D
D
–L–
Z
W
20
1
S
S
S
0.010 (0.250)
T
L-M
N
G1
X
V
A
VIEW D–D
M
M
S
S
S
S
0.007 (0.180)
0.007 (0.180)
T
L-M
L-M
N
N
M
S
S
N
0.007 (0.180)
T
L-M
H
Z
T
R
K1
K
C
E
M
S
S
N
0.007 (0.180)
T
L-M
F
0.004 (0.100)
VIEW S
G
–T– SEATING
PLANE
J
VIEW S
NOTES:
INCHES
MILLIMETERS
G1
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
DIM MIN
MAX
0.395
0.395
0.180
0.110
0.019
MIN
9.78
9.78
4.20
2.29
0.33
MAX
10.03
10.03
4.57
2.79
0.48
S
S
S
0.010 (0.250)
T
L-M
N
A
B
C
E
F
0.385
0.385
0.165
0.090
0.013
G
H
J
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
0.026
0.020
0.025
0.350
0.350
0.042
0.042
0.042
---
0.032
---
---
0.66
0.51
0.64
8.89
8.89
1.07
1.07
1.07
---
2
0.81
---
---
9.04
9.04
1.21
1.21
1.42
0.50
10
K
R
U
V
W
X
Y
Z
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
0.356
0.356
0.048
0.048
0.056
0.020
10
2
_
_
_
_
G1 0.310
K1 0.040
0.330
---
7.88
1.02
8.38
---
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6
MC10124
PACKAGE DIMENSIONS
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
DIM MIN MAX
MILLIMETERS
MIN
19.05
6.10
---
MAX
19.93
7.49
5.08
0.50
A
B
C
D
E
F
0.750
0.240
---
0.015
0.050 BSC
0.785
0.295
0.200
0.020
–T–
SEATING
PLANE
0.39
K
N
1.27 BSC
0.055
0.065
1.40
1.65
G
H
K
L
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
G
0.300 BSC
7.62 BSC
M
S
T B
0.25 (0.010)
M
N
0
0.020
15
0.040
0
_
0.51
15
1.01
D 16 PL
_
_
_
M
S
T A
0.25 (0.010)
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
–A–
ISSUE R
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
MILLIMETERS
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
SEATING
PLANE
–T–
G
H
J
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
K
L
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
_
_
_
_
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
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7
MC10124
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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MC10124/D
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