MC100EP195FAR2 [ONSEMI]
3.3V ECL Programmable Delay Chip; 3.3V ECL可编程延迟芯片
| 型号： | MC100EP195FAR2 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V ECL Programmable Delay Chip |
| 文件： | 总20页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP195, MC100EP195
3.3V ECL Programmable
Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay
increment of the EP195 has a digitally selectable resolution of about
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 3.
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MARKING
DIAGRAM*
MCXXX
EP195
AWLYYWW
32
LQFP−32
FA SUFFIX
CASE 873A
1
Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
XXX
A
WL
YY
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
WW
*For additional marking information, refer to
Application Note AND8002/D.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between V (pin 7) and V (pin 8)
EF
CF
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave V and V open. For ECL operation, short V and
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
CF
EF
CF
V
EF
(pins 7 and 8). For LVTTL level operation, connect a 1.5 V
supply reference to V and leave open V pin. The 1.5 V reference
CF
EF
voltage to V pin can be accomplished by placing a 2.2 kW resistor
CF
between V and V for a 3.3 V power supply.
CF
EE
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
The 100 Series contains temperature compensation.
• Maximum Input Clock Frequency >1.2 GHz Typical
• Programmable Range: 0 ns to 10 ns
• Delay Range: 2.2 ns to 12.2 ns
• Open Input Default State
• Safety Clamp on Inputs
• A Logic High on the EN Pin Will Force Q to Logic
Low
• 10 ps Increments
• PECL Mode Operating Range:
• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
Inputs
V
CC
= 3.0 V to 3.6 V with V = 0 V
EE
• V Output Reference Voltage
BB
• NECL Mode Operating Range:
= 0 V with V = −3.0 V to −3.6 V
V
CC
EE
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
October, 2004 − Rev. 13
MC10EP195/D
MC10EP195, MC100EP195
V
EE
D0 V
Q
Q
V
V
NC
CC
CC CC
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
D1
D2
D3
EN
CASCADE
CASCADE
V
MC10EP195
MC100EP195
V
CC
EE
D4
D5
SETMAX
SETMIN
LEN
D6
D7
V
EE
1
2
3
4
5
6
7
8
D8 D9 D10 IN IN
V
V
V
BB EF CF
Figure 1. 32−Lead LQFP Pinout (Top View)
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2
MC10EP195, MC100EP195
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
D[0:9]
LVCMOS, LVTTL,
ECL Input
Low
Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to V
(Note 1)
.
EE
3
D[10]
LVCMOS, LVTTL,
ECL Input
Low
Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to V . (Note 1)
EE
4
5
IN
IN
ECL Input
ECL Input
Low
Noninverted Differential Input. Internal 75 kW to V
.
EE
High
Inverted Differential Input. Internal 75 kW to V and 36.5 kW to
EE
V
CC
.
6
V
BB
V
EF
V
CF
V
EE
−
−
−
−
−
−
−
−
ECL Reference Voltage Output
7
8
Reference Voltage for ECL Mode Connection
LVCMOS, ECL, OR LVTTL Input Mode Select
9, 24, 28
Negative Supply Voltage. All V Pins must be Externally
EE
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
13, 18, 19, 22
V
CC
−
−
Positive Supply Voltage. All V Pins must be externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
CC
10
11
LEN
ECL Input
ECL Input
Low
Low
Single−ended D pins LOAD / HOLD input. Internal 75 kW to V
.
EE
SETMIN
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
. (Note 1)
V
EE
12
14
15
SETMAX
CASCADE
CASCADE
ECL Input
ECL Output
ECL Output
Low
−
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
. (Note 1)
V
EE
Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50 W to V = V − 2 V.
TT
CC
−
Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50 W to V = V − 2 V.
TT
CC
16
17
EN
NC
ECL Input
−
Low
−
Single−ended Output Enable Pin. Internal 75 kW to V
.
EE
No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
21
20
Q
Q
ECL Output
ECL Output
−
−
Noninverted Differential Output. Typically Terminated with 50 W to
V
TT
= V − 2 V.
CC
Inverted Differential Output. Typically Terminated with 50 W to
= V − 2 V.
V
TT
CC
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All V and V pins must be externally connected to Power Supply to guarantee proper operation.
CC
EE
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3
MC10EP195, MC100EP195
Table 2. CONTROL PIN
Pin
State
LOW (Note 3)
HIGH
Function
EN
Input Signal is Propagated to the Output
Output Holds Logic Low State
LEN
LOW (Note 3)
HIGH
Transparent or LOAD mode for real time delay values present on D[0:10].
LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
SETMIN
SETMAX
D10
LOW (Note 3)
HIGH
Output Delay set by D[0:10]
Set Minimum Output Delay
LOW (Note 3)
HIGH
Output Delay set by D[0:10]
Set Maximum Output Delay
LOW (Note 3)
HIGH
CASCADE Output LOW, CASCADE Output HIGH
CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
V
Pin (Note 4)
ECL Mode
VCF
VCF
EF
No Connect
LVCMOS Mode
LVTTL Mode (Note 5)
V
CF
1.5 V $ 100 mV
4. Short V (pin 8) and V (pin 7).
CF
EF
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, R (suggested resistor value
CF
is 2.2 kW $5%), between V and V pins.
CF
EE
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10])
LVCMOS
YES
LVTTL
YES
LVPECL
YES
LVNECL
N/A
POWER SUPPLY
PECL Mode Operating Range
NECL Mode Operating Range
N/A
N/A
N/A
YES
Table 5. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
ESD Protection
(R1)
75 kW
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity (Note 6)
Flammability Rating
Transistor Count
Level 2
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
1217 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
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4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IN
Q
Q
R1
512
GD*
256
GD*
128
GD*
64
GD*
32
GD*
16
GD*
8
GD*
4
GD*
2
GD*
1
GD*
1
GD*
IN
R1
EN
R1
LEN
R1
R1
10 BIT LATCH
R1
SET MIN
SET MAX
R1
D9
R1
R1
R1
R1
R1
R1
R1
R1
D0
R1
V
V
V
V
BB
CF
EF
D8
D7
D6
D5
D4
D3
D2
D1
EE
*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE
(MINIMUM FIXED DELAY APPROX. 2.2 ns)
CASCADE
CASCADE
Latch
D10
R1
MC10EP195, MC100EP195
Table 6. THEORETICAL DELAY VALUES
D(9:0) Value
XXXXXXXXXX
0000000000
SETMIN
SETMAX
Programmable Delay*
0 ps
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
0 ps
0000000001
10 ps
0000000010
20 ps
0000000011
30 ps
0000000100
40 ps
0000000101
50 ps
0000000110
60 ps
0000000111
70 ps
0000001000
80 ps
0000010000
160 ps
320 ps
640 ps
1280 ps
2560 ps
5120 ps
10230 ps
10240 ps
0000100000
0001000000
0010000000
0100000000
1000000000
1111111111
XXXXXXXXXX
*Fixed minimum delay not included.
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6
MC10EP195, MC100EP195
14000.0
13000.0
12000.0
11000.0
10000.0
9000.0
8000.0
7000.0
6000.0
5000.0
4000.0
3000.0
2000.0
1000.0
0.0
85°C
25°C
−40°C
V
V
= 0 V
CC
= −3.3 V
EE
0.0
100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1000.0
Decimal Value of Select Inputs (D[9:0])
Figure 3. Measured Delay vs. Select Inputs
Table 7. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
Positive Mode Power Supply
Negative Mode Power Supply
V
V
6
EE
= 0 V
−6
V
CC
Positive Mode Input Voltage
Negative Mode Input Voltage
V
V
= 0 V
= 0 V
V ≤ V
6
V
V
EE
I
CC
V ≥ V
−6
CC
I
EE
I
I
Output Current
Continuous
Surge
50
mA
mA
out
100
V
BB
Sink/Source
±0.5
mA
°C
BB
T
Operating Temperature Range
−40 to +85
−65 to +150
A
T
Storage Temperature Range
°C
stg
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
LQFP−23
LQFP−23
80
55
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Wave Solder
Standard Board
LQFP−23
12 to 17
265
°C/W
°C
JC
T
sol
< 2 to 3 sec @ 248°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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7
MC10EP195, MC100EP195
Table 8. 10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 7)
CC
EE
−40°C
25°C
Typ
150
85°C
Typ
150
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Input HIGH Voltage (Single−Ended)
Unit
mA
mV
mV
mV
I
EE
100
145
175
100
180
100
180
V
OH
V
OL
V
IH
2165 2290 2415 2230 2355 2480 2290 2415 2540
1365 1490 1615 1430 1555 1680 1490 1615 1740
2090
2000
2000
2415 2155
3300 2000
3300 2000
2480 2215
3300 2000
3300 2000
2540
3300
3300
LVPECL
LVCMOS
LVTTL
V
IL
Input LOW Voltage (Single−Ended)
mV
1365
0
0
1690 1430
1755 1490
1815
800
800
LVPECL
LVCMOS
LVTTL
800
800
0
0
800
800
0
0
V
V
V
V
ECL Output Voltage Reference
LVTTL Mode Input Detect Voltage
1790 1890 1990 1855 1955 2055 1915 2015 2115
1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6
1915 2020 2120 1940 2080 2190 1985 2130 2265
mV
V
BB
CF
Reference Voltage for ECL Mode Connection
mV
V
EF
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
2.0
3.3
2.0
3.3
2.0
3.3
IHCMR
I
I
Input HIGH Current (@ V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@ V )
IN
IN
0.5
−150
0.5
−150
0.5
−150
IL
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −0.3 V.
CC
EE
8. All loading with 50 W to V − 2.0 V.
CC
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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8
MC10EP195, MC100EP195
Table 9. 10EP DC CHARACTERISTICS, NECL V = 0 V, V = −3.3 V to −3.0 V (Note 10)
CC
EE
−40°C
25°C
Typ
150
85°C
Typ
150
Min
100
Typ
Max
Min
Max
Min
Max
180
Symbol
Characteristic
Unit
mA
mV
I
EE
Negative Power Supply Current
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
145
175
100
180
100
V
OH
V
OL
V
IH
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV
mV
Input HIGH Voltage (Single−Ended)
LVNECL
−1210
−885 −1145
−820 −1085
−760
V
IL
Input LOW Voltage (Single−Ended)
LVNECL
mV
−1935
−1610 −1870
−1545 −1810
−1485
V
V
ECL Output Voltage Reference
−1510 −1410 −1310 −1445 −1345 −1245 −1385 −1285 −1185 mV
−1385 −1280 −1180 −1360 −1220 −1110 −1315 −1170 −1035 mV
BB
Reference Voltage for ECL Mode
Connection
EF
V
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
IHCMR
I
I
Input HIGH Current (@ V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@ V )
IN
IN
0.5
−150
0.5
−150
0.5
−150
IL
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V
V
can vary +0.3 V to −0.3 V.
CC. EE
11. All loading with 50 W to V − 2.0 V.
CC
12.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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9
MC10EP195, MC100EP195
Table 10. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 13)
CC
EE
−40°C
25°C
Typ
140
85°C
Typ
145
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
I
EE
Negative Power Supply Current
100
135
160
100
170
100
175
mA
V
OH
V
OL
V
IH
Output HIGH Voltage (Note 14)
Output LOW Voltage (Note 14)
Input HIGH Voltage (Single−Ended)
2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
mV
2075
2000
2000
2420 2075
3300 2000
3300 2000
2420 2075
3300 2000
3300 2000
2420
3300
3300
LVPECL
CMOS
TTL
V
IL
Input LOW Voltage (Single−Ended)
mV
1355
0
0
1675 1490
1675 1490
1675
800
800
LVPECL
CMOS
TTL
800
800
0
0
800
800
0
0
V
V
V
V
ECL Output Voltage Reference
LVTTL Mode Input Detect Voltage
1775 1875 1975 1775 1875 1975 1775 1875 1975 mV
1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6
1915 2020 2120 1940 2080 2190 1985 2130 2265 mV
BB
V
CF
Reference Voltage for ECL Mode Connection
EF
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 15)
2.0
3.3
2.0
3.3
2.0
3.3
V
IHCMR
I
I
Input HIGH Current (@ V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@ V )
IN
IN
0.5
−150
0.5
−150
0.5
−150
IL
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13.Input and output parameters vary 1:1 with V
V
can vary +0.3 V to −0.3 V.
CC. EE
14.All loading with 50 W to V − 2.0 V.
CC
15.V
min varies 1:1 with V , V
max varies 1:1 with V
The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC.
IHCMR
input signal.
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10
MC10EP195, MC100EP195
Table 11. 100EP DC CHARACTERISTICS, NECL V = 0 V, V = −3.3 V (Note 16)
CC
EE
−40°C
Typ
25°C
Typ
140
85°C
Typ
145
Min
Max
160
Min
Max
Min
Max
Symbol
Characteristic
Unit
I
EE
Negative Power Supply Current
(Note 17)
100
135
100
170
100
175
mA
V
OH
V
OL
V
IH
Output HIGH Voltage (Note 18)
Output LOW Voltage (Note 18)
Input HIGH Voltage (Single−Ended)
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
mV
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV
mV
−1225
−880 −1225
−880 −1225
−880
LVNECL
V
IL
Input LOW Voltage (Single−Ended)
mV
−1945
−1625 −1945
−1625 −1945
−1625
LVNECL
V
V
ECL Output Voltage Reference
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
−1385 −1280 −1180 −1360 −1220 −1110 −1315 −1170 −1035 mV
BB
Reference Voltage for ECL Mode Con-
nection
EF
V
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
IHCMR
I
I
Input HIGH Current (@ V
)
150
150
150
mA
mA
IH
IH
Input LOW Current (@ V )
IN
IN
0.5
−150
0.5
−150
0.5
−150
IL
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
16.Input and output parameters vary 1:1 with V
V
can vary +0.3 V to −0.3 V.
CC. EE
17.Required 500 lfpm air flow when using +5 V power supply. For (V − V ) > 3.3 V, 5 W to 10 W in line with V required for maximum thermal
CC
EE
EE
protection at elevated temperatures. Recommend V − V operation at ≤ 3.8 V.
CC
EE
18.All loading with 50 W to V − 2.0 V.
CC
19.V
min varies 1:1 with V , V
max varies 1:1 with V . The V range is referenced to the most positive side of the differential
IHCMR
IHCMR
EE IHCMR
CC
input signal.
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11
MC10EP195, MC100EP195
Table 12. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −3.6 V or V = 3.0 V to 3.6 V; V = 0 V (Note 20)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
1.2
85°C
Typ
1.2
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Maximum Frequency
Propagation Delay
Unit
GHz
ps
f
1.2
max
t
t
PLH
PHL
1650
2050
2450
1800
2200
2600
1950
2350
2750
IN to Q; D(0−10) = 0
9500 11500 13500 10000 12200 14000 10800 13300 15800
IN to Q; D(0−10) = 1023
EN to Q; D(0−10) = 0
D0 to CASCADE
1600
300
2150
420
2600
500
1800
350
2300
450
2800
550
2000
425
2500
525
3000
625
t
Programmable Range
ps
ps
RANGE
7850
9450
8200 10000
8850 10950
t
(max) − t (min)
PD
PD
Dt
Step Delay (Note 21)
13
27
44
14
30
47
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
41
100
145
360
90
97
130
312
590
1100
2250
4500
140
335
650
1180
2400
4800
690
1300
2650
5300
mono
Monotonicity (Note 27)
TBD
25
t
Duty Cycle Skew (Note 22)
ps
ps
SKEW
25
25
|t
−t
|
PHL PLH
t
s
Setup Time
200
300
300
0
140
150
200
300
300
0
160
170
200
300
300
0
180
180
D to LEN
D to IN (Note 23)
EN to IN (Note 24)
t
t
Hold Time
ps
ps
h
200
400
60
250
200
400
100
280
200
400
80
300
LEN to D
IN to EN (Note 25)
Release Time
R
150
400
350
−25
200
275
150
400
350
−75
250
200
150
400
350
−50
300
225
EN to IN (Note 26)
SET MAX to LEN
SET MIN to LEN
t
RMS Random Clock Jitter
@ 1.2 GHz
3
3
3
ps
mV
ps
jitter
V
Input Voltage Swing
(Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
PP
t
r
t
f
Output Rise/Fall Time @ 50 MHz
85
100
100
140
135
200
85
110
110
150
135
200
95
130
125
170
155
220
20−80% (Q)
20−80% (CASCADE)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
21.Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
22.Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
23.This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
24.This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/IN transition.
25.This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition.
26.This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
27.The monotonicity indicates the increasing delay value for each binary count increment on the control inputs D[9:0].
http://onsemi.com
12
MC10EP195, MC100EP195
IN
V
INPP
= V (D) − V (D)
IH IL
IN
Q
V
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 4. AC Reference Measurement
Cascading Multiple EP195s
Figure 5 illustrates the interconnect scheme for cascading
two EP195s. As can be seen, this scheme can easily be
expanded for larger EP195 chains. The D10 input of the
EP195 is the CASCADE control pin. With the interconnect
scheme of Figure 5 when D10 is asserted, it signals the need
for a larger programmable range than is achievable with a
single device and switches output pin CASCADE HIGH and
pin CASCADE LOW. The A11 address can be added to
generate a cascade output for the next EP195. For a 2−device
configuration, A11 is not required.
To increase the programmable range of the EP195,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP195s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range: however, this
increase is at the expense of a longer minimum delay.
Need if Chip #3 is used
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4
D8
V
EE
D3 D2 D1
D7 D6 D5 D4
D8
V
EE
D3 D2 D1
V
EE
V
EE
D9
D0
D9
D0
D10
D10
V
CC
V
CC
EP195
EP195
IN
IN
Q
IN
IN
Q
INPUT
OUTPUT
Q
CC
CC
Q
CC
CC
CHIP #2
CHIP #1
V
V
V
V
V
V
BB
EF
BB
EF
V
V
V
CF
NC
V
CF
NC
Figure 5. Cascading Interconnect Architecture
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13
MC10EP195, MC100EP195
An expansion of the latch section of the block diagram is
pictured in Figure 6. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10
(1111111111 on the A0—A9 address bus) D10 will be
asserted to signal the need to cascade the delay to the next
EP195 device. When D10 is asserted, the SET MIN pin of
chip #2 will be deasserted and SET MAX pin asserted
resulting in the device delay to be the maximum delay.
Table 13 shows the delay time of two EP195 chips in
cascade.
To expand this cascading scheme to more devices, one
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 5. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
of chip #1 in Figure
5 is LOW this device’s
CASCADE output will also be low while the CASCADE
output will be high. In this condition the SET MIN pin of
chip #2 will be asserted HIGH and thus all of the latches of
chip #2 will be reset and the device will be set at its minimum
delay.
Chip #1, on the other hand, will have both SET MIN and
SET MAX deasserted so that its delay will be controlled
entirely by the address bus A0—A9. If the delay needed is
greater than can be achieved with 1023 gate delays
TO SELECT MULTIPLEXERS
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
D4 Q4
BIT 5
D5 Q5
BIT 6
BIT 7
BIT 8
BIT 9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D6 Q6
D7 Q7
D8 Q8
D9 Q9
LEN
Set Reset
LEN
Set Reset
LEN
Set Reset
LEN
Set Reset
LEN
Set Reset
LEN
Set Reset
LEN
Set Reset
LEN
Set Reset
LEN
Set Reset
LEN
Set Reset
SET
MIN
SET
MAX
Figure 6. Expansion of the Latch Section of the EP195 Block Diagram
http://onsemi.com
14
MC10EP195, MC100EP195
Table 13. Delay Value of Two EP195 Cascaded
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1
Total
D10
0
D9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
D8
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
D7
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
D6
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
D5
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
D4
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
D3
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
D1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
D0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
Delay Value
Delay Value
0 ps
4400 ps
0
10 ps
20 ps
4410 ps
4420 ps
4430 ps
4440 ps
4450 ps
4460 ps
4470 ps
4480 ps
4560 ps
4720 ps
5040 ps
5680 ps
6960 ps
9520 ps
14630 ps
0
0
30 ps
0
40 ps
0
50 ps
0
60 ps
0
70 ps
0
80 ps
0
160 ps
220 ps
640 ps
1280 ps
2560 ps
5120 ps
10230 ps
0
0
0
0
0
0
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1
Total
Delay Value
14640 ps
D10
1
D9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
D8
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
D7
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
D6
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
D5
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
D4
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
D3
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
D1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
D0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
Delay Value
10240 ps
10250 ps
10260 ps
10270 ps
10280 ps
10290 ps
10300 ps
10310 ps
10320 ps
10400 ps
10560 ps
10880 ps
11520 ps
12800 ps
15360 ps
20470 ps
1
14650 ps
14660 ps
14670 ps
14680 ps
14690 ps
14700 ps
14710 ps
14720 ps
14800 ps
14960 ps
15280 ps
15920 ps
17200 ps
19760 ps
24870 ps
1
1
1
1
1
1
1
1
1
1
1
1
1
1
http://onsemi.com
15
MC10EP195, MC100EP195
Multi−Channel Deskewing
be sent through each EP195 as shown in Figure 7. One signal
channel can be used as reference and the other EP195s can be
used to adjust the delay to eliminate the timing skews. Nearly
any high−speed system can be fine−tuned (as small as 10 ps)
to reduce the skew to extremely tight tolerances.
The most practical application for EP195 is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high−speed
system. To deskew multiple signal channels, each channel can
EP195
IN
IN
Q
Q
#1
EP195
#2
IN
IN
Q
Q
EP195
#N
IN
IN
Q
Q
Digital
Data
Control
Logic
Figure 7. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
If the programmed delay through the second EP195 is too
long, the flip−flop output will be at logic high. On the other
hand, if the programmed delay through the second EP195 is
too short, the flip−flop output will be at a logic low. If the
programmed delay is correctly fine−tuned in the second
EP195, the flip−flop will bounce between logic high and logic
low. The digital code in the second EP195 can be directly
correlated into an accurate device delay.
EP195s provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP195s and EP31 as shown in Figure 8,
the delay can be measured. The first EP195 can be set to
SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip−flop of
EP31. The second EP195 is triggered along with the first
EP195 and its output provides a clock signal for EP31.
The programmed delay of the second EP195 is varied to
detect the output edge from the unknown delay device.
EP195
CLOCK
IN
IN
Q
Q
Unknown Delay
Device
CLOCK
#1
D
Q
Q
EP31
CLK
EP195
#2
IN
IN
Q
Q
Control
Logic
Figure 8. Multiple Channel Deskewing Diagram
http://onsemi.com
16
MC10EP195, MC100EP195
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
MC10EP195FA
Package
LQFP−32
LQFP−32
LQFP−32
LQFP−32
Shipping
250 Units / Tray
2000 / Tape & Reel
250 Units / Tray
MC10EP195FAR2
MC100EP195FA
MC100EP195FAR2
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
17
MC10EP195, MC100EP195
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1642/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
http://onsemi.com
18
MC10EP195, MC100EP195
PACKAGE DIMENSIONS
32 LEAD LQFP
CASE 873A−02
ISSUE B
4X
A
A1
0.20 (0.008) AB T−U
Z
32
25
1
AE
AE
−U−
V
−T−
P
B
B1
DETAIL Y
−Z−
BASE
METAL
DETAIL Y
V1
17
8
N
9
4X
0.20 (0.008) AC T−U
Z
9
F
D
S1
S
_
8X M
J
R
DETAIL AD
G
SECTION AE−AE
−AB−
−AC−
E
C
SEATING
PLANE
0.10 (0.004) AC
W
_
Q
H
K
X
DETAIL AD
NOTES:
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
0.138 BSC
0.276 BSC
0.138 BSC
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
B1
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.012
0.053
0.012
E
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.500
0.150
0.200
0.700
0.002
0.004
0.020
0.006
0.008
0.028
J
K
_
12 REF
_
12 REF
M
N
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5_
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
http://onsemi.com
19
MC10EP195, MC100EP195
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC10EP195/D
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