LV8814J-AH [ONSEMI]
Motor Driver 3-Phase PWM Full-Wave BLDC;
| 型号： | LV8814J-AH |
| 厂家： | 
ONSEMI |
| 描述： | Motor Driver 3-Phase PWM Full-Wave BLDC |
| 文件： | 总36页 (文件大小：2107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LV8811G, LV8813G, LV8814J
Motor Driver, 3-Phase, PWM,
Full-Wave, BLDC
Overview
The LV8811G, LV8813G, and LV8814J are 3-phase BLDC motor drivers
which are controlled with single Hall sensor. A 180 degrees sinusoidal driving
method is adopted and the IC can control motor with low vibration and the low
noise. Lead-angle adjustment is possible by external pins. The lead-angle base
and lead-angle slope can be adjusted independently. Thus, the device can be
driven by high efficiency and low noise with various motors. The power element
to drive a motor is built-in and contributes to high efficiency by low on
resistance (0.5 Ω). The Hall sensor bias driver is equipped, and a Hall IC is
supported as well. As a method of the rotary speed control of the motor,
direct-PWM pulse input or DC-voltage input can be chosen.
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LV8811G, LV8813G : 20-pin TSSOP
with exposed pad
Features
CASE 948AZ
∙3-phase full wave (sinusoidal) drive
∙Any practical combination of slot and pole can be handled. (e.g. 3S2P, 3S4P,
6S4P, 6S8P, 12S8P, 9S12P and so on)
LV8814J: 20-pin SSOP
CASE 565AN
MARKING DIAGRAM
∙Built-in power FETs (P-MOS/N-MOS)
∙Speed control function by direct PWM or DC voltage input
∙Minimum input PWM duty cycle can be configured by voltage input
∙Soft start-up function and soft shutdown function
∙Soft PWM duty cycle transitions
∙Built-in current limit circuit and thermal protection circuit
∙Regulated voltage output pin for Hall sensor bias
∙Built-in locked rotor protection and auto recovery circuit
∙FG signal output
∙Dynamic lead angle adjustment with respect to rotational speed
∙Lead-angle control parameters can be configured by voltage inputs.
XXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
Typical Applications
ORDERING INFORMATION
∙Refrigerator
∙PC
∙Games
Ordering Code:
LV8811G-AH
LV8813G-AH
LV8814J-AH
Package
LV8811G, LV8813G
TSSOP20J
(Pb-Free / Halogen Free)
LV8814J
SSOP20
(Pb-Free / Halogen Free)
Shipping (Qty / packing)
2000 / Tape & Reel
† For information on tape and reel specifications, including part
orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D.
http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
LV8811G_LV8813G_LV8814J/D
June 2016- Rev. 0
LV8811G, LV8813G, LV8814J
BLOCK DIAGRAM
Figure 1. LV8811G, LV8813G, and LV8814J Block Diagram
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LV8811G, LV8813G, LV8814J
APPLICATION CIRCUIT DIAGRAM
UO
WO
Hall
VO
Power
Supply
VO
PGND
(NC)
WO
1
2
20
19
18
17
16
15
14
13
12
11
UO
D1
R1
RF
3
RFS
VCC
REG
PH1
PH2
PWM
FG
SGND
CPWM
VTH
4
R11
R12
5
6
C2
R3
MDS
IN2
7
R5
R6
R4
8
C3
Exposed-PAD
R7
HB
9
PWM
Signal
Input
( )
R8
IN1
10
Hall
Pull up
power
R9
Rotation
Signal
Output
( )
R10
Notice: LV8814J do not include the exposed-PAD.
Figure 2. Three-phase BLDC Motor Drive with LV8811G, LV8813G, and LV8814J using One Hall Sensor
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LV8811G, LV8813G, LV8814J
UO
WO
Hall
VO
Power
Supply
VO
PGND
(NC)
WO
1
2
20
19
18
17
16
15
14
13
12
11
UO
D1
R1
RF
3
RFS
VCC
REG
PH1
PH2
PWM
FG
SGND
CPWM
VTH
4
R11
R12
5
6
C2
R3
R4
MDS
IN2
7
R5
R13
R14
8
R6
C3
Exposed-PAD
R7
HB
9
PWM
Signal
Input
( )
R8
IN1
10
Hall
IC
Pull up
power
R9
R15
Rotation
Signal
Output
( )
R10
Notice: LV8814J do not include the exposed-PAD.
Figure 3. Three-phase BLDC Motor Drive with LV8811G, LV8813G, and LV8814J using One Hall IC
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LV8811G, LV8813G, LV8814J
UO
WO
Hall
VO
Power
Supply
VO
PGND
1
2
20
19
18
17
16
15
14
13
12
11
UO
RF
(NC)
WO
D1
R1
3
RFS
SGND
4
R14
R15
VCC
REG
CPWM
VTH
5
C5
C4
R17
6
C2
R3
R4
R18
R16
MN1
PH1
MDS
IN2
HB
7
R5
PH2
8
R11
R6
C3
Exposed-PAD
PWM
9
R12
FG
IN1
10
Hall
Pull up
power
R9
Rotation
Signal
Output
PWM
Signal
Input
( )
R13
R10
Notice: LV8814J do not include the exposed-PAD.
Figure 4. Three-phase BLDC Motor Drive with LV8811G, LV8813G, and LV8814J using input PWM to DC conversion for
speed control
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LV8811G, LV8813G, LV8814J
EXAMPLE COMPONENT VALUE
Device
D1
ZD1
Value
MBRA340T3G (ON semi)
MNSZ5247BT1G (ON semi)
Device
R5
R6
R7
Value
0 to 50kΩ
50k to 0Ω
1kΩ
CM
C1
C2
C3
C4
C5
4.7µF
1500pF
1µF
0.1µF
1µF
R8
R9
NC
1k to 10kΩ
1kΩ
0 to 50kΩ
50k to 0Ω
10kΩ
30kΩ
7.5kΩ
62kΩ
68kΩ
1kΩ
R10
R11
R12
R13
R14
R15
R16
R17
R18
330pF
R1
R2
R3
R4
0.22Ω // 0.22Ω (0.5W)
1kΩ
0 to 50kΩ
50k to 0Ω
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LV8811G, LV8813G, LV8814J
PIN ASSIGNMENT
20
19
18
17
16
15
14
13
12
11
1
2
PGND
(NC)
WO
VO
UO
RF
3
4
RFS
SGND
CPWM
VTH
5
VCC
REG
PH1
PH2
PWM
FG
6
7
MDS
IN2
8
Exposed-PAD
9
HB
10
IN1
Notice: LV8814J do not include the exposed-PAD.
Figure 5. LV8811G, LV8813G, and LV8814J Pin Assignment
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LV8811G, LV8813G, LV8814J
LV8811G, LV8813G, and LV8814J COMPARISION
ASSUME APPLICATION
-LV8811G: Wide operation supply voltage range. Suitable rotate for small-size fans.
-LV8813G: Stable start-up even with a large load. Suitable rotate for large-size fans.
-LV8814J: Stable start-up even with a large load. Suitable rotate for large-size fans.
DIFFERENT CHARACTERISTICS
Comment
Reference
page
LV8811G
LV8813G
LV8814J
LV8811G and LV8814J have a wide operation voltage
range.
LV8811 and LV8814J have different lower Vcc limit in
comparison with the LV8813 to support larger fans.
LV8813G and LV8814J have stronger alignment to
secure the start-up of large-size fans.
VCC/RF operating
Supply
range
voltage 3.6V to 16V 6.0V to 16V 3.6V to 16V
10
Alignment
cycle
duty
6%->5%->
20%->15%
50%->25%
1.0s
20
LV8813G and LV8814J have longer alignment time to
secure the start-up of large-size fans.
10, 20,
23,25
Alignment time
0.8ms
LV8813G and LV8814J have longer detection time to
prevent false Lock detection on large-size fans at the
start-up.
Lock
time
detection
0.33s
0.77s
10, 23, 25
Lock-Stop
5.8s
1:5
5.4s
1:3
Release Time
Lock/Release time
ratio
This characteristic is different due to a different Lock
detection time.
23, 25
34, 35
TSSOP20J has the Exposed-PAD on back. SSOP20
don’t have Exposed-PAD. Foot pattern is same.
Package type
TSSOP20J
SSOP20
PIN FUNCTION DISCRIPTION
Pin No.
Pin Name
VO
Description
V-phase output pin
U-phase output pin
Inverter power supply and Motor current sense resistor pin
Motor Current Sense
Power supply pin
Internal regulator output pin
Lead-angle adjustment pin 1
Lead-angle adjustment pin 2
Speed reference input PWM pin
Motor speed feedback output pin
Hall sensor input pin 1
Hall sensor bias output pin
Hall sensor input pin 2
Minimum output PWM duty cycle setting pin
Speed reference input DC voltage pin
PWM clock frequency control pin
System ground pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
UO
RF
RFS
VCC
REG
PH1
PH2
PWM
FG
IN1
HB
IN2
MDS
VTH
CPWM
SGND
WO
W-phase output pin
No connection
Power ground pin
NC
PGND
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LV8811G, LV8813G, LV8814J
MAXIMUM RATINGS (Note 1)
Parameter
Symbol
VCCMAX
VOUTMAX
IOUTMAX
IREGMAX
IHBMAX
Value
Unit
V
Maximum supply voltage (Note2)
Maximum output voltage (Note3)
Maximum output current (Note3, Note4)
REG pin maximum load current
HB pin maximum load current
PWM pin maximum input voltage
FG pin maximum voltage
20
20
V
2.0
A
20
mA
mA
V
10
VPWMMAX
VFGMAX
(Note 6)
PdMAX
6
17
V
Input pins maximum voltage (Note5)
Allowable Power Dissipation (Note7)
Storage Temperature
3.6
V
2.5
W
ºC
T
−55 to 150
stg
T
Junction Temperature
150
3
ºC
-
JMAX
Moisture Sensitivity Level (MSL) (Note8)
Lead Temperature Soldering Pb-Free Versions (30sec or less) (Note 9)
ESD Human body Model : HBM (Note10)
MSL
T
255
±2000
ºC
V
SLD
ESDHBM
1. Stresses exceeding those listed in the Maximum Rating table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
2.
V
supply pins are V
(5pin), RF (3pin), and RFS (4pin).
CC
CC
3. Motor power supply pins are UO (2pin), VO (1pin), and WO (18pin).
4. IOUTMAX is the peak value of the motor supply current.
5. Input pins are PH1 (7pin), PH2 (8pin), IN1 (11pin), IN2 (13pin), MDS (14pin), VTH (15pin), and CPWM (16pin).
6. Pin : Symbol PH1:VPH1MAX, PH2:VPH2MAX, IN1:VIN1MAX, IN2:VIN2MAX, MDS:VMDSMAX, VTH:VVTHMAX, CPWM:VCPWMMAX
7. Specified circuit board: 57.0mm×57.0mm×1.6mm, glass epoxy 2-layer board. It has 1 oz copper traces on top and bottom of the board.
Please refer to Thermal Test Conditions of page 32.
8. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC standard: J-STD-020A
9. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
http://www.onsemi.com/pub_link/Collateral/SOLDERRM-D.PDF
10. ESD Human Body Model is based on JEDEC standard: JESD22-A114
THERMAL CHARACTERISTICS
Parameter
Symbol
Condition
Value
50.0
95.0
15.5
35.0
Unit
Case of the LV8811G and LV8813G
Case of the LV8814J
ºC/W
ºC/W
ºC/W
ºC/W
R
Thermal Resistance, Junction-to-Ambient (Note7)
θJA
Case of the LV8811G and LV8813G
Case of the LV8814J
R
Thermal Resistance, Junction-to-Case (Top) (Note7)
ΨJT
2.8
2.4
2
2.5
θ
ja : LV8811G, LV8813G
(TSSOP20J)
1.6
1.2
0.8
0.4
0
1.31
0.9
θ
ja : LV8814J
(SSOP20)
0.47
-40
-20
0
20
40
60
80
100
120
140
Ambient temperature, Ta - ˚C
Figure 6. Power Dissipation vs Ambient Temperature Characteristic
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LV8811G, LV8813G, LV8814J
RECOMMENDED OPERATING RANGES (Note11)
Parameter
Symbol
VCCOP
Ratings
Unit
V
VCC supply voltage Range at LV8811G and LV8814J (Note2)
VCC supply voltage Range at LV8813G (Note2)
PWM input frequency range
3.6 to 16.0
6.0 to 16.0
20 to 50
0 to 100
0 to 5
V
fPWM
kHz
%
V
PWM input duty cycle range
PWM input voltage range
DPWM
VPWM
VIN1
IN1 input voltage range
0 to VREG
0.3 to 1.8
0 to VREG
−40 to 105
V
IN2 input voltage range
VIN2
V
Control input Voltage Range (Note12)
Ambient Temperature
(Note 13)
TA
V
ºC
11. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.
12. Control input pins are PH1, PH2, MDS, and VTH
13. Pin : Symbol PH1:VPH1, PH2:VPH2, MDS:VMDS, VTH:VVTH
ELECTRICAL CHARACTERISTICS
TA=25ºC, VCCOP = 12V UNLESS OTHERWISE NOTED. (NOTE 14)
Parameter
Symbol
Condition
Min
Typ
4.5
Max
7.0
Unit
mA
Circuit Current
Supply Current
ICC0
PWM = 3V, CPWM=0V, IO=0A
Protection (Note15)
Over Current Detection Voltage
Over Voltage Detection Voltage
Over Voltage Detection Hysteresis
VTHCLM
VTHOVP
ΔVTHOVP
The voltage between VCC - RF
VCC pin, Guaranteed by design
VCC pin, Guaranteed by design
Case of the LV8811G
0.162
19
0.180
20
0.198
V
V
V
S
S
S
S
2
0.23
0.55
4.15
3.82
0.32
0.76
5.68
5.23
0.41
0.97
7.21
6.64
Lock Detection Time
Lock Protection Time
TLD
Case of the LV8813G and LV8814J
Case of the LV8811G
TLP
Case of the LV8813G and LV8814J
Thermal Protection Detection
Temperature
Thermal Protection Detection
Hysteresis
TTHP
Guaranteed by design
Guaranteed by design
150
180
15
˚C
˚C
ΔTTHP
Regulator
REG Pin Output Voltage
Output
VREG
2.7
3.0
3.3
V
UO/VO/WO Output Resistance
FG Output (Note16)
ROUTON
IO=0.8A, High-side + Low-side
0.5
0.65
Ω
FG Pin Low Level Output Voltage
FG Pin Leak Current
Hall Bias & Hall Signal Input
HB Pin Output Voltage
IN1/IN2 Input Current
Hall Signal Input Hysteresis
VFGL
IFGLK
IFG=5mA
VFG=16V
0.3
1
V
μA
VHB
IH
IHB=5mA
1.06
1.18
1.30
1
V
μA
mV
ΔVH
Guaranteed by design
+/-10
Continued on next page.
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LV8811G, LV8813G, LV8814J
Continued from preceding page.
Parameter
Symbol
Condition
Min
Typ
Max
Unit
PWM Input
PWM Pin Low Level Input
Voltage
PWM Pin High Level Input
Voltage
VPWML
0
0.6
5.5
V
VPWMH
2.3
200
200
V
PWM On Time
TPWMON
TPWMOFF
Guaranteed by design
Guaranteed by design
ns
ns
PWM Off Time
CPWM Input
VCPWML
VREG
CPWM Minimum Output
Ratio (Note17)
× 100
16
18
20
%
V
CPWM Maximum Output
Ratio (Note17)
CPWMH × 100
65
17
-41
67
29
-29
69
41
-17
%
VREG
CPWM Source Current
CPWM Sink Current
ICPWMSO
VCPWM=1.3V
VCPWM=1.3V
μA
μA
ICPWMSI
14. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
15. Refer to the protection circuit explanation in the function description. Refer to page 23.
16. For FG output pin, it is recommended to connect pull-up resistor between the pin and power supply of the controller.
17. VCPWMH and VCPWML are peak voltage of triangle wave in CPWM pin.
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LV8811G, LV8813G, LV8814J
TYPICAL CHARACTERISTICS
Figure 10. Current limiter detection voltage vs VCC
voltage
Figure 7. Supply current vs VCC voltage
Figure 8. VREG output voltage vs VCC voltage
Figure 9. Output ON resistance vs Output current
Figure 11. VREG output voltage vs REG load current
Figure 12. FG output voltage vs FG input current
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LV8811G, LV8813G, LV8814J
Figure 13. FG leakage current vs FG input voltage
Figure 16. VHB output voltage vs VCC voltage
Figure 17. IN1/IN2 input current vs IN1/IN2 input voltage
Figure 18. CPWM charge/discharge current
Figure 14. VHB output voltage vs HB load current
Figure 15. PWM threshold voltage vs VCC voltage
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LV8811G, LV8813G, LV8814J
Functional Description
POWER SUPPLY PINS (VCC, RF)
RF is output power supply whereas VCC is other circuit
supply. The RF pin supplies large current to built-in
power MOS FTEs. (Figure 23)
*Please refer to page.15 ‘Motor Current Sense Resistor
Pin (RF)’ about the CLM sense resistance of RF
terminal.
GND PIN (SGND, PGND)
PGND is power ground whereas SGND is other circuit
ground. Since PGND has to tolerate surge of current,
separate it from the SGND as far away as possible and
connect it point-to-point to the ground side of the
capacitor (CM) between power supply and ground.
Figure 20. Equivalent circuit of FG
Internal 3.0V Voltage Regulator Pin (REG)
MOTOR DRIVE OUTPUT PINS (UO, VO, WO)
These pins are output of built-in three-phase MOSFET
based inverter that drives the motor. Each leg of the
inverter is having high side P-MOSFET and low side
N-MOSFET. (Figure 21)
An internal 3.0V voltage regulator acts a power source
for internal logic, oscillator, and protection circuits.
When MDS and PH1 and PH2 are used, it is
recommended that application circuits are made using
this output. In addition, the application circuit of VTH is
same, too. The maximum load current of REG is 10mA.
Warn not to exceed this. Place capacity of 1uF degree
and the 0.1uF degree in the close this pin. (Figure 19)
Figure 21. Equivalent circuit of U/V/W
HALL-SENSOR BIAS OUTPUT PIN (HB)
The LV811G, LV8813G, and LV8814 provide a bias
regulator output (1.18V typ.) for a hall sensor. It is
recommended that this output used only for hall sensor
bias.
Figure 19. Equivalent circuit of REG
ROTATIONAL SIGNAL PIN (FG)
Frequency of the FG output represents the motor’s
electrical rotational speed (the same rectangular waves
as the UO). It is an open drain output. Recommended
pull up resistor value is 1kΩ to 10kΩ. Leave the pin
open when not in use. (Figure 20)
HALL-SENSOR INPUT PINS (IN1, IN2)
Differential output signals of the Hall sensor are
connected to IN1 and IN2 individually. Its polarity is
determined by a combination of the number of slot and
poles. (Figure 29)
It is recommended to add 0.1uF capacitor between
them to filter system noise.
Topologies, in the case of a Hall IC, are shown in Figure
30 on page18. The topology (including polarity) is also
determined by the combination of the number of slot
and poles.
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LV8811G, LV8813G, LV8814J
When the pin IN1 is connected to the output of the Hall
The sense resistor value is calculated as follows.
IC, the pin IN2 must be kept in the middle level of the
Hall IC power supply voltage. When the pin IN2 is
connected to the output of the Hall IC, the pin IN1 must
be kept in the middle level of the Hall IC power supply
voltage. Because of the input circuit (Figure 22), the
input voltage of IN2 must be higher than 0.3V.
Therefore, the resistance ratio must be decided so that
IN2 voltage is higher than 0.3V. (Figure 30)
[ ]
VTHCLM
V
[ ]
Sense Resistor Ω =
[ ]
A
ICLM
For example, to set the CLM current threshold at 1.5A,
the sense resistor value is
0.18(typ)
Sense Resistor =
1.5
Regarding the polarity of a Hall sensor and IC, refer
‘Rotation Direction’ on page18.
Res = 0.12[Ω]
MOTOR CURRENT SENSE PIN (RFS)
This pin reads voltage across the series sense resistor
and compares with internal VTHCLM. When the
measured voltage exceeds VTHCLM, CLM is triggered
and when it falls below VTHCLM, the LV8811G,
LV8813G, and LV8814J exits from the CLM mode. A
series RC filter is recommended to avoid false detection
due to switching noise. (Figure 24)
Vcc
LPF
∆V
RFS
Vcc
Figure 22 Equivalent circuit of IN1, IN2
V = VTHOCP
MOTOR CURRENT SENSE RESISTOR PIN (RF)
This is also the power supply pin for the built-in power
inverter. Voltage across the sense resistor represents the
motor current and is compared against the internal
VTHOVC (0.18Vtyp.) for setting the over-current limiter
(CLM). (Figure 23)
RF
∙∆V < VTHOCP
׃
The OCP mode is ineffictive.
∙ ∆V > VTHOCP
׃
The OCP mode is effictive.
Control to OCP
The serise resistor(Sence resistor)
Vcc
U
V
W
Figure 24. Schematic view of the CLM circuit
RF
PGND
The powerMOS FETs
Figure 23. Schematic view of power current route
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LV8811G, LV8813G, LV8814J
COMMAND INPUT (PWM)
PWM FREQUENCY SETTING PIN (CPWM)
This pin reads the duty cycle of the PWM pulse and
controls rotational speed. The PWM input signal level is
supported from 2.5V to 5V. The combination with the
rotational speed control by DC voltage is impossible.
When the pin is not used, it must be connected to ground.
The minimum pulse width is 200ns. (Figure 25)
When rotational speed is controlled with the DC voltage,
this pin is used. The frequency of the triangle wave
which the pin generates at external capacity can be
changed. The frequency of this triangle wave equals
frequency of the PWM control that the output works.
The relations between the external capacitor and
frequency are shown in the next equation.
PWM Frequency fPWM [Hz] is,
ICPWMSI/O[A]
fPWM
=
2 × (VCPWMH − VCPWML)[V] × CPWM[pF]
Where,
[
]
ICPWMSI/O = ICPWMSO = −ICPWMSI ∶ 29 uA (typ. )
Charge/discharge current
VCPWMH: 2.01[V] (typ.) Upper peak voltage of CPWM
triangle waveform. 67% of 3V VREG
VCPWML: 0.54[V] (typ.) Lower peak voltage of CPWM
triangle waveform. 18% of 3V VREG
For example, the capacitance of CPWM, to make the
PWM frequency 30 kHz, can be determined by the
followings
Figure 25. Equivalent circuit of PWM
MINIMUM DUTY CYCLE SETTING PIN (MDS)
29u
30k =
The too small duty cycle of the input PWM can be
blanked out. The threshold of the minimum duty cycle
is configurable. The DC voltage level applied to this pin
is converted to this threshold. The voltage is fetched
right after the power-on-reset. Because the internal
conversion circuit works inside REG power rail, it is
2.94 × CPWM
CPWM ≅ 330[pF]
CPWM decides output PWM frequency. Thus, this value
must choose appropriately. The range from 220pF to
330pF is recommended. CPWM is represented C5 in the
application circuit diagram, Figure 4 on page 5.
recommended that the MDS voltage is made from VREG
.
This pin is also used for setting of FG frequency. Refer
‘Parameter Setting by Constant Voltage’ on page 28,
and ‘Setting Minimum PWM Duty Cycle’ on page 29.
The combination with the rotational speed control by
PWM is impossible. When this pin is not used, it must
be connected to GND. Refer ‘PWM duty CYCLE
control by analog voltage’ on page 26. (Figure 26)
LEAD-ANGLE SETTING PIN (PH1, PH2)
LV8811G, LV8813G, and LV8814J provide the
dynamic lead angle adjustment. To match the motor
characteristics, the base angle and change ratio with
respect to the rotation speed can be configured. The DC
voltage levels applied to these pins are converted to the
lead angle parameter. The voltages are fetched right
after the power-on-reset. Because the internal
conversion circuit works inside REG power rail, it is
recommended that the PH1 and PH2 voltages are made
from VREG. Refer ‘Parameter Setting by Constant
Voltage’ on page 28, and ‘Setting Lead Angle’ on page
30.
Figure 26. Equivalent circuit of CPWM
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16
LV8811G, LV8813G, LV8814J
ROTATIONAL CONTROL PIN BY DC VOLTAGE (VTH)
This pin reads the input DC voltage and controls
rotational speed. The VTH voltage is compared with the
CPWM triangle wave with an internal comparator and
generates PWM pulse and controls rotational speed with
frequency and duty cycle of this pulse.
If the external control signal is the pulse type, it should
be flattening by the filter and be shifted to suitable level.
The external circuit example is shown in Figure 4.
VTH input level flatten by the filter is calculated in the
following equation.
R15 + R16 R14 × R16 DPWM
VVTH = VREG × �
Where
−
×
ꢀ
RA
RA × RB
100
Figure 27. Equivalent circuit of VTH
RA = R14 + R15 + R16
RB = R14 + R15
VVTH = VTH input level
NC PIN (NC)
This pin is not connection to the internal circuit.
This calculation is justified by the condition that Rds of
MN1 << R16. So, a large value of resistor should be
selected to R16.
For example, when the input PWM duty cycle is set in
50%, can be determined by follows.
[ ]
50 %
[ ]
VVTH = 3 V × (0.698 − 0.498 ×
)
100
VVTH = 1.35[V]
Where
R14=7.5[kΩ], R15=30[kΩ], R16=62[kΩ]
The cut-off frequency fc by C4 and R18 is calculated in
the following equation.
1
fc =
2ꢁ × ꢂ4 × ꢃ18
The actual value of C4 or R18 is better to select more than
50 times the above calculation value to be flatten
thoroughly. Furthermore, it is better to do it by the value
of C3 because of the effect of input impedance at VTH
pin.
If the external control signal is the DC type, it inputs
into direct VTH pin. However, It is recommended that
the filter (C4 and R18) is kept because rid of the influence
of the noise.
The CPWM amplitude is decided by VREF. Thus, VTH
recommends that it is made from VREG. The
combination with the rotational speed control by PWM
is impossible. When the pin is not used, it must be
OPEN. Refer ‘PWM duty CYCLE control by analog
voltage’ on page 26. (Figure 27)
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LV8811G, LV8813G, LV8814J
DETAILED DESCRIPTION
As for all numerical value used in this description, the design value or the typical value is used.
ROTATION DIRECTION
The motor type can be categorized into two groups as
3S2P and 3S4P. (S: Slot, P: Pole). The 3S2P group
contains 3S2P, 6S4P and 12S8P, for instance, and 3S4P
groups contains 3S4P, 6S8P and 9S12P. The rotate
direction of 3S2P group is CW, that of 3S4P group is
CCW. The direction can be changed by exchanging
connection between U and W, in the case where the hall
sensor is between U coil and W coil. (Figure 28)
3S2P
6S4P
12S8P
3S4P
6S8P
9S12P
Figure 28. Schematic diagram of motor
Hall output polarity also needs to be set with the type of SP motors. It is shown in Figure 29, Figure 30
REG
IN2
HB
6
IN2 13
HB 12
IN1 11
IN2 13
HB 12
IN1 11
3S2P
6S4P
+
Hall
-
13
3S2P
6S4P
Open
12
12S8P
12S8P
VDD
VSS
IN1
11
Hall
IC
3S4P
6S8P
+
Hall
-
REG
6
9S12P
3S4P
6S8P
IN2
HB
IN1
13
Figure 29. Hall element use connection
Open
12
9S12P
VDD
VSS
Hall
IC
11
Figure 30. Hall IC use connection
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LV8811G, LV8813G, LV8814J
DEVICE START-UP
OUTPUT WAVEFORM
The LV8811G, LV8813G, and LV8814J will start driving,
when the PWM signal is input at the PWMIN pin after a
power supply is turned on.
The output PWM duty cycle is modulated so that the
phase-to-phase voltage waveform is sinusoidal. Two
phases are driven with PWM, while the other phase sunk
to ground.
It can handle the rotational speed up to the 250Hz of FG
frequency (electrical cycle). However, for high speed case,
it depends on motor mechanical parameters. Low speed
side recommends the rotational speed down to the 30Hz
of FG frequency.
COMMUTATION
The commutation timing is determined with respect to the
one Hall sensor or Hall-IC signal, while conventional
sensor-based BLDC motor drivers need three sensors.
A wave pattern example is shown in Figure 31.
IN1 +
IN1 -
IN1
hall
L
L
L
H
H
H
L
L
L
H
H
H
comparator
FG
Max
UO
0%
Max
VO
0%
Max
WO
0%
Figure 31. Timing chart example: Normal Rotation
The amplitude of current waveform is controlled with input PWM duty cycle while the sinusoidal waveform is kept.
FG
U-out
Current of U-out
Input PWM duty-cycle 50%
Input PWM duty-cycle 100%
Figure 32. Normal Rotation (Output pin)
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LV8811G, LV8813G, LV8814J
DETAIL OF THE ROTOR START POSITION ALIGNMENT
After detecting input PWM, the motor-rotor is aligned
to the start position. The start position alignment is
independent on the input PWM duty cycle, and applies
the preset duty cycle described below.
[LV8813G, LV8814J] The output PWM duty cycle
sequence for the rotor alignment consists of the single
step.
[LV8811G] The output PWM duty cycle sequence for
the rotor alignment consists of the three steps.
Alignment duty cycle 1st: 6%, 2nd: 5%, 3rd: 20%
Alignment duty cycle 50%
(Figure 33)
Input duty [%]
60%
Input frequency [kHz]
30kHz
50%
LV8813G, LV8814J
25%
20%
15%
6%
5%
LV8811G
0%
Time
60ms
LV8811G Alignment time
800ms
1s
LV8813G and LV8814J Alignment time
Output frequency [kHz]
30kHz
Figure 33. Timing chart example: Alignment duty cycle
ROTATION START-UP AND SOFT-START
After the adjustment of the start position, the output
duty-cycle begin from 15% (LV8811G) or 25%
(LV8813G, LV8814J). The motor starts to rotate in
sinusoidal drives, increasing output duty cycle (increment
slope is 26[%/s]) till the output duty cycle reaches the
target duty cycle. In case the input PWM duty cycle is
under 20%, the output duty cycle decreases to the target
duty cycle (decrement slope is 26[%/s]) after reaching
20%. After 32 FG pulses the lead angle increases to the
target lead angle (tuned from PH1/PH2) by 1 degree steps
at every FG edge. (Figure 34)
Output duty [%](Duty was set more than 20%)
Target duty( > 20% )
LV8813G
LV8814J
LV8811G
Alignment term
20%
Δ= 26[%/sec]
Output duty [%](Duty was set less than 20%)
LV8813G
LV8814J
Alignment term
20%
Δ= - 26[%/sec]
Target duty( < 20% )
Target Lead angle
LV8811G
Lead angle [deg]
Lead angle
adjusting
FG count
= 32
Δ= 1 [deg/FG]
Time
0
0.8s / 1.0s
Positioning drive
Sinusoidal drive
Figure 34. Timing chart example: Positioning and Soft start
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LV8811G, LV8813G, LV8814J
PWM
FG
U out
Current
of U-out
Input PWM duty-cycle 18%
Input PWM duty-cycle 50%
Figure 35. Alignment and Soft start (Case of the LV8811G)
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LV8811G, LV8813G, LV8814J
DUTY CYCLE DECREASING AND STOP
When input PWM duty cycle is changed from high to low,
the output duty cycle decreases gradually to low with the
decrement slope of 26[%/s]. The target duty cycle is
always updated at positive edge of FG. (Figure 36)
Input
duty [%]
80%
20%
60%
0%
Output duty [%]
LV8813G
LV8814J
80%
80%
60%
60%
Δ= 26[%/sec]
Alignment term
20%
20%
LV8811G
Time [sec]
0
0.8s / 1.0s
Input PWM duty
FG pulse
80%
20%
Target PWM duty
80%
20%
Figure 36. Timing chart example: When PWM Duty cycle changed (80% -> 20% -> 60% -> 0%)
50%
0%
PWM
FG
80%
20%
U-Out
Current
of U-Out
Figure 37. Input duty cycle changing (Case of the LV8811G)
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LV8811G, LV8813G, LV8814J
OUTPUT FREQUENCY
When input PWM duty cycle is 100%, the output
from 66kHz to input PWM frequency (this case is 30kHz).
When input PWM duty cycle is changed to 100% again,
output frequency will remain last input frequency (this
case is 30kHz). (Figure 38)
frequency is 66kHz generated from the internal oscillator.
When input PWM duty cycle is changed from 100% to
low (e.g. 50% with 30kHz), output frequency is changed
Input duty [%]
100%
(DC)
50%
100%
(DC)
Input frequency [kHz]
30kHz
100%
100%
LV8813G
LV8814J
100%
Alignment term
LV8811G
50%
50%
20%
25%
15%
Time
Output frequency [kHz]
66kHz (Initial freq)
30kHz
30kHz
Figure 38. Timing chart example: Output frequency changing
PROTECTIONS
When THP (Thermal Protection) or CLM (Current
Limiter) is detected, the output duty cycle decreases to the
minimum duty cycle rapidly. After exiting the protection
mode, the output duty cycle increases with 26 [%/s] slope.
When OVP (Over Voltage Protection) or LVD (Low
Voltage Detection) signal is detected, all outputs are
turned off. After OVP and LVD are released, outputs are
turned on. (Figure 39)
decreases to the input duty cycle immediately without
slope rate.
(Figure 41)
The level of current limiter is adjustable using the value of
RF resistor.
The value of RF resistor should be set higher than the
current drawn at 100% input duty cycle.
When the current limiter is detected, the output duty cycle
may be restricted before achieving target duty cycle. The
output duty cycle decreases immediately by the current
limiter. The current limiter is release, because the output
duty cycle decreases. Herewith, the output duty cycle
increases to the target duty cycle. And the current limiter
is detected again, and the output duty cycle decreases.
On/off of the current limiter is repeated, and the output
duty cycle is limited. When the PWM input changes to
low duty cycle that release CLM, the output duty cycle
decreases gradually with normal slope rate of 26[%/s].
(Figure 40)
Lock detection and Lock protection
[LV8811G] It takes 5.68s for Lock protection time. Lock
start time is 1.12s. This equals to the total of lock detect
time and the alignment time. The protection-start time
ratio is approx. 1:5. Output under lock protection is in
Hi-Z state.
(Figure 43)
[LV8813G, LV8814J] The lock protection behavior is
same as LV8811G. However, the release time and restart
time are changed as follows:
Lock protection time: 5.23s Lock start time: 1.76s
Protection-start ratio: approx. 1:3 (Figure 44)
When current limiter activates with 100% input duty
cycle, the output duty cycle is restricted before achieving
target duty cycle (100%). When the PWM input changes
from less than low duty cycle, the output duty cycle
When the lock start time, heat is generated that because IC
turned on electricity to the motor. On the other, when the
lock protection time, radiated heat that because IC turned
off electricity to the motor.
Output duty [%]
80%
50%
20%
Time
Input duty
THP or CLM
OVP
80%
20%
50%
LVD
Figure 39. Timing chart example: Protections
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LV8811G, LV8813G, LV8814J
80%
50%
Input duty [%]
30kHz
Input frequency [kHz]
30kHz
LV8813G, LV8814J
80%
Target 80%
Limit Duty
LV8811G
50%
Alignment term
25%
20%
15%
Time
Output frequency [kHz]
30kHz
30kHz
CLM (Current limitter)
*In the case of LV8811G
Figure 40. Timing chart example: Normal current limiter (e.g. input duty cycle 80% -> 50%)
Input duty [%]
100%
(DC)
50%
Input frequency [kHz]
30kHz
LV8813G, LV8814J
100%
Target 100%
LV8811G
Limit Duty
50%
Alignment term
25%
15%
20%
Time
Output frequency [kHz]
66kHz (Initial)
30kHz
CLM (Current limitter)
*In the case of LV8811G
Figure 41. Timing chart example: Current limiter at input duty cycle 100%
PWM
100% Duty
50% Duty
100% Duty
50% Duty
FG
U-Out
Current
of U-Out
CLM ON at PWM duty-cycle 100%
CLM OFF at PWM duty-cycle 100%
Figure 42. Inputting 100% with and without CLM (Case of the LV8811G)
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LV8811G, LV8813G, LV8814J
0.80s
0.32s
0.80s
0.32s
5.68s
Alignment
Drive
Lock
Detect
Alignment
Drive
Lock
Detect
Lock Protect
( Hi-Z state )
Time
[sec]
Lock start time
Lock protection time
5.68sec
Lock start time
1.12sec
1.12sec
Lock start time : Lock protection time = 1.12 : 5.68 ≈ 1: 5 (Protection-start ratio)
Figure 43. Timing chart example: Lock Protection for LV8811G
1.00s
0.76s
1.00s
0.76s
5.23s
Alignment
Drive
Lock
Detect
Alignment
Drive
Lock
Detect
Lock Protect
( Hi-Z state )
Time
[sec]
Lock start time
1.76sec
Lock protection time
5.23sec
Lock start time
1.76sec
Lock start time : Lock protection time = 1.76 : 5.23 ≈ 1: 3 (Protection-start ratio)
Figure 44. Timing chart example: Lock Protection for LV8813G and LV8814J
PWM
Alignment
&
FG
Lock detect
Lock protect
U-Out
Lock protect
Current
of U-Out
Re-start
Figure 45. Lock Protection (Case of the LV8811G)
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LV8811G, LV8813G, LV8814J
PWM DUTY CYCLE CONTROL BY ANALOG VOLTAGE
The duty cycle of PWM output is determined by
the PWM output is switched to the current circulation
state with self-induction of the coil.
The DC level of VTH can control between VREG×18% and
VREG×67%. But the PWM pulse width must not make less
than 200ns. The pulse width of 0s is accepted. (Figure 46)
comparison of CPWM oscillation and DC level which is
input to VTH pin. When CPWM level is lower than VTH,
the PWM output applies the voltage to the coil from the
power supply. When CPWM level is higher than VTH,
VTH
VREG x 67%
CPWM
VREG x 18%
PWM
The pulse width
200ns and more.
The pulse width
200ns and more.
Controllable duty by VHT input
Fixed duty by
MDS setting
Figure 46. PWM Duty cycle control by CPWM and the VTH voltage
The input range of VTH is calculated in the following
equation. (Figure 47)
The relations of VVTH and output PWM duty cycle are
clculated by following equation.
DOUT
VVTH = VCPWMH − (VCPWMH − VCPWML) ×
100
tꢄ
h′ =
× h
t
Where
VTH control range V = 0.18VREG + h′ ~ 0.67VREG − h′
[ ]
DOUT = Output PWM duty cycle
Where,
For example, when the output PWM duty cycle is set in
30%, it can be determined by follows.
h = VCPWMH[V] − VCPWML[V]
[
]
30 %
(
)
VꢅꢆꢇꢈꢉꢊVꢅꢆꢇꢈꢋ [V]×Cꢌ[pF]
[ ] [ ])
(
[ ]
VVTH = 2.01 V − 2.01 V − 0.54 V ×
t =
100
Iꢅꢆꢇꢈꢍꢎ/ꢏ[A]
[ ]
= 1.569 V
t′ = 200ns ÷ 2 = 100ns
When the output PWM duty cycle is set in 100%, it is
recommended to set the VTH input level lower than
VCPWML. In addition, when the output PWM duty cycle
is set in 0%, it is recommended to set the VTH input
*C5 is the CPWM pin external capacity. Refer to page.5 and 17
For example, when 330[pF] is used for CPWM capacity, can
be determined by followings
level higher than VCPWMH
.
0.1[us]
h′ =
[ ]
× 1.47 V = 8.79[mV]
16.73[us]
From the above-mentioned result, the range of the VTH input
voltage is
∙Full speed
0.18VREG or less than,
∙ Rotational speed control
0.18VREG+8.79[mV] to 0.67VREG-8.79[mV],
∙ Motor stop
0.67VREG or more than
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LV8811G, LV8813G, LV8814J
A
∆ABC ~∆ADE
BC : DE = AC : AE
CPWM
h'
h'
VTH
Ө
h
D
→ t : t' = h : h'
E
h
t'
t
∴h'= ×h
t
Ө
PWM
B
t'
C
t
Pulse width(200ns and more)
2t'
Figure 47. Reference of the calculation of the VTH input range
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LV8811G, LV8813G, LV8814J
PARAMETER SETTING BY CONSTANT VOLTAGE
PH1, PH2 and MDS can be set by the external DC voltage
levels. PH1 and PH2 are used for setting the lead angle.
MDS is for setting minimum duty cycle. The input span of
these pins is 0 to 3V (VREG). The full scale is divided by
64 steps, thus the resolution is 47mV/step. Excluding the
lowest 3 steps and the highest 2 steps, the DC voltage is
translated to the parameters linearly. Hence, the linear
setting range is 0.141V to 2.906V. The voltage within the
lowest 3 steps (0 to 0.141V) selects the default value.
As for the highest 2 steps is below.
MDS
•Lowest 3 steps are FG cycle 1 electrical, and default
setting for MDS.
•Highest 2 steps is FG cycle 2 electrical, and default
setting for MDS.
PH1/PH2
•Highest 2 steps is prohibit.
(Figure 48)
MIN SET
0.141V
3/64 x VREG
MAX SET
2.906V
62/64 x VREG
0V
1.0V
2.0V
3.0V
VREG
1/3 VREG
2/3 VREG
VPH1[V]
VPH2[V]
VMDS[V]
64 step
3 step
Default setup
2 step
Prohibit
Adjustablerange (60 step)
PH1
-30deg
15deg
0deg
15deg
30deg
60deg
Lead angle axis intercepts[deg]
PH2
0.15deg/Hz
Lead angle gradients[deg/Hz]
0deg/Hz
0.15deg/Hz
0.3deg/Hz
FG freq 1/2
(Lead angle vs FG frequency)
14%
4%
Enable
6%
4%
2%
14%
6%
26%
6%
34%
6%
48% 14
6%
MDS
Hys 6% 1%
Minimum input duty [%]
Disable 8% 3%
8%
20%
28%
42% 8%
Figure 48. Pin-set PH1, PH2 and MDS
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LV8811G, LV8813G, LV8814J
SETTING MINIMUM PWM DUTY CYCLE
When the input PWM duty cycle is less than the minimum
duty cycle, which is set by MDS pin voltage, the output
duty cycle becomes 0%. And, this threshold has
hysteresis. In the meantime, MDS pin is also used for the
FG frequency setting.
(Figure 49, Figure 50)
0.282~
0.752
0.752~
2.906
VMDS range [V]
0~0.141 0.141~ 0.282
2.906 ~ 3.0
Minimum input duty cycle hysteresis [%]
Minimum input duty cycle for enable [%]
Minimum input duty cycle for disable [%]
FG cycle
6
14
8
1
4
6
6
15.9ꢐꢑꢒꢓ + 1.763
15.9ꢐꢑꢒꢓ + 1.763 − ℎꢔꢕ
1 electrical
14
8
2 electrical
Output Duty
Default setting
100%
<EXAMPLE>
Disable 8%
Enable 14%
VREG
MDS
MDS
48%
VMDS
47k
VMDS
47k
14%
8%
*
FG cycle
= 2 electrical
0%
VMDS[V]
0V
Ajustment
Range
VREG(3.0V)
141mV
(4%)
2.906V
(48%)
Figure 49. Example Setting Minimum PWM duty cycle (case of default setting)
Output Duty
100%
VREG
<EXAMPLE>
Disable 20%
Enable 26%
R
MDS_
47k
A
B
48%
VMDS
MDS
R
MDS_
47k
26%
20%
VMDS =
VREG * (RMDS_B / (RMDS_A + RMDS_B)) = 1/2 VREG
0%
VMDS[V]
0V
Ajustment
Range
VREG(3.0V)
141mV
(4%)
2.906V
(48%)
Figure 50. Example Setting Minimum PWM duty cycle (case of 1/2 VREG setting)
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LV8811G, LV8813G, LV8814J
SETTING LEAD ANGLE
PH1 and PH2 pin determine the optimum lead angle for a
specific speed range. PH1 provides lead angle at the low
speed, The PH2 pin provides lead angle slant for speed
(FG frequency). Both pins become the initial value in
GND. (Figure 51, Figure 52, Figure 53)
[
]
where ꢘ is FG frequency Hz
when VPH1 and ꢐꢜꢝ2 = 0
ꢙꢚ
ꢗ = 0.15[deg/Hz]
ꢛ = 15[deg]
Note: The equations above are based on the ideal case as a
reference for the user application design. It must be
readjusted by an experimental confirmation with the
actual movement and the motor to be used.
The lead angle P (typ.) is determined by the following
equation.
ꢖ = ꢗꢘ + ꢛ
ꢙꢚ
ꢗ = 0.1081ꢐꢜꢝ2 − 0.015
ꢛ = 32.54ꢐꢜꢝ1 − 34.58
Lead Angle[deg]
VPH1[V]
MAX
VPH1 = MAX
VPH2 = MAX
Lead Angle = A x fFG + B
A : Tuned from VPH2
B : Tuned from VPH1
<EXAMPLE (4-polemotor)>
Default setup
30Hz(450rpm) 20deg
100Hz(3000rpm) 30deg
200Hz(6000rpm) 45deg
120deg
Default
VPH1 = 0V
VPH2 = 0V
VPH1 = MAX
VPH2 = MIN
60deg
15deg
-30deg
VREG
Default setup
(100Hz, 30deg)
PH1
PH2
VPH1 = MIN
VPH2 = MAX
VPH1
VPH2
1/2
VREG
47k
47k
MIN
VPH1 = MIN
VPH2 = MIN
FG
Frequency[Hz]
0V
400Hz
20step
Figure 51. Example Setting Lead Angle (case of default setting)
Lead Angle[deg] VPH1[V]
<EXAMPLE (4-polemotor)>
Adjustment setup
30Hz(450rpm)
VPH1 = MAX
VPH2 = MAX
0deg
100Hz(3000rpm) 22deg
200Hz(6000rpm) 47deg
120deg
VPH1 = 1V
VPH2 = 2.4V
VREG
VREG
VPH1 = MAX
VPH2 = MIN
VREG
R
PH1_
30k
A
B
R
PH2_
11k
A
60deg
(100Hz, 22deg)
Fixed from
VPH2= 4/5 x VREG
VPH1
VPH2
PH1
PH2
R
PH1_
15k
RPH2_B
43k
1/3
VREG
0deg
FG
VPH1 = MIN
VPH2 = MIN
Frequency[Hz]
0V
VPH1 = VREG * (RPH1_B / (RPH1_A + RPH1_B)) = 1/3 VREG
VPH2 = VREG * (RPH2_B / (RPH2_A + RPH2_B)) = 4/5 VREG
-30deg
400Hz
20step
Figure 52. Example Setting Lead Angle (case of 1/3VREG and 4/5VREG setting)
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LV8811G, LV8813G, LV8814J
Sinusoidal PWM signals are generated from 1-hall signal, handling the lead angle parameters.
IN1 +
IN1 -
IN1
L
L
L
H
H
H
L
L
L
H
H
H
hall
comparator
Lead angle
FG
Max
UO
0%
Max
VO
0%
Max
WO
0%
Figure 53. Timing chart example: Lead Angle
Efficiency and sinusoidal waveform can be optimized by
changing the voltage levels of PH1 and PH2. First, adjust
PH1 in low speed (low PWM duty cycle) such as 20%. In
the examples below, VPH1 = ~1.5V is the best case for
efficiency and the shape of sinusoidal wave. After
optimizing VPH1, adjust VPH2 adjusted in high speed
(high PWM duty cycle) such as 100%.
(Figure 54)
PWM
FG
U-Out
Current
of U-Out
Input PWM duty-cycle 20%, VPH1 = 0.3V
Input PWM duty-cycle 20%, VPH1 = 1.5V
PWM
FG
U-Out
Current
of U-Out
Input PWM duty-cycle 100%, VPH2 = 2.8V
Figure 54. Relations of the lead angle and rotational speed, waveform and efficiency (Case of the LV8811G)
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31
LV8811G, LV8813G, LV8814J
PCB GUIDELINES
VCC AND GROUND ROUTING
RF ROUTING
Make sure to short-circuit VCC line externally by a low
impedance route on one side of PCB. As high current
flows into PGND, connect it to GND through a low
impedance route.
Power current (output current) flows through the RF line.
Make sure to short-circuit the line from VCC through RF
as well as VCC. The RF resistance must choose the
enough power rating.
The capacitance connected between the VCC pin and the
opposite ground is to stabilize the battery. Make sure to
connect an electrolytic capacitor with capacitance value
of about 10uF (4.7uF or greater) to eliminate low
frequency noise. Also, to eliminate high frequency noise,
connect a capacitor of superior frequency characteristics,
with capacitance value of about 0.1uF and make sure that
the capacitor is connected as close to the pin as possible.
Allow enough room in the design so the impact of PWM
drive and kick-back does not affect other components.
Especially, when the coil inductance is large and/or the
coil resistance is small, current ripple will rise so it is
necessary to use a high-capacity capacitor with superior
frequency characteristics. Please note that if the battery
voltage rises due to the impact of the coil kick-back as a
result of the use of diode for preventing the break down
caused by reverse connection, it is necessary to either
increase the capacitance value or place Zener diode
between the battery and the ground so that the voltage
does not exceed absolute maximum voltage.
NC PIN UTILIZATION
NC pins are not connected internally inside the LV8811G,
LV8813G, and LV8814J. If the NC pin has to be
connected to another pin for the development of the PCB
board, make sure to assign the pin using wires of stable
voltage and current with lower impedance value.
MOTOR DRIVER OUTPUT PINS
Since the pins have to tolerate surge of current, make sure
that the wires are thick and short enough when designing
the PCB board.
THERMAL TEST CONDITIONS
Size: 57.0mm × 57.0mm × 1.6mm (Double layer PCB)
Material: Glass epoxy
Copper wiring density: L1 = 80% / L2 = 85%
RECOMMENDATION
When the electrolytic capacitor cannot be used, add the
resistor with the value of about 1Ω (R20) and a ceramic
capacitor with the capacitor value of about 10μF (C20) in
series for the alternative use. When the battery line is
extended, (20-30 cm to 2-3 m), the battery voltage may
overshoot when the power is supplied due to the impact of
the routing of the inductance. Make sure that the voltage
does not exceed the absolute maximum standard voltage
when the power supply turns on.
The thermal data provided is for the thermal test condition
where 95% or more of the exposed die pad is soldered.
It is recommended to derate critical rating parameters for
a safe design. Electrical parameters that are recommended
to be derated are operating voltage, operating current,
junction temperature, and device power dissipation. The
recommended derating for a safe design is as shown
below:
These capacitance values are just for reference, so the
confirmation with the actual application is essential to
determine the values appropriately.
Maximum 80% or less for operating voltage
Maximum 80% or less for operating current
Maximum 80% or less for junction temperature
EXPOSED PAD
Check solder joints and verify reliability of solder joints
for critical areas such as exposed die pad, power pins and
grounds.
Any void or deterioration, if observed, in solder joint of
these critical areas parts, may cause deterioration in
thermal conduction and that may lead to thermal
destruction of the device.
The exposed pad is connected to the frame of the
LV8811G, LV8813G, and LV8814J. Therefore, do not
connect it to anywhere else other than ground. If GND and
PGND are in the same plane, connect the exposed pad to
the ground plane. Else, if GND and PGND are separated,
connect the exposed pad to GND.
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32
LV8811G, LV8813G, LV8814J
L1 : Copper wiring pattern diagram (top)
L2 : Copper wiring pattern diagram (bottom)
Figure 55. Pattern Diagram of Top and Bottom Layer
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33
LV8811G, LV8813G, LV8814J
PACKAGE DIMENSIONS
Figure 56 LV8811G and LV8813G Package
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34
LV8811G, LV8813G, LV8814J
Figure 57 LV8814J Package
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35
LV8811G, LV8813G, LV8814J
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36
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