LV24250LS-TLM-E [ONSEMI]
1 芯片调频 (FM) 调谐集成电路，用于紧凑型便携设备;
| 型号： | LV24250LS-TLM-E |
| 厂家： | 
ONSEMI |
| 描述： | 1 芯片调频 (FM) 调谐集成电路，用于紧凑型便携设备 信息通信管理 商用集成电路 |
| 文件： | 总18页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1699B
LV24250LS
Bi-CMOS LSI
1-Chip FM Tuner IC
for Compact Portable Equipment
http://onsemi.com
Overview
The LV24250LS is an I2C-controlled single-chip FM tuner IC that integrates external components which are necessary
for tuning in a compact VQLP package with dimensions of only 3.5mm×3.5mm.
Features
FM FE
FM IF
MPX stereo decoder
FLL Tuning
Standby
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Symbol
Conditions
Analog block supply voltage
Digital block supply voltage
SCL, SDA, Int
Ratings
Unit
V
Maximum supply voltage
V
max
5.0
4.0
CC
DD
V
V
max
V
Maximum input voltage
1 max
V
V
+0.3
+0.3
140
V
IN
DD
V
2 max
External_clk_in
V
IN
DD
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta 70C *
mW
C
C
-20 to +70
Tstg
-40 to +125
* : When mounted on the specified printed circuit board (40.0mm × 50.0 mm × 0.8mm), Four layers glass epoxy (2S2P)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
June, 2013
60811 SY/60910 SY/42810 SY 201003265-S00003 No.A1699-1/18
LV24250LS
Operating Conditions at Ta = 25C
Parameter
Symbol
Conditions
Analog block supply voltage
Digital block supply voltage
Ratings
Unit
V
Recommended supply voltage
V
3.0
3.0
CC
V
V
DD
Operating supply voltage range
V
V
op
op
op
2.6 to 3.6
2.5 to 3.6
2.2 to 3.6
V
CC
V
DD
V
Interface voltage
V
IO
Note : Supply voltage V equal V , or V ≤ V
IO DD IO DD
& V ≥ 2.2 V
IO
* Stabilize the service voltage so as not to cause the voltage change by the noise etc.
Operating Characteristics at Ta = 25°C, V
= 3.0V, V
= 3.0V, Volume =15/16, Soft Mute = 1/Soft Stereo = off
DD
CC
with the designated test circuit
Output level set with Radio Control 1 of control register map (0Dh Bit0, Bit1,Bit5 set to ‘1’, ‘1’)
Control 2 of control register map (0Dh Bit1 set to ‘1’)
In addition, Set IF_OSC = 170kHz, IF_BW = 100% (Radio Control 1 : 0D Bit6, Bit7 set to ‘1’, ’1’)
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Current drain
I
A
D
A
D
Analog block at 60dBV EMF input
Digital block at 60 dBV EMF input
Analog standby mode
12
0.3
3
17
mA
mA
A
CC
(in operation)
I
0.8
30
CC
Current drain
(in standby)
I
CC
I
Digital standby mode
3
30
A
CC
FM receive band
F_range
Refer to PCB mounting conditions to cover
the FM receive band of 76M to 108MHz
76
108
MHz
FM receive characteristics; MONO : fc = 80MHz, fm = 1kHz, 22.5kHzdev. Note that Soft_mute = 1, Soft_stereo function OFF, IHF-BPF used
3dB sensitivity
-3dB LS
60dBV, 22.5kHzdev output standard,
-3dB input.
5
17
dBV
EMF
dBV
EMF
V
Practical sensitivity 1
Practical sensitivity 2 (Reference)
QS1
Input at S/N = 30dB
8
16
De-emphasis = 75s, SG open display
Input at S/N = 26dB
QS2
1.10
De-emphasis = 75s, SG terminal display
60dBV EMF, pin 19 output
Demodulation output
Channel balance
Vo
CB
80
-2
110
0
160
2
mVrms
dB
60dBV EMF, pin 18 output/pin 19 output
60dBV EMF, pin 19 output
Signal-to-noise ratio
S/N
48
58
0.4
dB
Total harmonic distortion 1
(MONO)
THD1
60dBV EMF, pin 19 output, 22.5kHz dev.
1.5
3
%
Total harmonic distortion 2
(MONO)
THD2
FS
60dBV EMF, pin 19 output, 75.0kHz dev.
1.3
10
%
Field intensity display level
Reg1Dh_bit0 = OFF
3
20
dBV
Input level at which Reg02h_bit1-3 change
from 1 to 2.
EMF
Mute attenuation
Mute-Att.
60dBV EMF, pin 19 output
60
70
dB
FM receive characteristics ; STEREO characteristics : fc = 80MHz, fm = 1kHz, V = 60dBV EMF, Pilot = 10% (7.5kHzdev), MPX-Filter used
IN
Separation
SEP
L-mod, pin 19 / pin 18 output
20
35
dB
%
L+R signals = 30% (22.5kHz dev.)
Main-mod (for L + R input), 19 output
IHF_BPF L+R signals = 30% (22.5kHzdev.)
Total harmonic distortion (Main)
THD-ST1
0.6
1.8
Interface block allowable operation range at Ta = -20 to +70C, V = 0V
SS
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Supply voltage
V
2.5
3.6
V
V
DD
Digital block input
V
High-level input voltage range
Low-level input voltage range
Output current at Low level
Output voltage at Low level I
0.7V
V
IH
DD
0
DD
V
0.1V
V
IL
DD
Digital block output
I
2.0
mA
V
OL
V
= 2mA
OL
0.6
OL
External clock operating frequency
fclk_ext
Clock frequency for external input
32k
32.768k
20M
Hz
Note : External clock input (pin 12) allows also input of the sine wave signal.
No.A1699-2/18
LV24250LS
Package Dimensions
unit : mm (typ)
3393
TOP VIEW
3.5
SIDE VIEW
BOTTOM VIEW
(0.1)
0.35
2
1
(0.75)
0.2
SIDE VIEW
VQLP24J(3.5X3.5)
Pin Assignment
18 17 16 15 14 13
Line_out_L
Package-GND
Package-GND
Package-GND
Package-GND
GND
Ext_CLK_IN
Package-GND
Package-GND
Package-GND
Package-GND
SCL
19
20
21
22
23
24
12
11
10
9
8
7
1
2
3
4
5
6
Top view
No.A1699-3/18
LV24250LS
Block Diagram
18
17
16
15
14
13
Voltage
Line_out_L
Package_GND
Package_GND
Package_GND
Ext_CLK_IN
Package_GND
Package_GND
Package_GND
Package_GND
SCL
19
20
21
22
12
11
10
9
Stabilizer
To
Each Block
Line SW
Buffer
AMP
And
Mute
FM
Stereo
De-
emphasis
Demodulator
Decorder
FM Selectivity
Filter
Tuning
System
FLL
Tuning
Power
Manage
ment
RF and FM
Quadrature
Mixer
Package_GND 23
8
Quadrature
Oscillator
Digital Interface
I2C Conversion
To
Each
Block
24
7
GND
To
Each Block
1
2
3
4
5
6
No.A1699-4/18
LV24250LS
Pin Function
Pin No.
Pin name
Description
Antenna input
Pin voltage
1V
Internal equivalent circuit
Mixer
1
2
FM-ANT1
FM-ANT2
Vstabi
For pin 1 single input, pin 2 is set
to AC_GND via capacity
ANT1
1
1V
1V
Vstabi
ANT2
2
1V
1V
Mixer
3
V
Digital interface supply voltage
Power pin dedicated to the
interface input/output elements
V
I/O
V
I/O
DD
V_I/O
3
to each interface block
4
5
V
Digital supply voltage
V
DD
DD
V
DD
4
Power pin for digital block
to each logic block
INT
Interrupt line
V
V
DD
IO
Output pin dedicated to interrupt
(hardware output: used for
options)
INT
5
6
SDA
Digital interface DATA ine
Bidirectional data line. Pull up to
Vio line with 3.3kΩ to 10kΩ
resistor
V
IO
V
DD
data
6
data
7
SCL
Digital interface Clock line
V
DD
V
IO
SCL
7
8
Package-GND
Ext_CLK_IN
GND for package-shield
(GND)
9
BND pin for package shield
10
11
12
Reference clock-source input
for measurement
V
DD
V
IO
External standard CLK input pin.
CLK
12
Continued on next page.
No.A1699-5/18
LV24250LS
Continued from preceding page.
Pin No.
13
Pin name
Description
Pin voltage
Supplement
V
Analog supply voltage
Power pin for analog (tuner)
block
V
V
CC
CC
CC
13
to each V
block
CC
26V
Bias Regulater
14
Vstabi
Stabilizer voltage
2.6V
.
V
CC
Local oscillator reference bias
pin. NC pin to be used
Vstabi. line for
each block
V
CC
2.6V
Bias Regulater
14
13
OSC block
15
16
. NC
Keep this open
FLL_LPF
LPF for FLL
Vstabi
LPF pin for noise decrease when
FLL operates. Capacity(0.47μF
to 1.0μF) is added this pin and
between Vstabi pin of 14pin. NC
pin to be used
16
17
MPX_OUT
MPX-signal output
2.3V
Vstabi
Stereo decoder input monitor pin.
NC pin to be used
17
18
19
LINE-OUT-R
LINE-OUT-L
Package-GND
GND
Radio Rch Line-output
Audio R_ch output
1.2V
1.2V
Vstabi
Vstabi
18
19
Radio Lch Line-output
Audio L_ch output
20
21
22
23
24
GND for package-shield
(GND)
(GND)
GND pin for package shield
GND (Analog and Digital GND)
GND pin for analog (FM tuner)
block and digital (control) block
No.A1699-6/18
LV24250LS
Format of Bus Transfers
Bus transfers are primarily based on the I2C primitives
Start condition
Repeated start condition
Stop condition
Byte write
Byte read
Start, restart, and stop conditions are specified as shown in Table 1 below.
Start
Repeated start
Stop
SCL
SDA
SCL
SCL
SDA
SDA
Fig. 1 the I2C start, repeated start and stop conditions.
For details, like timing, etc., refer to specifications of I2C.
8-bit write
8-bit data is sent from the master microcomputer to LV24250LS.
Data bit consists of MSB first and LSB last.
Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC.
Do not change data while SCL remains HIGH.
LV24250LS outputs the ACK bit between eighth and ninth falling edges of SCL
SCL
D7
D6
D5
D4
D3
D2
D1
D0
Ack
SDA
Fig. 2 Signal pattern of the I2C byte write
Read is of the same form as write, only except that the data direction is opposite.
Eight data bits are sent from LV24250LS to the master while Ack is sent from the master to LV24250LS.
SCL
D7
D6
D5
D4
D3
D2
D1
D0
Ack
SDA
Fig. 3 Signal pattern of the I2C byte read
The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV24250LS in
synchronization with the falling edge while the master side performs latching at the rising edge.
No.A1699-7/18
LV24250LS
LV24250LS latches ACK at the rising edge.
The sequence to write data D into the register A of LV24250LS is shown below.
Start condition
write the device address (C0h)
write the register address, A
write the target data, D
stop condition
start
write device address
SCL
SDA
Ack
DA7
DA6...1
write register address
write data byte
stop
Ack
Ack
A7
A6...1
D7
D6...0
Fig. 4 Register write through I2C
When one or more data has been provided for writing, only the first data is allowed to be written.
Read sequence
start condition
write the device address (C0h)
write the register address, A
repeated start condition (or stop + start in a single master network)
write the device address + 1 (C1h)
read the register contents D, transmit NACK (no more data to be read)
stop condition
start
write device address
write register address
rep.
SCL
SDA
Ack
Ack
DA7
DA6...1
A7
A6...0
start
write device address + 1
read data byte with NACK
stop
Ack
DA7
DA6...1
D7
D6...0
Fig. 5 Register read through I2C
Interrupt Pin INT
LV24250LS has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected.
The INT output pin is kept floating while the PWRAD bit is cleared during initialization.
Therefore, to avoid influence on the CPU side during initialization, it is recommended to secure the non-active state by
means of the pull-up or pull-down resistor.
This enables direct INT output connection to non-masking interruption of the host CPU.
No.A1699-8/18
LV24250LS
Digital interface specification (interface specification : reference)
(1). Characteristics of SDA and SCL bus line relative to the I2C bus interface
START Condition
Repeated START
T
LOW
T
HIGH
Tf
Tr
SCL
SDA
Tf
Tr
T
HD;STA
T
T
T
SU;STA
HD;DAT
SU;DAT
Standard-mode
0
High_Speed-mode
min max
Parameter
SCL clock frequency
Symbol
unit
min
max
F
100
300
0
20+0.1Cb
20+0.1Cb
0.6
400
300
300
kHz
ns
ns
s
s
s
s
s
s
ns
s
pF
SCL
Fall time of both SDA and SCL
Rise time of both SDA and SCL
High time of SCL
Tf
Tr
1000
T
4.0
4.7
4.0
0
HIGH
Low time of SCL
T
1.3
LOW
Hold time of STAT condition
Hold time of Data
T
0.6
HD ; STA
T
3.45
400
0
0.9
HD ; DAT
Set-up time of STAT condition
Set-up time of STOP condition
Set-up time of Data
T
4.7
4.0
250
4.7
0.6
SU ; STA
T
0.6
SU ; STO
T
100
SU ; DAT
Bus free time between a STOP and
Capacitivie load for each bus line
T
1.3
BUF
Cb
400
*Cb = Total capacitance of one bus line
(2). Register map (On Register Map)
Following is Sub address map of LV24250LS. Each register becomes 8-bit constitution.
Address
Register Name
Mode
R/W
R
Remark
00h
CHIP_ID
Chip ID
02h
RADIO_STAT
RFCAP
Status of Radio Station
RF Cap bank
0Bh
0Dh
0Eh
0Fh
10h
R/W
R/W
R/W
R/W
R
RADIO_CTRL1
RADIO_CTRL2
RADIO_CTRL3
TNPL
Radio Control 1
Radio Control 2
Radio Control 3
Tune Position Low
11h
TNPH_STAT
REF_CLK_PRS
REF_CLK_DIV
REF_CLK_OFF
SCN_CTRL
R
Tune Position High and Status
Reference clock pre-scalar
Reference clock divider
Reference clock offset
Scan control
19h
R/W
R/W
R/W
R/W
R/W
R/W
1Ah
1Bh
1Dh
1Eh
1Fh
TARGET_VAL_L
TARGET_VAL_H
Target value Low
Target value High
R : Read only register R/W : Read and Write register
No.A1699-9/18
LV24250LS
(3). Register description (ON Contents of each Register)
Register 00h – CHIP_ID – Chip identify register (Read/Write)
7
6
5
4
3
2
1
0
ID [7 : 0]
bit 7-0 :
ID [7 : 0] : 8-bit chip ID.
LV24250LS : 15h
Note : To abort the command, write any value in this register.
Register 02h – RADIO_STAT – Radio station status (Read-Only)
7
6
5
4
3
2
1
0
RAD_IF
N/A
N/A
MO_ST
FS [2 : 0]
SF5DB
bit 7 :
RAD_IF : Radio interrupt flag.
0 = no interrupt
1 = interrupt
Note :
When status (field strength, stereo/mono) changes, this bit is set.
If Interrupt of IRQ pin is enabled, Interrupt pin is set by following IPOL register condition.
This bit is cleared by register read. In stand-by mode (PW_RAD = 0), this bit is 1
bit 6-5 :
NA [1 : 0] : NA 0 fixed
bit 4 :
MO_ST : Mono/stereo indicator
0 = Forced monaural
1 = Normal (Receiving in stereo mode)
bit 3-1
FS [2 : 0] : Fieldstrength :
0 = Low field strength
…
7 = High field strength
bit 0 :
SF5DB : Fieldstrength +5dB :
0 = FS5dB no UP
1 = FS5dB UP
For details, refer to Application note.
Register 0Bh – RFCAP – RF Cap bank (Read/Write)
7
6
5
4
3
2
1
0
RFCAP [7 : 0]
bit 7-0 :
RFCAP [7 : 0] : RF Oscillator CAP bank
No.A1699-10/18
LV24250LS
Register 0Dh – RADIO_CTRL1 – Radio control 1 (Read/Write)
7
6
5
4
3
2
1
0
IF_SEL
IFBWSEL
AGC_SPD
DEEM
ST_M
nMUTE
VOL [1 : 0]
bit 7 :
IF_SEL : IF Frequency Setting
0 = 150kHz
1 = 170kHz
bit 6 :
IFBWSEL : IF band width setting
0 = 50%
1 = 100%
bit 5 :
bit 4 :
VOL_2 : Volume setting
For details, refer to Bit0,1 for RADIO_CTRL1
DEEM : de-emphasis
0 = 50s : Korea, China, Europe, Japan
1 = 75s : USA
bit 3 :
ST_M : Stereo/mono setting
0 = Stereo enabled
1 = Stereo disabled (mono mode)
bit 2 :
nMUTE : Audio Mute
0 = Mute On
1 = Mute Off
bit 1-0 :
VOL [1 : 0] : Volume Setting
* It controls by Bit5 of RADIO_CTRL1 and combination 4Bit with Bit1 of RADIO_CTRL2.
Vol_3 Vol_2 Vol_1 Vol_0
0
0
0
0
0
0
0
0
1
0 : Minimum level
1
0
…
1
1
1
1 : Max level
Register 0Eh – RADIO_CTRL2 – Radio control 2 (Read/Write)
7
6
5
4
3
2
1
0
SOFTST [2 : 0]
SOFTMU [2 : 0]
N/A
STABI_BP
bit 7-5 :
SOFTST [2 : 0] : Soft Stereo setting
000b = Soft stereo level 3
001b = Disable soft stereo
010b = Soft stereo level 1 (*)
100b = Soft stereo level 2
Note : do not use without these value.
(*) : recommended setting
bit 4-2 :
SOFTMU [2 : 0] : Soft audio mute setting
000b = Soft audio mute level 3
001b = Disable soft audio mute
010b = Soft audio mute level 1
100b = Soft audio mute level 2 (*)
Note : do not use without these value.
(*) : recommended setting
bit 1 :
bit 0 :
VOL_3 : Volume setting
For details, refer to Bit0,1 for RADIO_CTRL1
STABI_BP : Internal regulator by-pass bit
0 = Internal regulator operate (normal)
1 = Internal regulator by-pass
No.A1699-11/18
LV24250LS
Register 0Fh – RADIO_CTRL3 – Radio control 3 (Read/Write)
7
6
5
4
3
2
1
0
IPOL
SM_IE
RAD_IE
SD_PM
nIF_PM
EXT_CLK_CFG [1 : 0]
PW_RAD
bit 7 :
IPOL : Interrupt (IRQ) Polarity
0 = IRQ active high
1 = IRQ active low
bit 6 :
bit 5 :
bit 4 :
bit 3 :
bit 2-1 :
SM_IE : Command end interrupt
0 = Disable
1 = Enable
RAD_IE : Radio Interrupt (field strength/stereo changes)
0 = Disable
1 = Enable
SD_PM : Stereo decoder clock PLL mute
0 = SD PLL On (Normal Operation)
1 = SD PLL Off (Adjustment)
nIF_PM : IF PLL mute
0 = IF PLL Off (Adjustment)
1 = IF PLL On (Normal Operation)
EXT_CLK_CFG [1 : 0] : External Clock Setting
EXT_CLK_CFG [1 : 0]
Reference clock
Off
00
01
10
NA:Do not use
Oscillator clock source / 32
(for high frequency source)
Oscillator clock source
11
(for low frequency source)
bit 0 :
PW_RAD : Radio Circuit Power
0 = Power Off (Stand-by).
1 = Power On
Note : At the time of start, PW_RAD becomes 0 (Stand-by)
Register 10h – TNPL – Tune position low (Read-Only)
7
6
5
4
3
2
1
0
TUNEPOS [7 : 0]
TUNEPOS [7 : 0] : Current RF Frequency (Low 8bit)
bit 7-0 :
No.A1699-12/18
LV24250LS
Register 11h – TNPH_STAT – Tune position high/status (Read-Only)
7
6
5
4
3
2
1
0
ERROR [2 : 0]
SM_IF
TUNED
NA
TUNEPOS [9 : 8]
bit 7-5 :
ERROR [2 : 0] : Error Code
ERROR [2 : 0]
Remark
0
1
2
3
6
7
OK, Command end (No Error)
Default value after or during reset
Band Limit Error
DAC Limit Error
Command forced End
Command busy
bit 4 :
SM_IF : Command End interrupt flag
0 = No Interrupt
1 = Interrupt
This bit is set when the command is over. When the IRQ pin interrupt is allowed, the pin status is changed, Reading this register causes clearing.
bit 3 :
TUNED : Radio tuning Flag
0 = No tune
1 = Tuned
Note : This flag is set when Tuned or a station search succeeded.
This flag is cleared under 3 conditions as below.
(1) PW_RAD = 0
(2) Tuning Frequency
(3) FM station searching
bit 2 :
NA : 0 (Fix)
bit 1 : 0 :
TUNEPOS [9 : 8] : Current RF frequency (High 2 bit)
Register 19h – REF_CLK_PRS – Reference clock prescaler (Read/Write)
7
6
5
4
3
2
1
0
REFPRE [2 : 0]
REFMOD [4 : 0]
bit [7 : 5] :
REFPRE [2 : 0] : Reference Clock pre- scaler
0 = 1 : 1
1 = 1 : 2
…
7 = 1:128
bit [4 : 0] :
REFMOD [4 : 0] : 5-bit slope correction
Register 1Ah – REF_CLK_DIV – Reference clock divider (Read/Write)
7
6
5
4
3
2
1
0
REFDIV [7 : 0]
Bit 7-0 :
REFDIV [7 : 0] : Reference Clock Divider
0 : Divider Value = 1
1 : Divider Value = 2
…
255 : Divider Value = 256
Register 1Bh –REF_CLK_OFF – Reference clock offset (Read/Write)
7
6
5
4
3
2
1
0
REFOFFS [7 : 0]
REFOFFS [7 : 0] : Offset register for the spread of reference clock
Bit 7-0 :
No.A1699-13/18
LV24250LS
Register 1Dh – SCN_CTRL – Scan control (Read/Write)
7
6
5
4
3
2
1
0
GRID [1 : 0]
FLL_ON
FLL_MODE
FS [2 : 0]
SHF5DB
bit 7-6 :
GRID [1 : 0] : FM station search frequency interval :
0 = IFSD set
1 = 50kHz grid
2 = 100kHz grid
3 = 200kHz grid
bit 5 :
FLL_ON : FLL Control
0 = FLL OFF
1 = FLL ON
During setting of the FM frequency and during seek, keep this OFF. Turn it ON after tuning.
bit 4 :
Reserved : 0 (Fix)
However, '1' is set when capacity is added to 16pin, and it uses it as Smoothing Filter(FLL_LPF).
bit 3-1 :
FS [2 : 0] : Field strength setting at the time of FM station search and a frequency adjustment bit
Set 1 for setting of IFSD.
bit 0 :
SHF5DB : Scan stop level +5dB
Register1Eh – TARGET_VAL_L – Target Value Low Register (Read/Write)
7
6
5
4
3
2
1
0
TARGET [7 : 0]
TARGET [7 : 0] : Target frequency low 8 bit :
Tuning frequency or Limit Frequency for FM Station Search
bit 7-0 :
Register 1Fh – TARGET_VAL_H – Target Value High Register (Read/Write)
7
6
5
4
3
2
1
0
TARGET [15 : 8]
TARGET [15 : 8] : Target frequency High 8 bit :
bit 7-0 :
Target value of oscillator calibration, Tuning frequency value or limit frequency value for station search
Note : GRID [1 : 0] is not 0 TARGET [15 : 14] has different definition
With radio power ON, lower eight bits of the target frequency are set. Then, set higher eight bits of the target frequency to this register. The command is
executed.
No.A1699-14/18
LV24250LS
Test Circuit
Line_out_R
Line_out_L
+
SW
V
CC
18 17 16 15 14 13
External_CLK_IN
Voltage
Source
19
20
21
22
23
24
12
11
10
9
Top View
Package
GND
Package
GND
8
SCL
GND
7
1
2
3
4
5
6
FM_ANT
1000pF
1000pF
V
IO
Voltage
Source
SW
V
DD
I2C_Bus
MPU
Voltage
Source
SW
No.A1699-15/18
LV24250LS
Application Circuit
Not necessary
when the CD cut capacity
is on the receive side
Line_out_R
+
Changeover of resistor
possible depending on the
state of power supply
SW
V
CC
18 17 16 15 14 13
External_CLK_IN
Voltage
Source
19
12
11
10
9
Line_out_L
20
21
22
23
24
Top View
Package
GND
Package
GND
8
SCL
GND
7
1
2
3
4
5
6
FM_ANT
100 to
1000pF
R1 R2 R3
R4
27pF
47pF
120nH
Winding type
R6
R5
V
DD
Voltage
Source
SW
Changeover of resistor
possible depending on the
state of power supply
I2C_Bus
MPU
Voltage for I2C
interface pull-up
Cautions for mounting of IC
Note1 : For external part constant, the recommended value is described. Since the constant may differ during actual use
with the set mounted, be sure to consider optimization.
Note2 : The single input antenna application has been described. The difference input is also possible (The signal input
from 1pin and 2pin: Refer to the application note for details).
Note3 : If the spike noise between MPU and IC is large during communication, it is recommended to add limiting
resistors R1, R2, and R3 between MPU and IC. 0 at 1.8V.
Note4 : To reduce noise from power supply, add a capacitor between V
- GND and between V
- GND.
CC
DD
Note5 : The I2C bus communication line requires pull-up resistors R5 and R6. The commonly-employed resistance value
is 4.7k (4.7k to 10k). Set the pull-up voltage to the same one of V of LV24250LS. (Supply from the same
IO
source as V and V
is recommended.
IO
DD
Note6 : Please use the INT pin arbitrarily. Recommended to open when unused.
The INT pin becomes unstable at IC startup. To protect MPU from any effects during startup, it is recommended
to add either the pull-up or pull-down resistor to set the non-active mode. (This is not necessary when the MPU
can be set to non-active by a software during initialization.
No.A1699-16/18
LV24250LS
PCB Mounting Conditions to cover the FM Receiving Area of 76M to 108MHz
LV24250LS's PCB mounting conditions
LV24250LS
Printed Circuit Board
X = 0mm
LAYER
LV24250LS has an inductor for local oscillator on the package bottom side.
In order to cover the receiving frequency range of 76MHz to 108MHz, provide the GND layer to the first layer of
Side A of PCB that is directly below the package bottom side, as shown in the figure.
Recommended layout of PCB substrate
3.50 × 3.50
3.50 × 3.50
PCB GND Layer
0.57
0.79
0.55
X = 2.40
0.55
2.64
IC backside_LV24250LS
IC directly-below_PCB recommended
GND patten diagram
With this SPL, the receiving frequency is measured under the following conditions :
The X-value can be set freely between Min = 2.00mm and Max = 2.60mm with reference to IC.
(The X-value for Our Demo Board is 2.4mm.)
The Y-value can be set freely between Min = 1.00mm and Max = 2.40mm with reference to IC.
(The Y-value for Our Demo Board is 2.30mm.)
Avoid providing another wiring within 0.4mm of bottom layer of PCB_GND as much as possible.
No.A1699-17/18
LV24250LS
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PS No.A1699-18/18
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