LE25FU106BMA_技术文档

Ordering number : EN*A1140A

CMOS IC

LE25FU106B

1M-bit (128K

×

8) Serial Flash Memory

Overview

The LE25FU106B is a serial interface-compatible flash memory device with a 128K × 8-bit configuration. It uses a

single 2.5V power supply for both reading and writing (program and erase functions) and does not require a special

power supply. As such, it can support on-board programming. It has three erase functions, each of which corresponds to

the size of the memory area in which the data is to be erased at one time: the small sector (4K bytes) erase function, the

sector (32K bytes) erase function, and the chip erase function (for erasing all the data together). The memory space can

be efficiently utilized by selecting one of these functions depending on the application. A page program method is

supported for data writing. The page program method of the LE25FU106B can program any amount of data from 1 to

256 bytes. The program time of 2.0ms (typ.) when programming 256 bytes (1 page) at one time makes for fast data

writing. While making the most of the features inherent to a serial flash memory device, the LE25FU106B is housed in

an 8-pin ultra-miniature package. Serial flash memory devices tend to be at a disadvantage in terms of their read speed,

but the LE25FU106B has maximally eliminated this speed-related disadvantage by supporting clocks with frequencies up

to 30MHz under SPI bus specifications. All these features make this device ideally suited to storing program codes in

applications such as portable information devices and small disk systems, which are required to have increasingly more

compact dimensions.

Features

• Read/write operations enabled by single 2.5V power supply: 2.30 to 3.60V supply voltage range

• Operating frequency

• Temperature range

: 30MHz

50MHz (at the planning stage)

: 0 to 70°C

–40 to +85°C (at the planning stage)

Continued on next page.

* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by

SANYO Semiconductor Co., Ltd.

Jan-2011, Rev. 0

www.onsemi.com

Publication Order Number:

LE25FU106B/D

LE25FU106B

Continued from preceding page.

• Serial interface

• Sector size

: SPI mode 0, mode 3 supported

: 4K bytes/small sector, 32K bytes/sector

• Small sector erase, sector erase, chip erase functions

• Page program function (256 bytes/page)

• Block protect function

• Highly reliable read/write

Number of rewrite times: 10,000 times

Small sector erase time : 40ms (typ.), 150ms (max.)

Sector erase time

Chip erase time

: 60ms (typ.), 200ms (max.)

: 140ms (typ.), 1.4s (max.)

Page program time

• Status functions

: 2.0ms/256 bytes (typ.), 2.5ms/256 bytes (max.)

Ready/busy information, protect information

• Data retention period

• Package

: 20 years

: LE25FU106BTT MSOP8 (225mil)

: LE25FU106BMA MFP8 (225mil)

Package Dimensions

unit:mm (typ)

Package Dimensions

unit:mm (typ)

3276

[LE25FU106BTT]

3032E

[LE25FU106BMA]

5.2

5.0

8

5

8

1

2

1

4

(0.6)

1.27

0.15

0.35

(0.7)

1.27

0.35

0.125

SANYO : MFP8(225mil)

SANYO : MSOP8(225mil)

Figure 1 Pin Assignments

CS

1

2

3

4

8

7

6

5

V

DD

HOLD

SCK

SI

SO

WP

V

SS

Top view

MSOP8 (LE25FU106BTT)

MFP8 (LE25FU106BMA)

Rev. 0 | Page 2 of 21 | www.onsemi.com

LE25FU106B

Figure 2 Block Diagram

1M Bit

X-

Flash EEPROM

Cell Array

DECODER

ADDRESS

BUFFERS

&

LATCHES

Y-DECODER

I/O BUFFERS

&

DATA LATCHES

CONTROL

LOGIC

SERIAL INTERFACE

SCK

SI

SO

CS

WP

HOLD

Table 1 Pin Description

Symbol

SCK

Pin Name

Serial clock

Description

This pin controls the data input/output timing.

The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is

output synchronized to the falling edge of the serial clock.

SI

Serial data input

The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the

serial clock.

SO

CS

Serial data output

Chip select

The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock.

The device becomes active when the logic level of this pin is low; it is deselected and placed in standby

status when the logic level of the pin is high.

WP

Write protect

Hold

The status register write protect (SRWP) takes effect when the logic level of this pin is low.

HOLD

Serial communication is suspended when the logic level of this pin is low.

This pin supplies the 2.30 to 3.60V supply voltage.

This pin supplies the 0V supply voltage.

V

Power supply

Ground

DD

V

SS

Rev. 0 | Page 3 of 21 | www.onsemi.com

LE25FU106B

Table 2 Command Settings

Command

1st bus cycle

2nd bus cycle

A23-A16

3rd bus cycle

A15-A8

4th bus cycle

5th bus cycle

X

6th bus cycle

Nth bus cycle

Read

03h

0Bh

D7h

D8h

C7h

02h

06h

04h

B9h

05h

01h

9Fh

ABh

A7-A0

A23-A16

A15-A8

Small sector erase

Sector erase

A23-A16

A15-A8

A23-A16

A15-A8

Chip erase

Page program

A23-A16

A15-A8

A7-A0

PD *1

Write enable

Write disable

Power down

Status register read

Status register write

Read silicon ID 1 *2

Read silicon ID 2 *3

Exit power down mode

DATA

X

A7-A0

Explanatory notes for Table 2

"X" signifies "don't care" (that is to say, any value may be input).

The "h" following each code indicates that the number given is in hexadecimal notation.

Addresses A23 to A17 for all commands are "Don't care".

In order for commands other than the read command to be recognized, CS must rise after all the bus cycle input.

*1: "PD" stands for page program data. Any amount of data from 1 to 256 bytes in 1-byte unit is input.

*2: Of the two silicon ID commands, it is for the command with the 9Fh setting that the manufacturer code 62h is first

output. For as long as the clock input is continued, 1Dh of the device code is output continuously, followed by the

repeated output of 62h and 1Dh.

*3: Of the two silicon ID commands, it is for the command with the ABh setting that manufacturer code 62h is first

output when address A0 is "0", and the device code 1Dh is first output when address A0 is "1".

Addresses A7 to A1 are "don't care". For as long as the clock input is continued, 62h and 1Dh are repeatedly

output.

Rev. 0 | Page 4 of 21 | www.onsemi.com

LE25FU106B

Device Operation

The LE25FU106B features electrical on-chip erase functions using a single 2.5V power supply, that have been added to

the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are facilitated by

incorporating the command registers inside the chip. The read, erase, program and other required functions of the

device are executed through the command registers. The command addresses and data input in accordance with "Table

2 Command Settings" are latched inside the device in order to execute the required operations. "Figure 3 Serial Input

Timing" shows the timing waveforms of the serial data input. First, at the falling CS edge the device is selected, and

serial input is enabled for the commands, addresses, etc. These inputs are introduced internally in sequence starting with

bit 7 in synchronization with the rising SCK edge. At this time, output pin SO is in the high-impedance state. The

output pin is placed in the low-impedance state when the data is output in sequence starting with bit 7 synchronized to

the falling clock edge during read, status register read and silicon ID. Refer to "Figure 4 Serial Output Timing" for the

serial output timing.

The LE25FU106B supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is

automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of

SCK is high.

Figure 3 Serial Input Timing

t

CPH

CS

t

CLH

CLS

CSS

CLHI

CLLO CSH

SCK

t

DH

DS

SI

DATA VALID

High Impedance

SO

Figure 4 Serial Output Timing

CS

SCK

t

CHZ

CLZ

HO

SO

SI

DATA VALID

t

V

Rev. 0 | Page 5 of 21 | www.onsemi.com

LE25FU106B

Description of Commands and Their Operations

"Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions and

operations corresponding to each command is presented below.

1. Read

There are two read commands, the 4 bus cycle read command and 5 bus cycle read command. Consisting of the first

through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h), and the data in the

designated addresses is output synchronized to SCK. The data is output from SO on the falling clock edge of fourth bus

cycle bit 0 as a reference. "Figure 5-a 4 Bus Read" shows the timing waveforms.

Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy

bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference.

"Figure 5-b 5 Bus Read" shows the timing waveforms. The only difference between these two commands is whether the

dummy bits in the fifth bus cycle are input.

When SCK is input continuously after the read command has been input and the data in the designated addresses has

been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding

data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address

(1FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic

level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO

is in a high-impedance state.

Figure 5-a 4 Bus Read

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47

SCK

SI

Mode0

8CLK

03h

Add.

N

N+1

DATA DATA DATA

MSB MSB MSB

N+2

High Impedance

SO

Figure 5-b 5 Bus Read

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47 48

55

SCK

Mode0

8CLK

0Bh

SI

Add.

X

N

N+1

N+2

High Impedance

SO

DATA DATA DATA

MSB

Rev. 0 | Page 6 of 21 | www.onsemi.com

LE25FU106B

2. Status Registers

The status registers hold the operating and setting statuses inside the device, and this information can be read (status

register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 3

Status registers" gives the significance of each bit.

Table 3 Status Registers

Bit

Name

Logic

Function

Ready

Power-on Time Information

0

1

0

1

0

1

0

1

RDY

Bit0

Erase/Program

Write disabled

Write enabled

Bit1

Bit2

Bit3

WEN

BP0

BP1

0

Nonvolatile information

Block protect information

See status register descriptions on BP0 and BP1.

Bit4

Bit5

Bit6

0

Reserved bits

0

1

Status register write enabled

Status register write disabled

Bit7

SRWP

Nonvolatile information

2-1. Status register read

The contents of the status registers can be read using the status register read command. This command can be executed

even during the following operations.

• Small sector erase, sector erase, chip erase

• Page program

• Status register write

"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus

cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the

clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the

first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence,

synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is

output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock

input is continued. The data can be read by the status register read command at any time (even during a program or

erase cycle).

Figure 6 Status Register Read

CS

Mode 3

0

1

2

3

4

5

6

7

8

15 16

23

SCK

SI

Mode 0

8CLK

05h

High Impedance

SO

DATA DATA DATA

MSB MSB MSB

Rev. 0 | Page 7 of 21 | www.onsemi.com

LE25FU106B

2-2. Status register write

The information in status registers BP0, BP1, and SRWP can be rewritten using the status register write command.

RDY, WEN, bit 4, bit 5, and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, and

SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-

down. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20 shows a

status register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates

the internal write operation at the rising CS edge after the data has been input following (01h). Erase and program are

performed automatically inside the device by status register write so that erasing or other processing is unnecessary

before executing the command. By the operation of this command, the information in bits BP0, BP1, and SRWP can be

rewritten. Since bits RDY (bit 0), WEN (bit 1), 4, 5, and 6 of the status register cannot be written, no problem will arise

if an attempt is made to set them to any value when rewriting the status register. Status register write ends can be

detected by RDY of status register read. Information in the status registers can be rewritten 1,000 times (min.). To

initiate status register write, the logic level of the WP pin must be set high and status register WEN must be set to "1".

Figure 7 Status Register Write

Self-timed

Write Cycle

t

SRW

CS

WP

SCK

SI

t

WPH

WPS

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15

8CLK

01h

DATA

High Impedance

SO

2-3. Contents of each status register

RDY (bit 0)

The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is

in a busy state, and when it is "0", it means that write is completed.

Rev. 0 | Page 8 of 21 | www.onsemi.com

LE25FU106B

WEN (bit 1)

The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not

perform the write operation even if the write command is input. If it is set to "1", the device can perform write

operations in any area that is not block-protected.

WEN can be controlled using the write enable and write disable commands. By inputting the write enable command

(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0". In the following states,

WEN is automatically set to "0" in order to protect against unintentional writing.

• At power-on

• Upon completion of small sector erase, sector erase or chip erase

• Upon completion of page program

• Upon completion of status register write

* If a write operation has not been performed inside the LE25FU106B because, for instance, the command input for any

of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has failed or

a write operation has been performed for a protected address, WEN will retain the status established prior to the issue

of the command concerned. Furthermore, its state will not be changed by a read operation.

BP0, BP1 (bits 2, 3)

Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be

set depending on these bits. For the setting conditions, refer to "Table 4 Protect level setting conditions".

Table 4 Protect Level Setting Conditions

Status Register Bits

Protect Level

Protected Area

BP1

0

BP0

0

0 (Whole area unprotected)

1 (1/4 protected)

None

0

1

18000h to 1FFFFh

10000h to 1FFFFh

00000h to 1FFFFh

2 (1/2 protected)

1

0

3 (Whole area protected)

1

* Chip erase is enabled only when the protect level is 0.

SRWP (bit 7)

Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.

When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status

registers BP0, BP1, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not

protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5 SRWP setting conditions".

Table 5 SRWP Setting Conditions

WP

SRWP

Status Register Protect State

Unprotected

0

1

0

1

0

Protected

Unprotected

1

Unprotected

Bits 4, Bits 5, and 6 are reserved bits, and have no significance.

Rev. 0 | Page 9 of 21 | www.onsemi.com

LE25FU106B

3. Write Enable

Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is

the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.

"Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable

command consists only of the first bus cycle, and it is initiated by inputting (06h).

• Small sector erase, sector erase, chip erase

• Page program

• Status register write

4. Write Disable

The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable"

shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by

inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command

(06h).

Figure 8 Write Enable

Figure 9 Write Disable

CS

SCK

SI

CS

SCK

SI

Mode3

Mode0

Mode3

Mode0

0

1

2

3

4

5

6

7

0 1 2 3

4 5 6 7

8CLK

06h

8CLK

04h

High Impedance

SO

5. Power-down

The power-down command sets all the commands, with the exception of the silicon ID read command and the

command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows

the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting

(B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down

state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the

silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of

the power-down exit command.

Figure 10 Power-down

Figure 11 Exiting from Power-down

Power down

mode

Power down

mode

CS

SCK

SI

CS

SCK

SI

t

PRB

t

DP

Mode3

Mode0

Mode3

Mode0

0

1

2

3

4

5

6

7

0 1 2 3

4 5 6 7

8CLK

B9h

8CLK

ABh

High Impedance

SO

Rev. 0 | Page 10 of 21 | www.onsemi.com

LE25FU106B

6. Small Sector Erase

Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of

4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase

flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by

inputting the 24-bit addresses following (D7h). Addresses A16 to A12 are valid, and Addresses A23 to A17 are "don't

care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends

automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY.

Figure 12 Small Sector Erase

Self-timed

Erase Cycle

t

SSE

CS

SCK

SI

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31

8CLK

D7h

Add.

High Impedance

SO

7. Sector Erase

Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 32Kbytes. "Figure

13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command

consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h).

Addresses A16 to A15 are valid, and Addresses A23 to A17 are "don't care". After the command has been input, the

internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal

timer. Erase end can also be detected using status register RDY.

Figure 13 Sector Erase

Self-timed

Erase Cycle

t

SE

CS

SCK

SI

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31

8CLK

D8h

Add.

High Impedance

SO

Rev. 0 | Page 11 of 21 | www.onsemi.com

LE25FU106B

8. Chip Erase

Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the

timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus

cycle, and it is initiated by inputting (C7h). After the command has been input, the internal erase operation starts from

the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be

detected using status register RDY.

Figure 14 Chip Erase

Self-timed

Erase Cycle

t

CHE

CS

Mode3

Mode0

0

1 2 3

4 5 6 7

SCK

8CLK

C7h

SI

High Impedance

SO

9. Page Program

Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page

addresses: A16 to A8). Before initiating page program, the data on the page concerned must be erased using small

sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and

Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the

24-bit addresses. Addresses A16 to A0 are valid. The program data is then loaded at each rising clock edge until the

rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes, the

256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program

operation is not performed at the rising CS edge occurring at any other timing. The page program time is 2.0ms (typ.)

when 256 bytes (1 page) are programmed at one time.

Figure 15 Page Program

Self-timed

Program Cycle

t

PP

CS

Mode3

Mode0

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47

2079

SCK

8CLK

02h

SI

Add.

PD

High Impedance

SO

Rev. 0 | Page 12 of 21 | www.onsemi.com

LE25FU106B

10. Silicon ID Read

Silicon ID read is an operation that reads the manufacturer code and device code information. "Table 6 Silicon ID codes

table" lists the silicon ID codes. The silicon ID read command is not accepted during writing.

Two methods are used for silicon ID reading. The first method involves inputting the 9Fh command: the setting is

completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h and device code

1Dh are repeatedly output in succession so long as the clock input is continued. Refer to "Figure 16-a Silicon ID read 1"

for the waveforms.

The second method involves inputting the ABh command. This command consists of the first through fourth bus cycles,

and the silicon ID can be read when 16 dummy bits and an 8-bit address are input after (ABh). When address A0 is "0",

the manufacturer code 62h is read in the fifth bus cycle, and the device code 1Dh is read in the sixth bus cycle. "Figure

16-b Silicon ID read 2" shows the timing waveforms. If, after the manufacturer code or device code has been read, the

SCK input is continued, the manufacturer code and device code are output alternately with each bus cycle. When

address A0 is "1", reading starts with device code 1Dh in the fifth bus cycle.

Table 6 Silicon ID Codes

Address

Output Code

A0

Manufacturer code

Device code

0

1

62h

1Dh

The data is output starting with the falling clock edge of the fourth bus cycle bit 0, and silicon ID reading ends at the

rising CS edge.

Figure 16-a Silicon ID Read 1

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23

SCK

SI

Mode0

8CLK

9Fh

N

N+1

SiID

MSB

N

High Impedance

SO

SiID

MSB

Figure 16-b Silicon ID Read 2

CS

Mode3

0

1

2

3

4

5

6

7

8

15 16

23 24

31 32

39 40

47

SCK

SI

Mode0

8CLK

ABh

X

Add.

N

N+1

SiID

MSB

N

High Impedance

SO

SiID

MSB

SiID

MSB

Rev. 0 | Page 13 of 21 | www.onsemi.com

LE25FU106B

11. Hold Function

Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17

HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic

level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high,

HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited

and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state,

and SI and SCK are "don't care".

Figure 17 HOLD

Active

HOLD

Active

CS

t

HS

SCK

t

HH

HOLD

t

HLZ

HHZ

High Impedance

SO

12. Power-on

In order to protect against unintentional writing, CS must be kept at V

At power-on. After power-on, the supply

CC

voltage has stabilized at 2.30V or higher, wait for 100μs (t _READ) before inputting the command to start a read

PU

operation. Similarly, wait for 10ms (t _WRITE) after the voltage has stabilized before inputting the command to start

PU

a write operation.

Figure 18 Power-on Timing

Program, Erase and Write Command not Allowed

Full Access Allowed

Chip selection not Allowed

V

Read Access Allowed

DD

V

(Max)

(Min)

DD

t

_READ

PU

t

_WRITE

PU

0V

Rev. 0 | Page 14 of 21 | www.onsemi.com

LE25FU106B

13. Hardware Data Protection

In order to protect against unintentional writing at power-on, the LE25FU106B incorporates a power-on reset function.

The following conditions must be met in order to ensure that the power reset circuit will operate stably.

No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.

Figure 19 Power-down Timing

Program, Erase and Write Command not Allowed

V

DD

No Device Access Allowed

V

(Max)

(Min)

DD

t

_READ

PU

_WRITE

PU

t

PD

0V

vBOT

14. Software Data Protection

The LE25FU106B eliminates the possibility of unintentional operations by not recognizing commands under the

following conditions.

• When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)

• When the page program data is not in 1-byte increments

• When the status register write command is input for 2 bus cycles or more

15. Decoupling Capacitor

A 0.1μF ceramic capacitor must be provided to each device and connected between V

and V in order to ensure

SS

DD

that the device will operate stably.

Rev. 0 | Page 15 of 21 | www.onsemi.com

LE25FU106B

Specifications

Absolute Maximum Ratings

Parameter

Maximum supply voltage

DC voltage (all pins)

Symbol

Conditions

Ratings

-0.5 to +4.6

unit

V

With respect to V

SS

With respect to V

-0.5 to V +0.5

DD

V

SS

Storage temperature

Tstg

-55 to +150

°C

Operating Conditions

Parameter

Symbol

Conditions

Ratings

unit

V

Operating supply voltage

Operating ambient temperature

2.30 to 3.60

0 to 70

°C

-40 to +85 (at the planning stage)

Allowable DC Operating Conditions

Ratings

Parameter

Symbol

Conditions

unit

mA

min

typ

max

Read mode operating current

I

=0.1V

CS

,

=

=0.9V

HOLD WP

CCR

DD

SI=0.1V /0.9V , SO=open

DD DD

operating frequency=30MHz,

6

V

t

=V

max

DD DD

Write mode operating current

(erase+page program)

I

=V

max, t

=40ms,

SSE

CCW

DD DD

=60ms, t

=2.5ms

=140ms,

CHE

15

50

10

mA

μA

SE

t

PP

CMOS standby current

=V

CS

,

=

=V

,

HOLD WP

SB

DD

SO=open,

max

SI=V /V

SS DD,

V

DD= DD

Power-down standby current

=V

,

=

=V

,

CS

HOLD WP

DSB

DD

SO=open,

SI=V /V

SS DD,

V

max

DD= DD

Input leakage current

Output leakage current

Input low voltage

I

V

=V

to V , V =V

max

2

μA

V

LI

IN SS

DD DD DD

V

I

=V

to V , V =V

DD DD DD

LO

IN SS

V

=V

max

-0.3

0.7V

0.3V

DD

IL

DD DD

Input high voltage

Output low voltage

=V

min

V

+0.3

V

IH

OL

DD DD

DD

=100μA, V =V

DD DD

min

0.2

OL

V

I

=1.6mA, V =V

DD DD

0.4

OL

Output high voltage

V

=-100μA, V =V min

DD DD

V

-0.2

OH

CC

Power-on Timing

Ratings

Parameter

Symbol

unit

min

max

Time from power-on to read operation

Time from power-on to write operation

Power-down time

t

_READ

100

μs

ms

V

PU

PD

_WRITE

10

Power-down voltage

v

0.2

BOT

Pin Capacitance at Ta=25°C, f=1MHz

Ratings

max

Parameter

Symbol

Conditions

unit

Output pin capacitance

Input pin Capacitance

C

V

=0V

12

6

pF

DQ

=0V

IN

Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values

for some of the sampled devices.

Rev. 0 | Page 16 of 21 | www.onsemi.com

LE25FU106B

AC Characteristics

Ratings

typ

Parameter

Symbol

unit

min

max

Clock frequency

f

30

20

MHz

ns

ms

s

CLK

SCK logic high level pulse width

SCK logic low level pulse width

Input signal rising/falling time

t

16

CLHI

t

CLLO

t

RF

CS

setup time

t

10

5

CSS

SCK setup time

Data setup time

Data hold time

t

CLS

t

DS

t

5

DH

hold time

t

10

25

CS

SCK hold time

CS

CSH

t

CLH

wait pulse width

t

CPH

CS

Output high impedance time from

Output data time from SCK

Output data hold time

t

15

CHZ

t

10

V

t

1

7

3

HO

HOLD

setup time

hold time

t

HS

t

HH

HOLD

Output low impedance time from

t

9

HLZ

Output high impedance time from

t

HHZ

WP

setup time

hold time

t

20

WPS

t

WPH

Write status register time

Page programming cycle time

Small sector erase cycle time

Sector erase cycle time

Chip erase cycle time

t

5

15

2.5

0.15

0.2

1.4

3

SRW

t

2.0

0.04

0.06

0.14

PP

t

SSE

t

s

SE

t

s

CHE

Power-down time

t

μs

ns

DP

Power-down recovery time

3

PRB

CLZ

Output low impedance time from SCK

0

AC Test Conditions

Input pulse level··············· 0V, 2.5V

Input rising/falling time···· 5ns

Input timing level············· 0.3V , 0.7V

DD DD

Output timing level ·········· 1/2×V

DD

Output load ······················ 30pF

Note: As the test conditions for "typ," the measurements are conducted using 2.5V for V

at room temperature.

DD

Rev. 0 | Page 17 of 21 | www.onsemi.com

LE25FU106B

Figure 20 Status Register Write Flowchart

Status register write

Start

06h

Write enable

01h

Set status register write

command

Data

Program start on rising

edge of CS

Set status register read

command

05h

NO

Bit 0= “0” ?

YES

End of status register

write

* Automatically placed in write disabled state

at the end of the status register write

Rev. 0 | Page 18 of 21 | www.onsemi.com

LE25FU106B

Figure 21 Erase Flowcharts

Sector erase

Start

Small sector erase

Start

Write enable

06h

Write enable

06h

D8h

D7h

Set sector erase

command

Address 1

Address 2

Address 3

Set small sector erase

command

Address 1

Address 2

Address 3

Start erase on rising

edge of CS

Start erase on rising

edge of CS

Set status register read

command

Set status register read

command

05h

NO

Bit 0 = “0” ?

YES

NO

Bit 0 = “0” ?

YES

End of erase

* Automatically placed in write disabled

state at the end of the erase

* Automatically placed in write disabled

state at the end of the erase

Rev. 0 | Page 19 of 21 | www.onsemi.com

LE25FU106B

Figure 22 Page Program Flowchart

Page program

Start

Chip erase

Start

06h

Write enable

06h

C7h

02h

Set chip erase

command

Set page program

command

Address 1

Address 2

Address 3

Data 0

Start erase on rising edge

of CS

Set status register read

command

05h

Bit 0 = “0” ?

YES

Data n

Start program on rising

edge of CS

NO

End of erase

Set status register read

command

* Automatically placed in write disabled state at

the end of the erase

05h

NO

Bit 0= “0” ?

YES

End of

programming

* Automatically placed in write disabled state at

the end of the programming operation.

Rev. 0 | Page 20 of 21 | www.onsemi.com

LE25FU106B

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any

products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the

application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. SCILLC strives to supply high-

quality high-reliability products and recommends adopting safety measures when designing equipment to avoid accidents or malfunctions. Such measures include but are not limited to protective

circuits and error prevention circuits for safe design, redundant design, and structural design. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications

can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals,” must be validated for each customer application by customer’s

technical experts. SCILLC shall not be held liable for any claim or suits with regard to a third party’s intellectual property rights which has resulted from the use of the technical information and

products mentioned above. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components

in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create

a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

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Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

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For additional information, please contact your local

Sales Representative

LE25FU106B/D


型号：	LE25FU106BMA
厂家：	ONSEMI
描述：	IC FLASH 2.7V PROM, Programmable ROM 可编程只读存储器时钟光电二极管内存集成电路
文件：	总21页 (文件大小：119K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LE25FU106BMA [ONSEMI]

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