LC898130DP1XHTBG [ONSEMI]
OIS/CL-AF and Zoom Control LSI;
| 型号： | LC898130DP1XHTBG |
| 厂家： | 
ONSEMI |
| 描述： | OIS/CL-AF and Zoom Control LSI |
| 文件： | 总10页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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OIS/CL-AF & Zoom
Control LSI
Advance Information
WLCSP36
CASE 567ZU
LC898130DP
MARKING DIAGRAM
Overview
This is a system LSI integrating an on−chip 32bit DSP, a FLASH
ROM and peripherals including analog circuits for OIS (Optical
Image Stabilization) / Closed Loop−AF (Auto Focus) and Zoom
control, constant current drivers and PIEZO drivers.
898130XH
AWLYYWW
A
WL
YY
= Assembly Location
= Wafer Lot
= Year
Features
• On−chip 32bit DSP
WW
= Work Week
♦ Built−in Software for Digital Servo Filter
♦ Built−in Software for Gyro Filter
• Memory
ORDERING INFORMATION
♦ Flash Memory
♦ Program ROM
♦ Program SRAM
♦ Data SRAM
†
Device
Package
Shipping
LC898130DP1XHTBG WLCSP36
4,000 /
(Pb−Free) Tape & Reel
LC898130DPNXHTBG WLCSP36
4,000 /
• Peripherals
(Pb−Free) Tape & Reel
♦ AD Converter
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
♦ DA Converter
♦ 2−wire Serial I/F Circuit
2
(The Communication Protocol is Compatible with I C)
♦ Hall/MR Bias Circuit
♦ VGA (Hall/MR Amp)
♦ OSC (Oscillator)
♦ LDO (Low Drop−Out Regulator)
♦ Digital Gyro I/F (SPI)
♦ Interrupt I/F
This document contains information on a new product.
Specifications and information herein are subject to change
without notice.
♦ PLL
♦ Temperature Sensor
• Driver
♦ OIS/CL−AF and Zoom/PIEZO (Bi−direction)
Constant Current Linear Driver (x2ch, I = 200 mA)
full
♦ PIEZO (Di−direction)
PWM Driver (x2ch, Exclusive Use with Constant Current Linear
Driver)
• Package
♦ WLCSP36 (3 x 12 Pin) Thickness Max. 0.35 mm, with Back Coat
♦ Lead−Free
♦ Halogen Free
• Power Supply Voltage
♦ AD/DA/VGA/LDO/OSC/Flash/PLL/Temp. Sensor:
AVDD = 2.7 V to 3.6 V
♦ Driver: V = 2.7 V to 3.6 V
M
♦ 1.8 V I/O: I
= 1.7 V to 3.6 V
OVDD
♦ Core Logic: Generated by On−chip LDO
Connect 1 mF Capacitor to LDPO Pin
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
September, 2021 − Rev. P0
LC898130DP/D
LC898130DP
BLOCK DIAGRAM
DSP
RAM
ROM
RAM
FLASH
IOVDD
2−wire
Serial I/F
Slave
SCL
SDA
Hall
VGA
ADC
SSB0
SSB1
SCLK
MOSI
MISO
SPI
INT
Hall Offset
/ Bias
Port
EIRQ
AVDD
LDPO
2−wire
Serial I/F
Master/Slave
SCL2
SDA2
LDO
POR
OSC
PLL
1 mF
MCLK
DVSS
AVSS
OUT 1
OUT 2
OUT 3
OUT 4
H−Bridge
Driver
VM
PGND
Figure 1. Block Diagram
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2
LC898130DP
DSP
RAM
ROM
RAM
FLASH
IOVDD
2−wire
Serial I/F
Slave
SCL
SDA
MR
VGA
ADC
SSB0
SSB1
SCLK
MOSI
MISO
SPI
INT
Hall Offset
/ Bias
Port
EIRQ
AVDD
LDPO
2−wire
Serial I/F
Master/Slave
SCL2
SDA2
LDO
POR
OSC
PLL
1 mF
MCLK
DVSS
AVSS
OUT1
OUT2
OUT3
OUT4
H−Bridge
Driver
VM
PGND
Figure 2. Block Diagram
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3
LC898130DP
PIN LAYOUT
C
B
A
OUT2
VM
OUT1
OPINP1 OPINP2 OPINP3 OPINP4 HLBO1 HLBO2
DVSS
SSB1
IOVDD
SSB0
SDA2
SCL2
SDA
SCL
PGND OPINM1 OPINM2 OPINM3 OPINM4 PCNT1 PCNT2
OUT4
1
OUT3
2
MON1
3
MON2
4
AVSS
5
AVDD
6
LDPO
7
MCLK
8
EIRQ
9
MISO
10
MOSI
11
SCLK
12
Driver
VDD/VSS
Internal VDD Output
1.8 V I/O
Figure 3. Pin Layout (Bottom View)
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4
LC898130DP
PIN DESCRIPTION
PIN DESCRIPTION
No.
1
Pin
I/O
B
I/O Pwr
Function
Servo Monitor Analog In/Out
Init
Z
MON1
MON2
SCL
AVDD
AVDD
2
B
Servo Monitor Analog In/Out
Z
3
B
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
2−wire serial HOST I/F Clock Slave
Z
4
SDA
B
2−wire serial HOST I/F Data Slave
Z
5
SSB0
SCLK
MOSI
B
Digital Gyro Data I/F Chip Select 0 Out (3/4−wire Master)
Digital Gyro Data I/F Clock Out (3/4−wire Master)
Z
6
B
Z
7
B
Digital Gyro Data I/F Data InOut (3−wire Master)
Digital Gyro Data I/F Data Out (4−wire Master)
Z
8
MISO
B
IOVDD
Digital Gyro Data I/F Data In (4−wire Master)
U
SSB2
SELADR
9
EIRQ
MCLK
B
B
B
B
B
O
O
O
O
I
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VM
Interrupt Input
Z
Z
Z
Z
Z
Z
Z
Z
Z
−
−
−
−
−
−
−
−
Z
Z
Z
Z
−
−
−
−
−
−
−
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Master Clock
SSB1
Digital Gyro Data I/F Chip Select 1 Out (3/4−wire Master)
2−wire serial I/F Clock Master/Slave
2−wire serial I/F Data Master/Slave
Hall/MR Bias Output 1
SCL2
SDA2
HLBO1
HLBO2
PCNT1
PCNT2
OPINM1
OPINP1
OPINM2
OPINP2
OPINM3
OPINP3
OPINM4
OPINP4
OUT1
Hall/MR Bias Output 2
External Driver Power Control 1
External Driver Power Control 2
VGA (Hall/MR Amp) Input Minus 1
VGA (Hall/MR Amp) Input Plus 1
VGA (Hall/MR Amp) Input Minus 2
VGA (Hall/MR Amp) Input Plus 2
VGA Input Minus 3
I
I
I
I
I
VGA (MR Amp) Input Plus 3
VGA Input Minus 4
I
I
VGA (MR Amp) Input Plus 4
OIS Driver Output 1
O
O
O
O
P
P
P
P
P
P
P
OUT2
VM
OIS Driver Output 2
OUT3
VM
OIS Driver Output 3
OUT4
VM
OIS Driver Output 4
AVDD
Analog Power (2.7 V to 3.6 V)
Analog GND
AVSS
VM
Driver Power (2.7 V to 3.6 V)
Driver GND
PGND
IOVDD
DVSS
I/O Power (1.7 V to 3.6 V)
Digital GND
LDPO
Internal 1.38 V LDO Power Output
NOTE: Z: Hi−Z
U: Internal Pull−Up Register On
D: Internal Pull−Down Register On
*Process when pins are not used
• PIN TYPE “O” – Ensure that it is set to OPEN.
• PIN TYPE “I” – OPEN is inhibited. Ensure that it is connected to the V or V even when it is unused.
DD
SS
(Please contact onsemi for more information about selection of V or V .)
DD
SS
• PIN TYPE “B” – If you are unsure about processing method on the pin description of pin layout table, please contact us.
Note that incorrect processing of unused pins may result in defects.
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5
LC898130DP
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (AVSS = 0 V, PGND = 0 V, DVSS = 0 V)
Parameter Symbol Conditions
Power Supply Voltage
≤ 25°C
Ratings
−0.3 to 4.6
−0.3 to 4.6
−0.3 to 4.6
Unit
V
V
AD
max
max
max
T
A
V
T
≤ 25°C
≤ 25°C
≤ 25°C
≤ 25°C
≤ 25°C
V
M
A
V
IO
T
A
V
Input/Output Voltage
V , V
AI AO
T
A
−0.3 to V + 0.3
V
AD
V
MI
, V
T
A
−0.3 to V + 0.3
V
MO
M
V , V
II
T
A
−0.3 to V + 0.3
V
IOO
IO
Storage Temperature
T
stg
−55 to 125
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
ALLOWABLE OPERATING RATINGS (T = −40 to 85°C, AVSS = 0 V, PGND = 0 V, DVSS = 0 V)
A
Parameter
3.0 V POWER SUPPLY (AVDD)
Power Supply Voltage
Symbol
Min
Typ
Max
Unit
V
AD
2.7
0
2.8
3.6
V
V
Input Voltage Range
V
INA
−
V
AD
3.0 V POWER SUPPLY (VM)
Power Supply Voltage
V
2.7
0
2.8
3.6
V
V
M
Input Voltage Range
V
INM
−
V
M
1.8 V POWER SUPPLY (IOVDD)
Power Supply Voltage
V
1.7
0
1.8
3.6
V
V
IO
Input Voltage Range
V
INI
−
V
IO
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS: INPUT/OUTPUT
(T = −40 to 85°C, AVSS = 0 V, PGND = 0 V, DVSS = 0 V, AVDD = 2.7 to 3.6 V, IOVDD = 1.7 to 3.6 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Applicable Pins
High−level Input Voltage
V
CMOS
Schmitt
0.7 IOVDD
−
−
V
SCL, SDA, SCL2,
SDA2, SSB0, SSB1,
SCLK, MOSI, MISO,
EIRQ, MCLK
IH
Low−level Input Voltage
V
−
−
0.3 IOVDD
V
IL
High−level Input Voltage
Low−level Input Voltage
High−level Output Voltage
V
CMOS
0.7 AVDD
−
−
−
−
0.3 AVDD
−
V
V
V
MON1, MON2
IH
Schmitt
V
−
IL
V
OH
I
= −3 mA
IOVDD −
SDA, SCL2, SDA2,
SSB0, SSB1, SCLK,
MOSI, MISO, EIRQ,
MCLK
OH
0.2
Low−level Output Voltage
High−level Output Voltage
V
V
I
= 3 mA
−
−
−
0.2
V
V
SCL, SDA, SCL2,
SDA2, SSB0, SSB1,
SCLK, MOSI, MISO,
EIRQ, MCLK
OL
OL
I
I
= −2 mA
AVDD −
0.2
−
MON1, MON2
OH
OH
Low−level Output Voltage
V
OL
= 2 mA
−
−
−
0.2
V
V
OL
Analog Input Voltage
V
AVSS
AVDD
MON1, MON2,
OPINP1, OPINM1,
OPINP2, OPINM2,
OPINP3, OPINM3,
OPINP4, OPINM4
AI
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6
LC898130DP
DC CHARACTERISTICS: INPUT/OUTPUT (continued)
(T = −40 to 85°C, AVSS = 0 V, PGND = 0 V, DVSS = 0 V, AVDD = 2.7 to 3.6 V, IOVDD = 1.7 to 3.6 V)
A
Parameter
Pull Up Resistor
Symbol
Conditions
Min
Typ
Max
Unit
Applicable Pins
R
20
−
250
kW
SCL2, SDA2, SSB0,
SSB1, SCLK, MOSI,
MISO, EIRQ, MCLK,
MON1, MON2
up
Pull Down Resistor
R
20
−
250
kW
dn
DRIVER OUTPUT
(T = 25°C, AVSS = 0 V, PGND = 0 V, DVSS = 0 V, AVDD = VM = 2.8 V)
A
Parameter
Symbol
Conditions
Min
190
Typ
Max
Unit
Output Current, OUT1−OUT4
I
full
Full code
200
210
mA
NON−VOLATILE MEMORY CHARACTERISTICS
(T = −40 to 85°C, AVSS = 0 V, PGND = 0 V, DVSS = 0 V, AVDD = 2.7 to 3.6 V, IOVDD = 1.7 to 3.6 V)
A
Parameter
Symbol
Conditions
Read for FLASH
Program & Erase for FLASH
Value
−40 to 85
Unit
°C
Operating Temperature
T
opr1
T
opr2
−10 to 65 (Note 1)
°C
1. All drivers must be in the standby state.
Item
Symbol
EN
Conditions
Min
−
Typ
−
Max
1000
−
Unit
Cycles
Years
ms
Applicable Circuit
Endurance
Flash Memory
Data Retention
Write Time
RT
10
−
−
t
−
3
WT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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7
LC898130DP
AC CHARACTERISTICS
Power Supply Timing
t
R
t
W
AVDD
Min V
VM
IOVDD
10%
V
bot
Figure 4. VDD Supply Timing
Table 1.
Item
Symbol
Min
Typ
Max
Unit
Rise Time
t
−
100
−
−
−
−
3
−
ms
ms
V
R
Wait Time
t
W
Bottom Voltage
V
bot
0.2
Injection order between AVDD, VM and IOVDD is below.
1.7 V
1.7 V
IOVDD
t
t
AVIO
IOAV
2.7 V
2.7 V
AVDD
VM
0.2 V
0.2 V
t
t
AVVM
VMAV
0.2 V
0.2 V
Figure 5. Injection Order between AVDD, VM and IOVDD
Table 2.
Item
Symbol
Min
Typ
Max
Unit
IOVDD On to AVDD ON
AVDD ON to VM ON
t
0
0
0
0
−
−
−
−
−
−
−
*
ms
ms
ms
ms
IOAV
t
AVVM
VMAV
VM OFF to AVDD OFF
AVDD OFF to IOVDD OFF
t
t
AVIO
*Please make IOPRSTB (D0_0064h, bit0) = 0 before turning OFF AVDD when AVDD is turned off with keeping IOVDD on.
SDA, SCL, SSB0, SSB1, SCLK, MOSI, MISO, EIRQ, MCLK, SCL2 and SDA2 tolerate 3 V input at the time of IOVDD power
off.
The data in the Flash memory may be rewritten unintentionally if you do not keep specifications.
And it is forbidden to power off during Flash memory access. The data in the Flash memory may be rewritten unintentionally.
Drivers are recommended to set standby before VM power off.
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8
LC898130DP
2−wire Serial Interface Timing
The 2−wire serial interface timing definition and electric characteristics are shown below. The communication protocol is
2
compatible with I C. This circuit has clock stretch function.
Static Address: 7’b0100100
t
f
t
r
t
BUF
V
IHmin
SDA
SCL
V
ILmin
t
t
t
t
t
t
SU;STO
HD;STA
HD;DAT SU;DAT
SU;STA HD;STA
t
f
t
r
V
IHmin
V
ILmin
t
t
1/f
SCL
LOW
HIGH
Start Condition
Repeated Start Condition
Stop Condition Start Condition
Figure 6. 2−wire Serial Interface Timing
Table 3.
Standard−mode
Fast−mode
Fast−mode Plus
Min
Max
Min
Max
Min
Max
Item
SCL Clock Frequency
Symbol
Units
kHz
ms
f
−
100
−
−
400
−
−
1000
SCL
START Condition Hold Time
SCL Clock Low Period
SCL Clock High Period
t
t
4.0
4.7
4.0
4.7
0.6
1.3
0.6
0.6
0.26
0.5
−
−
−
−
HD;STA
t
−
−
ms
LOW
t
−
−
0.26
0.26
ms
HIGH
Setup Time for Repetition
START Condition
−
−
ms
SU;STA
Data Hold Time
t
0 (Note 2)
3.45
−
0 (Note 2)
0.9
−
0 (Note 2)
0.45
−
ms
ns
ns
ns
ms
ms
HD;DAT
Data Setup Time
t
250
−
100
−
50
−
SU;DAT
SDA, SCL Rising Time
SDA, SCL Falling Time
STOP Condition Setup Time
t
r
1000
300
−
300
300
−
120
120
−
t
f
−
−
−
t
4.0
4.7
0.6
1.3
0.26
0.5
SU;STO
Bus Free Time between
STOP and START
t
−
−
−
BUF
2. Although the I C specification defines a condition that 300 ns of hold time is required internally, this LSI is designed for a condition with typ.
2
33 ns of hold time. If SDA signal is unstable around falling point of SCL signal, please implement an appropriate treatment on board, such
as inserting a resister.
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9
LC898130DP
PACKAGE DIMENSIONS
WLCSP36 1.295x4.74x0.33
CASE 567ZU
ISSUE O
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
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Phone: 011 421 33 790 2910
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