LC75852E [ONSEMI]

1/2-Duty LCD Driver with Key Input Function;


型号：	LC75852E
厂家：	ONSEMI
描述：	1/2-Duty LCD Driver with Key Input Function 驱动 CD 接口集成电路
文件：	总19页 (文件大小：669K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LC75852E, LC75852W

1/2-Duty LCD Driver

with Key Input Function

Overview

The LC75852E and LC75852W are 1/2 duty dynamic LCD display drivers.

In addition to being able to directly drive LCD panels with up to 90 segments,

they can also control up to four general-purpose output ports. These products

also include a key scan circuit which allows them to accept input from

keypads with up to 30 keys. This allows end product front panel wiring to be

simplified.

www.onsemi.com

Features

 Up to 30 key inputs (Key scan is only performed when a key is pressed.)

 1/2 duty – 1/2 bias (up to 90 segments)

 Sleep mode and the all segments off function can be controlled from serial

PQFP64 14x14 / QIP64E

[LC75852E]

data.

 Segment output port/general-purpose output port usage can be controlled

from serial data.

 Serial data I/O supports CCB* format communication with the system

controller.

 High generality since display data is displayed directly without decoder

intervention

 Reset pin that can establish the initial state.

SPQFP64 10x10 / SQFP64

[LC75852W]

Specifications

Absolute Maximum Ratings at Ta = 25C, V = 0V

Parameter

Maximum supply voltage

Input voltage

Symbol

Conditions

, KI1 to KI5

Ratings

Unit

max

0.3 to +7.0

OSC, CE, CL, DI,

RES

0.3 to V +0.3

OSC, DO, S1 to S45, COM1, COM2, KS1 to KS6, P1 to P4

Output voltage

0.3 to V +0.3

OUT

S1 to S45

100

A

OUT

COM1, COM2, KS1 to KS6

P1 to P4

Output current

Allowable power dissipation

Operating temperature

Storage temperature

Pd max

Topr

Ta = 85C

200

C

40 to +85

55 to +125

Tstg

C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,

damage may occur and reliability may be affected.

* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and

the bus addresses are controlled by ON Semiconductor.

ORDERING INFORMATION

See detailed ordering and shipping information on page 19 of this data sheet.

July 2017 - Rev. 1

Publication Order Number :

LC75852E_W/D

LC75852E, LC75852W

Allowable Operating Ranges at Ta = –40 to +85°C, V_SS= 0 V

Parameter

Supply voltage

Symbol

V_DD

Conditions

min

4.5

typ

max

6.0

Unit

V_DD

V_IH1

V_IH2

V_IL

CE, CL, DI, RES

KI1 to KI5

0.8 V_DD

0.6 V_DD

V_DD

Input high-level voltage

Input low-level voltage

CE, CL, DI, RES, KI1 to KI5

0.2 V_DD

Recommended external

resistance

R_OSC

C_OSC

OSC

k

Recommended external

capacitance

OSC

680

Guaranteed oscillator range

Data setup time

Data hold time

f_OSC

t_ds

t_dh

t_cp

t_cs

t_ch

t_øH

t_øL

t_r

OSC

160

100

kHz

μs

CL, DI: Figure 1

CE wait time

CE, CL: Figure 1

CE setup time

CE, CL: Figure 1

CE hold time

CE, CL: Figure 1

High-level clock pulse width

Low-level clock pulse width

Rise time

CL: Figure 1

CE, CL, DI: Figure 1

DO, R_PU= 4.7 k, C_L= 10 pF*: Figure 1

Figure 2

160

Fall time

t_f

DO output delay time

DO rise time

t_dc

t_dr

1.5

RES switching time

Note: * Since DO is an open-drain output, these values differ depending on the pull-up resistor R_PUand the load capacitance C_L.

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended

Operating Ranges limits may affect device reliability.

Electrical Characteristics in the Allowable Operating Ranges

Parameter

Symbol

V_H

Conditions

CE, CL, DI, RES, KI1 to KI5

min

typ

max

Unit

Hysteresis

0.1 V_DD

Input high-level current

Input low-level current

Input floating voltage

Pull-down resistance

Output off leakage current

I_IH

CE, CL, DI, RES: V_I= 6.0 V

CE, CL, DI, RES: V_I= 0 V

KI1 to KI5

5.0

μA

I_IL

–5.0

V_IF

0.05 V_DD

250

R_PD

I_OFFH

KI1 to KI5: V_DD= 5.0 V

100

k

μA

DO: V_O= 6.0 V

6.0

V_OH1

V_OH2

V_OH3

V_OH4

KS1 to KS6: I_O= –1 mA

P1 to P4: I_O= –1 mA

V_DD– 1.0

V_DD– 0.6

0.4

Output high-level voltage

S1 to S45: I_O= –10 μA

COM1, COM2: I_O= –100 μA

KS1 to KS6: I_O= 50 μA

P1 to P4: I_O= 1 mA

V_OL1

V_OL2

V_OL3

V_OL4

V_OL5

1.0

3.0

1.0

0.6

0.5

3.6

2.85

Output low-level voltage

S1 to S45: I_O= 10 μA

COM1, COM2: I_O= 100 μA

DO: I_O= 1 mA

0.1

3.0

_MID1

_MID2

COM1, COM2: V_DD= 6.0 V, I_O= ±100 μA

COM1, COM2: V_DD= 4.5 V, I_O= ±100 μA

Sleep mode, Ta = 25°C

V_DD= 6.0 V, output open, Ta = 25°C, f_OSC= 50 kHz

2.4

Output middle-level voltage

Current drain

1.65

2.25

_DD1

_DD2

μA

1.4

2.5

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under different conditions.

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LC75852E, 75852W

1. When stopped with CL at the low level

2. When stopped with CL at the high level

Pin Assignment

Figure 1

Page 3

LC75852E, 75852W

Block Diagram

Pin Functions

Handling when

unused

Pin No.

Function

Active

—

I/O

Segment outputs: Used to output the display data that is transmitted over the

serial data input. Pins S1/P1 to S4/P4 can be used as general-purpose outputs

according to control data specification.

S1/P1 to S4/P4

S5 to S43

1 to 4

5 to 43

Open

COM1

COM2

Common driver outputs. The frame frequency f_Ois (f_OSC/512) Hz.

—

Key scan outputs. When a key matrix is formed, normally a diode will be

attached to the key scan timing line to prevent shorts. However, since the

output transistor impedance is an unbalanced CMOS output, it will not be

damaged if shorted. Pins KS1/S44 and KS2/S45 can be used as segment

outputs according to control data specification.

KS1/S44,

KS2/S45,

KS3 to KS6

48 to 51

—

Open

KI1 to KI5

52 to 56

GND

V_DD

Key scan inputs: Pins with a built-in pull-down resistor.

Oscillator connection: Oscillator circuit can be formed by connecting the pin to

a resistor and a capacitor.

OSC

—

I/O

CE: Chip enable

CL: Synchronization clock

DI: Transfer data

Serial data interface: Connected

to the controller. Since DO is an

open-drain output, it requires a

pull-up resistor.

GND

—

DO: Output data

Open

Reset input that re-initializes the LSI internal states. During a reset, the display

segments are turned off forcibly regardless of the internal display data. All

internal key data is reset to low and the key scan operation is disabled.

However, serial data can be input during a reset.

RES

GND

Power supply connection. A supply voltage of between 4.5 and 6.0 V must be

provided.

V_DD

V_SS

—

Power supply ground connection. Must be connected to GND.

Page 4

LC75852E, 75852W

Serial Data Input

1. When stopped with CL at the low level

2. When stopped with CL at the high level

CCB address......................[42H]

D1 to D90...........................Display data

S0, S1 ................................Sleep control data

K0, K1 ................................Key scan output/segment output selection data

P0, P1 ................................Segment output port/general-purpose output port selection data

SC ......................................Segment on/off control data

Page 5

LC75852E, 75852W

Control Data Functions

1. S0, S1.................Sleep control data

This control data switches the LSI between normal mode and sleep mode. It also sets the key scan output standby

states for pins KS1 to KS6.

Control data

S0 S1

Key scan standby mode output pin states

Segment outputs

Common outputs

Mode

Oscillator

KS1

KS2

KS3

KS4

KS5

KS6

Normal

Sleep

Operation

Stopped

Note: The KS1/S44 and KS2/S45 output pins are set to the key scan output state.

2. K0, K1................Key scan output/segment output selection data

This control data switches the KS1/S44 and KS2/S45 output pins between the key scan output and segment output

functions.

Control data

K0 K1

Output pin states

Maximum number

of key inputs

KS1/S44 KS2/S45

KS1

S44

KS2

S45

X: don’t care

3. P0, P1.................Segment output port/general-purpose output port selection data

This control data switches the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose

output port functions.

Control data

P0 P1

Output pin states

S1/P1

S2/P2

S3/P3

S4/P4

The table below lists the correspondence between the display data and the output pins when the general-purpose

output port function is selected.

Output

Corresponding

display data

S1/P1

S2/P2

S3/P3

S4/P4

For example, if the output pin S4/P4 is set for use as a general-purpose output port, the output pin S4/P4 will output a

high level when the display data D7 is 1.

4. SC.......................Segment on/off control data

This control data controls the segment on/off states.

Display state

Off

Page 6

LC75852E, 75852W

Display Data and Output Pin Correspondences

Output pin

S1/P1

S2/P2

S3/P3

S4/P4

COM1

COM2

D10

D12

D14

D16

D18

D20

D22

D24

D26

D28

D30

D32

D34

D36

D38

D40

D42

D44

D46

D48

D50

D52

D54

D56

D58

D60

D62

D64

D66

D68

D70

D72

D74

D76

D78

D80

D82

D84

D86

D88

D90

D11

D13

D15

D17

D19

D21

D23

D25

D27

D29

D31

D33

D35

D37

D39

D41

D43

D45

D47

D49

D51

D53

D55

D57

D59

D61

D63

D65

D67

D69

D71

D73

D75

D77

D79

D81

D83

D85

D87

D89

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

KS1/S44

KS2/S45

For example, the output states of output pin S11 are listed in the table below.

Display data

D21 D22

Output pin state

S11

Segment off for both COM1 and COM2

Segment on for COM2

Segment on for COM1

Segments on for both COM1 and COM2

Page 7

LC75852E, 75852W

Serial Data Output

1. When stopped with CL at the low level

2. When stopped with CL at the high level

CCB address......................[43H]

KD1 to KD30 ......................Key data

SA ......................................Sleep acknowledge data

Note: If key data is read when DO is high, the key data (KD1 to KD30) and sleep acknowledge data (SA) will be

invalid.

Output Data

1. KD1 to KD30.....Key data

When a key matrix with up to 30 keys is formed using the KS1 to KS6 output pins and the KI1 to KI5 input pins, the

key data corresponding to a given key will be 1 if that key is pressed. The table below lists that correspondence.

Item

KS1/S44

KS2/S45

KS3

KI1

KD1

KD6

KI2

KD2

KD7

KI3

KD3

KD8

KI4

KD4

KD9

KI5

KD5

KD10

KD11 KD12

KD16 KD17

KD21 KD22

KD26 KD27

KD13 KD14 KD15

KD18 KD19 KD20

KD23 KD24 KD25

KD28 KD29 KD30

KS4

KS5

KS6

When the output pins KS1/S44 and KS2/S45 are selected for segment output by the control data K0 and K1, the key

data items KD1 to KD10 will be 0.

2. SA ......................Sleep acknowledge data

This output data is set according to the state when the key was pressed. If the LSI was in sleep mode, SA will be 1,

and if the LSI was in normal mode, SA will be 0.

Sleep Mode

When S0 or S1 in the control data is set to 1, the oscillator at the OSC pin will stop (it will restart if a key is pressed) and

the segment and common outputs will all go to the low level. This reduces the LSI power dissipation. However, the

S1/P1 to S4/P4 output pins can be used as general-purpose output ports even in sleep mode if selected for such use by

the P0 and P1 control data bits.

Page 8

LC75852E, 75852W

Key Scan Operation

1. Key Scan Timing

The key scan period is 375T [s]. The key scan is performed twice to reliably determine the key on/off states, and the

LSI detects key data agreement. When the key data agrees, the LSI determines that a key has been pressed, and outputs

a key read request (by setting DO low) 800T [s] after the key scan started. If a key is pressed again without the key data

agreeing, a key scan is performed once more. Thus key on/off operations shorter than 800T [s] cannot be detected.

*1 The high or low states of these signals in sleep mode are determined by the S0 and S1 control data bits.

2. Key Scan during Normal Mode

• The pins KS1 to KS6 are set high.

• A key scan starts if any key is pressed, and the scan continues until all keys have been released. Multiple key

presses can be recognized by determining if multiple key data bits have been set.

• When a key has been pressed for 800T [s] (where T = 1/f_OSC) or longer, a key data read request (DO is set to low)

is output to the controller. The controller acknowledges this request and reads the key data. However, DO will go

high when CE is high during a serial data transfer.

• After the controller has finished reading the key data, the LSI clears the key data read request (by setting DO high)

and performs another key scan. Note that since DO is an open drain output, a pull-up resistor of between 1 and 10 kΩ

is required.

Page 9

LC75852E, 75852W

3. Key Scan during Sleep Mode

• The pins KS1 to KS6 are set high or low according to the S0 and S1 control data bits.

(See the description of the control data function for details.)

• If a key for a line corresponding to one of the pins KS1 to KS6 which is high is pressed, the oscillator at the OSC

pin starts and a key scan is performed. The key scan continues until all keys have been released. Multiple key

presses can be recognized by determining if multiple key data bits have been set.

• When a key has been pressed for 800T [s] (where T = 1/f_OSC) or longer, a key data read request (DO is set to low)

is output to the controller. The controller acknowledges this request and reads the key data. However, DO will go

high when CE is high during a serial data transfer.

• After the controller has finished reading the key data, the LSI clears the key data read request (by setting DO high)

and performs another key scan. Note that since DO is an open drain output, a pull-up resistor of between 1 and 10 kΩ

is required.

• Key scan example in sleep mode

Example: Here S0 = 0 and S1 = 1 (This is a sleep in which only KS6 is high.)

Multiple Key Presses

Without the insertion of additional diodes, the LC75852 supports key scan for double key presses in general, triple key

presses of keys on the lines for input pins KI1 to KI5, and multiple key presses of keys on the lines for the output pins

KS1 to KS6. However, if multiple key presses in excess of these limits occur, the LC75852 may recognize keys that

were not pressed as having been pressed. Therefore, series diodes must be connected to each key.

Page 10

LC75852E, 75852W

1/2 Duty - 1/2 Bias LCD Drive Scheme

COM1

COM2

S1 to S45 outputs for segments on

COM1 side being lit

S1 to S45 outputs for segments on

COM2 side being lit

S1 to S45 outputs for segments on

COM1,COM2 sides being lit

S1 to S45 outputs for segments on

COM1,COM2 sides not being lit

RES and the Display Controller

Since the LSI internal data (D1 to D90 and the control data) is undefined when power is first applied, the output pins

S1/P1 to S4/P4, S5 to S43, COM1, COM2, KS1/S44 and KS2/S45 should be held low by setting the RES pin low at the

same time as power is applied. Then, meaningless displays at power on can be prevented by transferring data from the

controller and setting RES high when that transfer has completed.

Figure 2

Page 11

LC75852E, 75852W

Internal Block States during the Reset Period (when RES is low)

1. CLOCK GENERATOR

Reset is applied and the basic clock stops. However, the state of the OSC pin (the normal or sleep state) is

determined after the control data S0 and S1 has been sent.

2. COMMON DRIVER, SEGMENT DRIVER & LATCH

Reset is applied and the display is turned off. However, display data can be input to the LATCH.

3. KEY SCAN

Reset is applied and at the same time as the internal states are set to their initial states, the key scan operation is

disabled.

4. KEY BUFFER

Reset is applied and all the key data is set to the low level.

5. CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER

To allow serial data transfers, reset is not applied to these circuits.

Output Pin States during the Reset Period (when RES is low)

Output pin

S1/P1 to S4/P4

S5 to S43

State during reset

L^*3

COM1, COM2

KS1/S44, KS2/S45

KS3 to KS5

KS6

L^*3

X^*4

H^*5

X: don’t care

Note: 3. These output pins are forcibly set to the segment output mode and held low.

4. Immediately following power on, these output pins are undefined until the control data S0 and S1 has been sent.

5. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin is held high during the reset period

even if key data is read.

Page 12

LC75852E, 75852W

Sample Application Circuit

Note: * Since DO is an open-drain output, a pull-up resistor is required. Select a value (between 1 and 10 kΩ) that is appropriate for the capacitance of the

external wiring so that the waveforms are not distorted.

Notes on Controller Display Data Transfer

The LC75852 transfers the display data (D1 to D90) in two operations. To assure visual display quality, all the display

data should be sent within a 30 ms or shorter period.

Page 13

LC75852E, 75852W

Notes on Controller Key Data Read Techniques

1. Controller key data reading under timer control

• Flowchart

• Timing Chart

t3 ..................Key scan execution time (800T [s]) when the key scan data for two key scans agrees

t4 ..................Key scan execution time (1600T [s]) when the key scan data for two key scans does not agree and a key scan is executed again

t5 ..................Key address (43H) transfer time

t6 ..................Key data read time

T =

f_OSC

• Description

When determining key on/off and reading key data, the controller must confirm the state of DO output when CE is

low for each period t7. When DO is low, the controller recognizes that a key has been pressed and reads the key

data.

During this operation t7 must obey the following condition:

t7 > t5 + t6 + t4

If key data is read when DO is high, the key data (KD1 to KD30) and the sleep acknowledge data (SA) will be

invalid.

Page 14

LC75852E, 75852W

2. Controller key data reading under interrupt control

• Flowchart

• Timing Chart

t3 ..................Key scan execution time (800T [s]) when the key scan data for two key scans agrees

t4 ..................Key scan execution time (1600T [s]) when the key scan data for two key scans does not agree and a key scan is executed again

t5 ..................Key address (43H) transfer time

t6 ..................Key data read time

T =

f_OSC

Page 15

LC75852E, LC75852W

• Description

When determining key on/off and reading key data, the controller must confirm the state of DO output when CE is

low. When DO is low, the controller recognizes that a key has been pressed and reads the key data. After the time t8,

the next key on/off determination and reading key data must be confirmed by the state of DO output when CE is low.

During this operation t8 must obey the following condition :

t8 > t4

If key data is read when DO is high, the key data (KD1 to KD30) and the sleep acknowledge data (SA) will be invalid.

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LC75852E, LC75852W

Package Dimensions

unit : mm

[LC75852E]

PQFP64 14x14 / QIP64E

CASE 122BP

ISSUE A

17.20.2

14.00.1

0.15

0.8

0.35

0.15

(1.0)

0 to 10

0.10

GENERIC

SOLDERING FOOTPRINT*

MARKING DIAGRAM*

16.30

XXXXXXXX

YMDDD

(Unit: mm)

XXXXX = Specific Device Code

Y = Year

M = Month

DDD = Additional Traceability Data

*This information is generic. Please refer to

device data sheet for actual part marking.

0.80

0.50

NOTE: The measurements are not to guarantee but for reference only.

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

LC75852E, LC75852W

Package Dimensions

unit : mm

[LC75852W]

SPQFP64 10x10 / SQFP64

CASE 131AK

ISSUE A

12.00.2

10.00.1

1 2

0.150.05

0.5

0.18

0.10

(1.25)

0 to 10

0.10

SOLDERING FOOTPRINT*

GENERIC MARKING DIAGRAM*

11.40

XXXXXXXX

YDD

XXXXXXXX

YMDDD

(Unit: mm)

XXXXX = Specific Device Code

Y = Year

XXXXX = Specific Device Code

Y = Year

DD = Additional Traceability Data

M = Month

DDD = Additional Traceability Data

*This information is generic. Please refer to

device data sheet for actual part marking.

0.50

0.28

NOTE: The measurements are not to guarantee but for reference only.

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

LC75852E, LC75852W

ORDERING INFORMATION

Device

Package

Shipping (Qty / Packing)

PQFP64 14x14 / QIP64E

(Pb-Free)

LC75852E-E

300 / Tray Foam

PQFP64 14x14 / QIP64E

(Pb-Free)

LC75852EHS-E

LC75852W-E

SPQFP64 10x10 / SQFP64

(Pb-Free)

800 / Tray JEDEC

1000 / Tape and Reel

SPQFP64 10x10 / SQFP64

(Pb-Free)

LC75852W-TML-E

† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel

Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF

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LC75852E [ONSEMI]

相关型号：

LC75852E-E

LC75852EHS-E

LC75852W

LC75852W-E

LC75852W-TML-E

LC75853

LC75853E

LC75853NE

LC75853NW

LC75853W

LC75854E

LC75854W