LB11923V [ONSEMI]
BRUSHLESS DC MOTOR CONTROLLER;
| 型号： | LB11923V |
| 厂家： | 
ONSEMI |
| 描述： | BRUSHLESS DC MOTOR CONTROLLER 电动机控制 |
| 文件： | 总20页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN7498A
LB11923V
Monolithic Digital IC
http://onsemi.com
Three-Phase Brushless
Motor Driver
Overview
The LB11923V is a pre-driver IC designed for variable-speed control of 3-phase brushless motors. It can be used to
implement a motor drive circuit with the desired output capacity (voltage, current) by using discrete transistors for the
output stage. It implements direct PWM drive for minimal power loss. Since the LB11923V includes a built-in VCO
circuit, applications can control the motor speed arbitrarily by varying the external clock frequency.
Function
Direct PWM drive output
Speed discriminator + PLL speed control circuit
Speed lock detection output
Built-in crystal oscillator circuit
Forward/reverse switching circuit
Braking circuit (short braking)
Full complement of on-chip protection circuits, including lock protection, current limiter, and thermal shutdown
protection circuits.
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Maximum supply voltage
Maximum input current
Output current
Symbol
Conditions
Ratings
Unit
V
VCC max
8
2
IREG max
IO max
Pd max1
Pd max2
Topr
VREG pin
mA
mA
W
UH, VH, WH, UL, VL, and WL outputs
Independent IC
30
Allowable power dissipation 1
Allowable power dissipation 2
Operating temperature
Storage temperature
0.62
* When mounted on the specified PCB
1.79
W
20 to +80
55 to +150
C
C
Tstg
* Specified PCB : 114.3 76.1 1.6 mm glass epoxy PCB
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
September, 2013
D0606 MS IM 20060327-S0004/21604TN (OT) No.7498-1/20
LB11923V
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
VCC
Conditions
Ratings
4.4 to 7.0
0.2 to 1.5
0 to 7
Unit
V
Supply voltage
Input current range
IREG
VFGS
IFGS
VLD
VREG pin (7 V)
mA
V
FG Schmitt output applied voltage
FG Schmitt output current
Lock detection applied voltage
Lock detection output current
0 to 5
mA
V
0 to 7
ILD
0 to 20
mA
Electrical Characteristics at Ta = 25°C, V = 6.3 V
CC
Ratings
typ
21
Parameter
Symbol
Conditions
Unit
min
max
29.5
I
CC1
mA
mA
mA
mA
V
ICC2
In stop mode
VCC = 5 V
2.3
20
3.3
28
Supply current
ICC3
ICC4
VCC = 5 V, In stop mode
2.1
2.9
0.3
1.2
Output saturation voltage 1-1
Output saturation voltage 1-2
Output saturation voltage 2
[Hall Amplifier]
V
O sat1-1 At low level: IO = 400 µA
VO sat1-2 At low level: IO = 10 mA
O sat2 At high level: IO = –20 mA
0.1
0.8
V
V
VCC – 1.2
VCC – 0.9
V
Input bias current
IHB(HA)
–2
–0.1
µA
V
Common-mode input voltage range 1
VICM1
When Hall-effect sensors are used
0.5
VCC – 2.0
When one-side biased inputs are used
(Hall-effect IC applications)
Common-mode input voltage range 2
VICM2
0
VCC
V
Hall input sensitivity
Hysteresis
Sine wave
100
25
mVp-p
mV
∆VIN(HA)
VSLH
35
17
52
29
–9
Input voltage low → high
Input voltage high → low
[PWM Oscillator]
9
mV
VSHL
–29
–18
mV
Output high-level voltage 1
Output high-level voltage 2
Output low-level voltage 1
Output low-level voltage 2
Oscillator frequency
Amplitude 1
V
OH(PWM)1
OH(PWM)2 VCC = 5 V
VOL(PWM)
OL(PWM)2 VCC = 5 V
f(PWM) C = 560 pF
V(PWM)
(PWM)2 VCC = 5 V
3.5
2.75
1.8
3.8
3.0
4.1
3.25
2.4
V
V
V
1
2.1
V
V
1.45
1.65
22
1.9
V
kHz
Vp-p
Vp-p
1
1.4
1.1
1.7
2.0
1.6
Amplitude 2
V
1.35
[CSD Oscillator]
Output high-level voltage 1
Output high-level voltage 2
Output low-level voltage 1
Output low-level voltage 2
External capacitor charge current
External capacitor discharge current
Oscillator frequency
Amplitude 1
VOH(CSD)
1
3.95
3.15
1.1
0.9
–13
8
4.4
3.5
1.4
1.1
–9
4.85
3.85
1.7
1.3
–6
V
V
V
OH(CSD)2 VCC = 5 V
V
OL(CSD)1
V
VOL(CSD)
CHG1
ICHG
f(RK)
V(RK)
2
VCC = 5 V
V
I
µA
µA
Hz
Vp-p
Vp-p
2
12
16
C = 0.068 µF
VCC = 5 V
22
1
2.65
2.1
3.0
2.4
3.35
2.65
Amplitude 2
V
(RK)2
[VCO Oscillator C pin]
Output high-level voltage 1
Output high-level voltage 2
Output low-level voltage 1
Output low-level voltage 2
Oscillator frequency
Amplitude 1
VOH(C)
VOH(C)
1
2.10
2.00
1.60
1.55
2.40
2.30
1.90
1.80
2.65
2.55
2.10
2.05
1.0
V
V
2
VCC = 5 V
V
OL(C)1
OL(C)2 VCC = 5 V
f(C)
(C)1
V(C)
V
V
V
MHz
Vp-p
Vp-p
V
0.3
0.3
0.5
0.5
0.7
Amplitude 2
2
VCC = 5 V
0.7
Continued on next page.
*Note: Not tested
No. 7498-2/20
LB11923V
Continued from preceding page.
Ratings
typ
Parameter
Symbol
VRF
Conditions
Unit
V
min
max
[Current Limiter Operation]
Limiter
0.235
150
0.260
0.285
[Thermal Shutdown Operation]
Thermal shutdown operating temperature
Hysteresis
TTSD
Design target value *
Design target value *
180
30
°C
°C
∆TSD
[VREG Pin]
VREG pin voltage
VREG
I = 500 µA
6.6
7.0
7.4
V
[Low-voltage Protection Circuit]
Operating voltage
VSDL
VSDH
∆VSD
3.55
3.85
0.18
3.75
4.03
0.28
4.00
4.25
0.38
V
V
V
Release voltage
Hysteresis
[FG Amplifier]
Input offset voltage
VIO(FG)
IB(FG)
VOH(FG)
–10
–1
+10
+1
mV
µA
V
Input bias current
Output high-level voltage 1
Output high-level voltage 2
Output low-level voltage 1
Output low-level voltage 2
FG input sensitivity
1
IFGI = –0.1 mA, No load
4.2
3.6
1.3
0.7
3
4.6
3.95
1.7
5.0
4.3
2.1
1.4
V
OH(FG)2 IFGI = –0.1 mA, No load, VCC = 5 V
VOL(FG) IFGI = 0.1 mA, No load
OL(FG)2 IFGI = 0.1 mA, No load, VCC = 5 V
Gain: 100×
V
1
V
V
1.05
V
mV
mV
kHz
dB
V
Schmitt amplitude for the next stage
Operating frequency range
Open-loop gain
100
180
250
4
f
(FG) = 2 kHz
45
51
Reference voltage
VB(FG)
–5%
VCC/2
5%
[FGS Output]
Output saturation voltage
Output leakage current
[Speed Discriminator Output]
Output high-level voltage
Output low-level voltage
[Speed Control PLL Output]
VO(FGS) IO(FGS) = 2 mA
0.2
0.4
10
V
IL(FGS)
VO = VCC
µA
VOH(D)
VOL(D)
VCC – 1.0
VCC – 0.7
0.8
V
V
1.1
VOH(P)
1
4.05
3.25
1.85
1.25
4.30
3.50
2.15
1.60
4.65
3.85
2.45
1.85
V
V
V
V
Output high-level voltage
Output low-level voltage
VOH(P)2 VCC = 5 V
V
OL(P)1
VOL(P)2 VCC = 5 V
[Lock Detection]
Output saturation voltage
Output leakage current
Lock range
VOL(LD) ILD = 10 mA
0.25
0.4
10
V
µA
%
IL(LD)
VO = VCC
–6.25
+6.25
[Integrator]
Input offset voltage
Input bias current
VIO(INT)
IB(INT)
OH(INT)1 IINTI = –0.1 mA, No load
–10
–0.4
4.1
+10
+0.4
4.7
mV
µA
V
Output high-level voltage 1
Output high-level voltage 2
Output low-level voltage 1
Output low-level voltage 2
Open-loop gain
V
4.4
3.7
VOH(INT)
VOL(INT)
2
IINTI = –0.1 mA, No load, VCC = 5 V
IINTI = 0.1 mA, No load
3.45
1.2
3.95
1.65
1.5
V
1
1.4
V
V
OL(INT)2 IINTI = 0.1 mA, No load, VCC = 5 V
1.1
1.3
V
45
51
dB
MHz
V
Gain-bandwidth product
Reference voltage
[FIL Output]
Design target value *
1.0
VB(INT)
–5%
VCC/2
5%
Output source current
Output sink current
IOH(FIL)
IOL(FIL)
–17
7
–13
12
–7
17
µA
µA
Continued on next page.
*Note: Not tested
No. 7498-3/20
LB11923V
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
[S/S Pin]
Input high-level voltage
Input low-level voltage
Input open voltage
Hysteresis
VIH(S/S) VCC = 6.3 V, 5 V
VIL(S/S) VCC = 6.3 V, 5 V
VIO(S/S)
2.0
VCC
V
V
0
VCC – 0.5
0.13
1.0
VCC
0.31
+10
V
∆VIN(S/S) VCC = 6.3 V, 5 V
0.22
0
V
Input high-level current
Input low-level current
Pull-up resistance
[F/R Pin]
IIH(S/S)
IIL(S/S)
RU(S/S)
VS/S = VCC
VS/S = 0 V
–10
µA
µA
kΩ
–170
–118
53.5
37
70
Input high-level voltage
Input low-level voltage
Input open voltage
Hysteresis
VIH(F/R) VCC = 6.3 V, 5 V
VIL(F/R) VCC = 6.3 V, 5 V
VIO(F/R)
2.0
0
VCC
1.0
V
V
VCC – 0.5
0.13
VCC
0.31
+10
V
∆VIN(F/R) VCC = 6.3 V, 5 V
0.22
0
V
Input high-level current
Input low-level current
Pull-up resistance
[BR Pin]
IIH(F/R)
IIL(F/R)
RU(F/R)
VF/R = VCC
VF/R = 0 V
–10
µA
µA
kΩ
–170
37
–118
53.5
70
Input high-level voltage
Input low-level voltage
Input open voltage
Hysteresis
VIH(BR) VCC = 6.3 V, 5 V
VIL(BR) VCC = 6.3 V, 5 V
VIO(BR)
∆VIN(BR) VCC = 6.3 V, 5 V
2.0
0
VCC
1.0
V
V
VCC – 0.5
0.13
VCC
0.31
+10
V
0.22
0
V
Input high-level current
Input low-level current
Pull-up resistance
[CLK Pin]
IIH(BR)
IIL(BR)
RU(BR)
VBR = VCC
VBR = 0 V
–10
µA
µA
kΩ
–170
37
–118
53.5
70
Input high-level voltage
Input low-level voltage
Input open voltage
Hysteresis
VIH(CLK) VCC = 6.3 V, 5 V
VIL(CLK) VCC = 6.3 V, 5 V
VIO(CLK)
2.0
0
VCC
1.0
V
V
VCC – 0.5
0.13
VCC
0.31
+10
V
∆VIN(CLK) VCC = 6.3 V, 5 V, design target value *
0.22
0
V
Input high-level current
Input low-level current
Input frequency
IIH(CLK) VCLK = VCC
–10
µA
µA
kHz
kΩ
IIL(CLK)
f(CLK)
VCLK = 0 V
–170
–118
3.9
70
Pull-up resistance
[N1 Pin]
RU(CLK)
37
53.5
Input high-level voltage
Input low-level voltage
Input open voltage
Hysteresis
VIH(N1)
VIL(N1)
VIO(N1)
VCC = 6.3 V, 5 V
VCC = 6.3 V, 5 V
2.0
0
VCC
1.0
V
V
VCC – 0.5
0.13
VCC
0.31
+10
V
∆VIN(N1) VCC = 6.3 V, 5 V, design target value *
0.22
0
V
Input high-level current
Input low-level current
Pull-up resistance
[N2 Pin]
IIH(N1)
IIL(N1)
RU(N1)
VN1 = VCC
VN1 = 0 V
–10
µA
µA
kΩ
–170
37
–118
53.5
70
Input high-level voltage
Input low-level voltage
Input open voltage
Hysteresis
VIH(N2)
VIL(N2)
VIO(N2)
VCC = 6.3 V, 5 V
VCC = 6.3 V, 5 V
2.0
0
VCC
1.0
V
V
VCC – 0.5
0.13
VCC
0.31
+10
V
∆VIN(N2) VCC = 6.3 V, 5 V, design target value *
0.22
0
V
Input high-level current
Input low-level current
Pull-up resistance
IIH(N2)
IIL(N2)
RU(N2)
VN2 = VCC
VN2 = 0 V
–10
µA
µA
kΩ
–170
37
–118
53.5
70
*Note: Not tested
No. 7498-4/20
LB11923V
Package Dimensions
unit : mm (typ)
3277
15.0
23
44
22
1
0.65
0.22
0.2
(0.68)
SSOP44(275mil)
Pd max – Ta
2.0
1.5
1.0
0.5
Mounted on the specified PCB
(114.3 × 76.1 × 1.6 mm glass epoxy PCB)
1.79 W
1.002 W
0.347 W
0.62 W Independent IC
0
–20
0
20
40
60
80
100
Ambient temperature, Ta – °C
ILB01550
Pin Assignment
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
LB11923V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
Top view
No. 7498-5/20
LB11923V
Speed Discriminator Count and VCO Divisor
N1
High or open
High or open
Low
N2
High or open
Low
Count
1024
1024
256
Divisor
1024
512
High or open
Low
256
Low
512
512
f
FG
= (divisor ÷ count) × f
CLK
Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN–.)
F / R = L
F / R = H
Output
PWM
Item
IN1
H
H
H
L
IN2
L
IN3
H
L
IN1
L
IN2
H
H
L
IN3
L
—
UL
UL
VL
VL
WL
WL
1
2
3
4
5
6
VH
WH
WH
UH
UH
VH
L
L
H
H
H
L
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
L
H
L
S/S Pin
BR Pin
High or open
Low
Stop
Start
High or open
Low
Brake
Released
No. 7498-6/20
LB11923V
Block Diagram
WH
VH
UH
WL
VL
HALL
HYS
AMP
CSD
OSC
LOGIC
FR
F/R
PRI
DRIVER
V
CC
UL
LOGIC
BR
BR
TSD
TOC
RF
S/S
S/S
INT
OUT
CURR
LIM
COMP
RFGND
RES
INT
IN
1.3VREF
PWM
OSC
V
CC
PWM
GND
LVSD
INT
REF
POUT
LD
LD
N2
N1
N2
N1
SPEED
DISCRI
SPEED
PLL
1/N
DOUT
FG
FGS
FILTER
R
C
VCO
VCO
PLL
FIL
FGO
FIL
VREG
CLK
V
CC
No. 7498-7/20
LB11923V
Pin Functions
Pin No.
Pin
Functions
Equivalent circuit
1
V
1
CC
1
VREG
7-V shunt regulator output
V
1
CC
Start/stop control
Low: 0 V to 1.0 V
High: 2.0 V to VCC
Goes high when left open.
Low for start.
3.5 kΩ
2
2
S/S
High or open for stop.
The hysteresis is about 0.22 V.
V
1
CC
External clock signal input
Low: 0 V to 1.0 V
High: 2.0 V to VCC
3.5 kΩ
3
CLK
3
Goes high when left open.
The hysteresis is about 0.22 V.
f = 3.9 kHz, maximum
V
1
CC
Forward/reverse control
Low: 0 V to 1.0 V
High: 2.0 V to VCC
Goes high when left open.
Low for forward.
3.5 kΩ
4
4
F/R
High or open for reverse.
The hysteresis is about 0.22 V.
Continued on next page.
No. 7498-8/20
LB11923V
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
V
1
CC
Brake control (short braking operation)
Low: 0 V to 1.0 V
High: 2.0 V to VCC
3.5 kΩ
5
5
BR
Goes high when left open.
High or open for brake mode operation.
The hysteresis is about 0.22 V.
V
1
CC
Switches the speed discriminator VCO divisor count.
Low: 0 V to 1.0 V
High: 2.0 V to VCC
3.5 kΩ
6
6
N1
Goes high when left open.
The hysteresis is about 0.22 V.
V
1
CC
The speed discriminator count switching.
Low: 0 V to 1.0 V
High: 2.0 V to VCC
3.5 kΩ
7
N2
7
Goes high when left open.
The hysteresis is about 0.22 V.
V
1
CC
8
FG amplifier output (after the Schmitt circuit)
This is an open collector output.
8
FGS
V
1
CC
9
Speed lock detection output
This is an open collector output.
Goes low when the motor speed is within the speed lock
range (±6.25%).
9
LD
Continued on next page.
No. 7498-9/20
LB11923V
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
1
V
CC
Speed discriminator output
Acceleration → high, deceleration → low
10
DOUT
10
V
1
CC
Speed control system PLL output
Outputs the phase comparison result for
CLK and FG.
11
11
POUT
V
1
CC
Integrating amplifier non-inverting input (1/2 VCC potential)
13
14
INT REF
500 Ω
500 Ω
INT IN
Integrating amplifier inverting input
13
14
V
1
CC
15
INT OUT
Integrating amplifier output (speed control)
15
Continued on next page.
No. 7498-10/20
LB11923V
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
1
V
CC
Torque command input
Normally, this pin is connected to the INT.OUT pin. The
PWM duty is increased when the TOC pin voltage falls.
Do not apply a voltage that exceeds VCC – 0.5 V to this pin.
(An input from a normal operational amplifier is desirable.)
16
TOC
300 Ω
16
V
1
CC
PWM oscillator frequency setting.
Connect a capacitor between this pin and ground.
17
19
20
PWM
FIL
R
300 Ω
17
V
1
CC
VCO PLL filter connection
300 Ω
19
V
1
CC
Sets the value of the charge current from the VCO circuit C
pin.
Insert a resistor between this pin and ground.
300 Ω
20
Continued on next page.
No. 7498-11/20
LB11923V
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
V
1
CC
VCO oscillator connection
This pin sets the VCO frequency.
C
300 Ω
21
Insert a capacitor between this pin and ground.
Set the value of the capacitor so that the oscillator
frequency does not exceed 1 MHz.
21
Reset circuit
V
1
CC
Sets the operating time of the constrained-rotor protection
circuit.
Reference signal oscillator used when the clock signal is cut
off and to prevent malfunctions.
The protection function operating time can be set by
connecting a capacitor between this pin and ground.
This pin also functions as the logic circuit block power-on
reset pin.
300 Ω
22
22
CSD
500 Ω
FGOUT
V
1
CC
FGIN+
FGIN–
23
24
FG amplifier input
500 Ω
500 Ω
23
24
V
1
CC
FG amplifier output
This pin is connected to the FG Schmitt comparator circuit
internally in the IC.
25
25
FGOUT
FG Schmitt comparator
V
1
CC
Output current detection
Connect a resistor between this pin and ground.
27
27
RF GND
Continued on next page.
No. 7498-12/20
LB11923V
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
V
1
CC
Output current detection
Connect a resistor between this pin and ground.
The output limitation maximum current, IOUT, is set to be
0.26/Rf by this resistor.
28
28
RF
29
30
GND1
GND2
Control block ground
Output block ground
V
2
CC
31
32
33
34
35
36
UL
UH
VL
VH
WL
WH
Outputs (that are used to drive external transistors).
The PWM duty is controlled on the UH, VH, and WH side of
these outputs.
31 33 35
32 34 36
Output block power supply
VCC
2
37
38
Control block power supply
Short VCC1 to VCC2 and, for stability, insert a capacitor
between these pins and ground.
V
CC1
V
1
CC
Hall-effect device inputs.
The input is seen as a high-level input when IN+ > IN–, and
as a low-level input for the opposite state.
If noise on the Hall-effect device signals is a problem, insert
capacitors between the corresponding IN+ and IN– inputs.
IN3–
IN3+
IN2–
IN2+
IN1–
IN1+
39
40
41
42
43
44
500 Ω
500 Ω
40 42 44
39 41 43
The logic high state indicates that VIN+ > VIN
–
12
18
26
NC
These are unconnected pins, and can be used for wiring.
No. 7498-13/20
LB11923V
Sample Application Circuit 1 (P-channel + n-channel, Hall-effect sensor application)
1
2
VREG
S/S
IN1+
44
IN1– 43
IN2+ 42
IN2– 41
IN3+ 40
IN3– 39
S/S
CLK
F/R
BR
3
CLK
F/R
4
5
BR
6
N1
N1
+
7
N2
V
1
2
38
37
N2
CC
8
FGS
LD
V
FGS
LD
CC
9
WH 36
WL 35
VH 34
10
11
DOUT
POUT
LB11923V
12 NC
13
VL
UH
UL
33
32
31
INT.REF
14
15
16
17
18
19
20
21
22
INT.IN
INT.OUT
TOC
PWM
NC
GND2 30
GND1 29
RF 28
RFGND 27
NC 26
FIL
R
FGOUT 25
FGIN– 24
FGIN+ 23
+
C
24 V
CSD
Top view
No. 7498-14/20
LB11923V
Sample Application Circuit 2 (PNP + NPN, Hall-effect sensor application)
VREG
S/S
IN1+
44
1
2
IN1– 43
IN2+ 42
IN2– 41
IN3+ 40
IN3– 39
S/S
CLK
F/R
BR
CLK
F/R
3
4
BR
5
N1
6
N1
+
N2
V
1 38
2 37
7
N2
CC
FGS
LD
V
8
FGS
LD
CC
WH 36
WL 35
VH 34
9
DOUT
POUT
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
LB11923V
VL
UH
UL
33
32
31
INT.REF
INT.IN
INT.OUT
TOC
PWM
NC
GND2 30
GND1 29
RF 28
RFGND 27
NC 26
FIL
R
FGOUT 25
FGIN– 24
FGIIN+ 23
C
CSD
+
24 V
Top view
No. 7498-15/20
LB11923V
IC Operation Description
1. Speed Control Circuit
This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed
discriminator circuit outputs (This counts a single FG period.) an error signal once every two FG periods. The PLL
circuit outputs an error signal once every one FG Period. As compared to the earlier technique in which only a speed
discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in motor
speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency (fFG) is
determined by the frequency relationship shown below and by the clock signal (fCLK) input to the CCLK pin.
f
FG
= (VCO divisor ÷ speed discriminator count) × f
CLK
N1
High or open
High or open
Low
N2
High or open
Low
Count
1024
1024
256
Divisor
1024
512
High or open
Low
256
Low
512
512
Therefore it is possible to implement half-speed control without switching the clock frequency by using combinations
of the N1 = high, N2 = low state and other setting states.
2. VCO Circuit
The LB11923V includes a built-in VCO circuit to generate the speed discriminator circuit reference signal. The
reference signal frequency is given by the following formula.
f
= f
× divisor
f
: Reference signal frequency
VCO
VCO
CLK
f : Externally input clock frequency
CLK
The range over which the reference signal frequency can be varied is determined by the resistor and capacitor
components connected to the R and C pins (pins 20 and 21) and by the VCO loop filter constant (the values of the
external components connected to pin 19).
Supply voltage
When VCC is 5 V
When VCC is 6.3 V
R (kΩ)
7.5
C (pF)
200
11
200
To acquire the widest possible range, it is better to use 6.3 V than 5 V as the supply voltage. It is also possible to
handle an even wider range than is possible with fixed counts by making the speed discriminator count and the VCO
divisor switchable.
The components connected to the R, C, and FIL pins must be connected with lines to their ground pins (pins 29 and
30) that are as short as possible.
3. Output Drive Circuit
To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are
external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with
which the output is on. The PWM switching is performed on the high side for each phase (UH, VH, and WH). The
PWM switching side in the output can be selected to be either the high or low side depending on how the external
transistors are connected.
4. Current Limiter Circuit
The current limiter circuit limits the (peak) current at the value I = V /R (V = 0.26 V (typical), R : current
RF
f
RF
f
detection resistor). The current limitation operation consists of reducing the output duty to suppress the current.
High accuracy detection can be achieved by connecting the RF and RFGND pin lines near the ends of the current
detection resistor (Rf).
5. Speed Lock Range
The speed lock range is ±6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open
collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to
the speed error to control the motor speed to be within the lock range.
No. 7498-16/20
LB11923V
6. Notes on the PWM Frequency
The PWM frequency is determined by the capacitor (F) connected to the PWM pin.
When V = 6.3 V: f
≈ 1/(82000 × C)
≈ 1/(66000 × C)
CC
PWM
PWM
When V = 5.0 V: f
CC
A PWM frequency of between 15 and 25 kHz is desirable. If the PWM frequency is too low, the motor may resonate
at the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result
in audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. To make the
circuit less susceptible to noise, the connected capacitors must be connected to the GND pin (pin 29 and pin 30) with
lines that are as short as possible.
7. Hall effect sensor input signals
An input amplitude of over 100 mV p-p is desirable in the Hall effect sensor inputs. The closer the input waveform is
to a square wave, the lower the required input amplitude. Inversely, a higher input amplitude is required the closer the
input waveform is to a triangular wave. Also note that the input DC voltage must be set to be within the common-
mode input voltage range.
If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those
capacitors must be located as close as possible to the input pins.
When the Hall inputs for all three phases are in the same state, all the outputs will be in the off state.
If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of
the Hall effect sensor signal inputs as 0 to VCC level signals if the other side is held fixed at a voltage within the
common-mode input voltage range that applies when a Hall effect sensors are used.
8. Forward/Reverse Switching
The motor rotation direction can be switched using the F/R pin. However, the following notes must be observed if the
motor direction is switched while the motor is turning.
• This IC is designed to avoid through currents when switching directions. However, increases in the motor supply
voltage (due to instantaneous return of motor current to the power supply) during direction switching may cause
problems. The values of the capacitors inserted between power and ground must be increased if this increase is
excessive.
• If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be
turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the
motor back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does
not exceed the ratings of the output transistors used. (The higher the motor speed at which the direction is
switched, the more severe this problem becomes.)
9. Brake Switching
The LB11923V provides short-circuit braking implemented by turning the output transistors for the high side for all
phases (UH, VH, and WH) on. (The opposite side transistors are turned off for all phases.) Note that the current
limiter does not operate during braking. During braking, the duty is set to 100%, regardless of the motor speed. The
current that flows in the output transistors during braking is determined by the motor back EMF voltage and the coil
resistance. Applications must be designed so that this current does not exceed the ratings of the output transistors
used. (The higher the motor speed at which braking is applied, the more severe this problem becomes.)
The braking function can be applied and released with the IC in the start state. This means that motor startup and stop
control can be performed using the brake pin with the S/S pin held at the low level (the start state). If the startup time
becomes excessive, it can be reduced by controlling motor startup and stop with the brake pin rather than with the S/S
pin. (Since the IC goes to the power saving state when stopped, enough time for the VCO circuit to stabilize will be
required at the beginning of the motor start operation.)
10. Constraint Protection Circuit
The LB11923V includes an on-chip constraint protection circuit to protect the IC and the motor in motor constraint
mode. If the LD output remains high (indicating the locked state) for a fixed period in the start state, the upper side
(external) transistors are turned off. This time is set by the capacitance of the capacitor attached to the CROCK pin. A
time of a few seconds can be set with a capacitance of under 0.1 µF.
No. 7498-17/20
LB11923V
When V = 6.3 V: The set time (in seconds) is 37 × C (µF)
CC
When V = 5.0 V: The set time (in seconds) is 30 × C (µF)
CC
To clear the rotor constrained protection state, the application must either switch to the stop state for a fixed period
(about 1 ms or longer) or turn off and reapply power.
If the rotor constrained protection circuit is not used, a 220 kΩ resistor and a 1500 pF capacitor must be connected in
parallel between the CSD pin and ground. However, in that case, the clock disconnect protection circuit described
below will no longer function. Since the CSD pin also functions as the power-on reset pin, if the CSD pin were
connected directly to ground, the IC would go to the power-on reset state and motor drive operation would remain
off. The power-on reset state is cleared when the CSD pin voltage rises above a level of about 0.64 V.
11. Clock Disconnect Protection Circuit
If the clock input goes to the no input state when the IC is in the start state, this protection circuit will operate and
turn off the PWM output. If the clock is resupplied before the motor constraint protection circuit operates, the IC will
return to the drive state, but if the motor constraint protection circuit does operate, the IC must either be set
temporarily (approximately 1 ms or over) to the stop or brake state, or the power must be turned off and reapplied.
12. Low-Voltage Protection Circuit
The LB11923V includes a low-voltage protection circuit to protect against incorrect operation when power is first
applied or if the power-supply voltage (V ) falls. The (external) all output transistors are turned off if V falls
CC
CC
under about 3.75 volts, and this function is cleared at about 4.0 volts.
13. Power Supply Stabilization
Since this IC is used in applications that draw large output currents, the power-supply line is subject to fluctuations.
Therefore, capacitors with capacitances adequate to stabilize the power-supply voltage must be connected between
the V pin and ground. If diodes are inserted in the power-supply line to prevent IC destruction due to reverse
CC
power supply connection, since this makes the power-supply voltage even more subject to fluctuations, even larger
capacitors will be required.
14. Ground Lines
The signal system ground and the output system ground must be separated and a single ground point must be taken at
the connector. Since the output system ground carries large currents, this ground line must be made as short as
possible.
Output system ground ... Ground for R and the output diodes
f
Signal system ground ... Ground for the IC and the IC external components
15. V
Pin
REG
If a motor drive system is formed from a single power supply, the V
pin (pin 1) can be used to create the power-
REG
supply voltage (about 6.3 V) for this IC. The V
pin is a shunt regulator and generates a voltage of about 7 volts by
REG
passing a current through an external resistor. A stable voltage can be generated by setting the current to value in the
range 0.2 to 1.5 mA. The external transistors must have current capacities of at least 80 mA (to cover the I + Hall
CC
bias current + output current <source> requirements) and they must have voltage handling capacities in excess of the
motor power-supply voltage. Since the heat generated by these transistor may be a problem, heat sinks may be
required depending on the packages used. If the IC power-supply voltage (4.4 to 7.0 V) is provided from an external
circuit, apply that voltage directly to the V pin(pin 37 and pin 38). In that case, the V
pin must either be left
REG
CC
open or connected to ground.
16. FG Amplifier
The FG amplifier is normally implemented as a filter amplifier such as that shown in the application circuits to reject
noise. Since a clamp circuit has been added at the FG amplifier output, the output amplitude is clamped at about
3 V p-p, even if the gain is increased.
Since a Schmitt comparator is inserted after the FG amplifier, applications must set the gain so that the amplifier
output amplitude is at least 250 mV p-p. (It is desirable that the gain be set so that the amplitude is over 0.5 V p-p at
the lowest controlled speed to be used.)
+
The capacitor inserted between the FGIN pin (pin 23) and ground is required for bias voltage stabilization. To make
the connected capacitor as immune from noise as possible, connect this capacitor to the GND pin (pin 29 and pin 30)
with a line that is as short as possible.
No. 7498-18/20
LB11923V
17. Integrating Amplifier
The integrating amplifier integrates the speed error pulses and the phase error pulses and converts them to a speed
command voltage. At the same time it also sets the control loop gain and frequency characteristics using external
components.
The integrating amplifier output (pin 15) is normally connected to the TOC pin (pin 16) using external wiring. In
cases where it is necessary to switch the integration constant in an application that uses a wide speed range by
isolating the integrating amplifier output and the PWM control circuit, this type of constant switching application can
be implemented by adding external operational amplifier, analog switch, and other components.
In either case, the basic idea is that the operational amplifier output is connected to the TOC pin. (Note that voltages
in excess of V – 0.5 V must not be applied to the TOC pin.)
CC
18. FIL Pin External Components
The capacitor inserted between the FIL pin and ground is used to suppress ripple on the FIL pin voltage. Therefore,
application designers must select a capacitance value that provides fully adequate smoothing of the FIL pin voltage
even at the lowest external clock input frequency used. Also, the FIL pin voltage convergence time (the time until the
reference signal stabilizes) when the input clock frequency is switched is shortened by connecting a resistor and a
capacitor in series between the FIL pin and ground. Therefore, designers must select values for the resistor and
capacitor that give the required convergence time.
19. R and C Pin External Components
The maximum range over which the reference signal frequency f
supply voltage is about a factor of three.
can be varied when 5 V is used as the V
CC
VCO
When it is desirable to make this range as wide as possible, since the values of the R pin external resistor (R) and the
C pin external capacitor (C) are determined by the maximum value of the reference signal frequency (f 1) and the
VCO
minimum value (V L) of the V power supply due to unit-to-unit variations, R and C can be determined using the
CC
CC
following procedure as a reference.
(1) Calculate R1 and C1 using the following formulas and determine values for R and C such that the conditions R ≤
R1 and C ≤ C1 will hold taking the sample-to-sample variations (including other issues such as temperature
characteristics) into account.
R1 = (V L – 2.2 V) / 280 µA
CC
C1 = (280 µA / 0.9 V) × (1/f 1) × 0.7
VCO
(2) The minimum value (f 2) for the reference signal frequency that can be set for the R and C values determined
VCO
in step (1) can be calculated from the following formula if we let R2 and C2 be the smallest values for R and C
due to the sample-to-sample variations (including other issues such as temperature characteristics). Therefore, the
range over which the reference signal frequency can be set is f
1 to f
VCO
2.
VCO
f 2 = 0.38 / (R2 × C2)
VCO
(3) The following are the conditions that must be met and the points that require care when determining the values of
the external components connected to the R and C pins.
1. The maximum value of the set reference signal frequency must not exceed 1 MHz.
2. The R pin voltage and the FIL pin voltage must be in the range 0.3 V to (V L – 2.2 V). (V L is the lowest
CC
CC
value of the V supply voltage given the unit-to-unit variations. V L is always greater than or equal to 4.4
CC
CC
V.) However, the lower the R pin voltage, the more susceptible the system will be to ground line noise, and the
reference signal frequency may become unstable as a result. Therefore the lower end of the R pin voltage range
must not be used if there is much ground line noise in the system.
3. Set the value of the R pin external resistor to a value in the range 6.8 kΩ to 15 kΩ. Also, assure that the R pin
current remains under 280 µA.
4. Set the value of the C pin external capacitor to a value in the range 150 pF to 1000 pF.
5. When it is desirable to make the range of the reference signal frequency as wide as possible, set the values of R
and C to the largest possible values. (However, those values must be lower than the calculated values R1 and
C1.) Use components with the smallest sample-to-sample variations possible. The V voltage must be made
CC
as much higher than 5 V as possible by, for example, using this IC’s VREG pin (7 V shunt regulator), to
acquire the widest possible range for the reference signal frequency.
No. 7498-19/20
LB11923V
20. NC pin
Since the NC pins are electrically open with respect to the IC itself, they can be used as intermediate connection
points for lines in the PCB pattern.
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warranty, representation or guarantee regarding the suitabilityof its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
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PS No.7498-20/20
相关型号：
LB11948T
Monolithic Digital IC PWM Constant Current Control 1-2 Phase Excitation Stepping Motor Driver
SANYO
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