KAE-01093-QBB-SD-FA [ONSEMI]
1024 (H) x 1024 (V) Interline Transfer EMCCD Image Sensor;型号: | KAE-01093-QBB-SD-FA |
厂家: | ONSEMI |
描述: | 1024 (H) x 1024 (V) Interline Transfer EMCCD Image Sensor CD |
文件: | 总39页 (文件大小:1902K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
KAE-01093
1024 (H) x 1024 (V) Interline
Transfer EMCCD Image Sensor
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Interline CCD; with EMCCD
1.0 Megapixels
Architecture
Resolution
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Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
1064 (H) × 1064 (V)
1040 (H) × 1040 (V)
1024 (H) × 1024 (V)
9.0Ămm (H) × 9.0Ămm (V)
Active Image Size
9.21 mm (H) × 9.21 mm (V)
13.0 mm (Diagonal)
1″ Optical Format
Aspect Ratio
1:1
Number of Outputs
2, or 4
−
−
Charge Capacity − VOUT2 / VOUT3
Output Sensitivity − VOUT2 / VOUT3
60,000 e / 30,000 e
−
−
Figure 1. KAE−01093 Interline
16.5ĂmV/e / 44ĂmV/e
Transfer EMCCD Image Sensor
Quantum Efficiency
Mono (500, 850, 920 nm) / R,G,B
(54%, 16%, 8%) / 44%, 48%, 43%
Read Noise (40 MHz)
Normal Mode (1× Gain)
Intra-scene Mode (20× Gain)
Dark Current (0°C)
Photodiode, VCCD
Features
< 20 electrons rms
< 1 electron rms
• Increased QE, with 2× Improvement at
820 nm
• 91 fps (4 Outputs); 144 fps (Binned)
• Intra-scene Switchable Gain
• Wide Dynamic Range
< 0.1, 8 electrons/s
Dynamic Range
Normal Mode (1× Gain)
Intra-scene Mode (20× Gain)
Charge Transfer Efficiency
Blooming Suppression
Smear
69 dB
95 dB
0.999999
> 500 X
• Low Noise Architecture
• Exceptional Low Light Imaging
• Global Shutter
−115 dB
< 1 electron
40 MHz
Image Lag
Maximum Data Rate
• Excellent Image Uniformity and MTF
Maximum Frame Rate
Normal Mode (40 MHz)
Intra-scene mode (40 MHz)
2x2 binning (40 MHz)
91 fps (quad), 52 fps (dual)
91 fps (quad), 52 fps (dual)
144 fps (quad), 91 fps (dual)
Applications
• Surveillance
• Scientific Imaging
• Medical Imaging
Package
148 pin PGA with TEC
MAR, Sealed
Cover Glass
NOTE: All Parameters are specified at T = 0°C unless otherwise noted.
• Situational Awareness (Ground Vehicles)
Description
The KAE−01093 Image Sensor is a 1 megapixel 1024 × 1024 CCD
in a 1″ optical format that provides enhanced Quantum Efficiency
(particularly for NIR wavelengths) without a decrease in Modulation
Transfer Function (MTF). In quad mode, the KAE−01093 runs at
91 fps. Each of the sensor’s four outputs incorporate both
a conventional horizontal CCD register and a high gain EMCCD
register. An intra-scene switchable gain feature samples each charge
packet on a pixel-by-pixel basis. This enables the camera system to
determine whether the charge will be routed through the normal gain
output or the EMCCD output based on a user selectable threshold.
Cameras can thus image in extreme low light even when bright objects
are within a dark scene, allowing a single camera to capture quality
images from sunlight to starlight.
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
August, 2019 − Rev. 0
KAE−01093/D
KAE−01093
ORDERING INFORMATION
US export controls apply to all shipments of this product
designated for destinations outside of the US and Canada,
requiring ON Semiconductor to obtain an export license
from the US Department of Commerce before image sensors
or evaluation kits can be exported.
Table 2. ORDERING INFORMATION − KAE−01093 IMAGE SENSOR
Part Number
Description
Marking Code
KAE−01093−ABB−SD−FA
Monochrome, Microlens, PGA Package, TEC, Sealed MAR Cover Glass,
Standard Grade
KAE−01093−ABB
Serial Number
KAE−01093−ABB−SD−EE
KAE−01093−FBB−SD−FA
KAE−01093−FBB−SD−EE
KAE−01093−QBB−SD−FA
KAE−01093−QBB−SD−EE
Monochrome, Microlens, PGA Package, TEC, Sealed MAR Cover Glass,
Engineering Grade
Gen2 Color (Bayer RGB), Microlens, PGA Package, TEC, Sealed MAR
Cover Glass, Standard Grade
KAE−01093−FBB
Serial Number
Gen2 Color (Bayer RGB), Microlens, PGA Package, TEC, Sealed MAR
Cover Glass, Engineering Grade
Gen2 Color (Sparse CFA), Microlens, PGA Package, TEC, Sealed MAR
Cover Glass, Standard Grade
KAE−01093−QBB
Serial Number
Gen2 Color (Sparse CFA), Microlens, PGA Package, TEC, Sealed MAR
Cover Glass, Engineering Grade
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
Warning
The KAE−01093−ABB−SD and KAE−01093−FBB−SD,
and KAE−01093−QBB−SD packages have an integrated
thermoelectric cooler (TEC) and have epoxy sealed cover
glass. The seal formed is non-hermetic, and may allow
moisture ingress over time, depending on the storage
environment.
Please address all inquiries and purchase orders to:
ON Semiconductor
1964 Lake Avenue
Rochester, New York 14615
Phone: (585) 784−5500
As a result, care must be taken to avoid cooling the device
below the dew point inside the package cavity, since this
may result in condensation on the sensor.
For all KAE−01093 configurations, no warranty,
expressed or implied, covers condensation.
ON Semiconductor reserves the right to change any
information contained herein without notice. All
information furnished by ON Semiconductor is believed to
be accurate.
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KAE−01093
DEVICE DESCRIPTION
Architecture
Quadrant c
Quadrant d
Quadrant a
Quadrant b
Figure 2. Block Diagram
Dark Reference Pixels
Image Acquisition
There are 12 dark reference rows at the top and bottom of
the image sensor, as well as 12 dark reference columns on the
left and right sides. However, the rows and columns at the
perimeter edges should not be included in acquiring a dark
reference signal, since they may be subject to some light
leakage.
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photo-site. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
Active Buffer Pixels
8 unshielded pixels adjacent to any leading or trailing dark
reference regions are classified as active buffer pixels. These
pixels are light sensitive but are not tested for defects and
non-uniformities.
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KAE−01093
24
Figure 3. Bayer Color Filter Pattern
Sparse Color Filter Pattern
24
Figure 4. Sparse Color Filter Pattern
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KAE−01093
Physical Description
Pin Grid Array Configuration
Figure 5. PGA Package Pin Designations (Bottom View)
Table 3. PIN DESCRIPTION
Pin No.
A3
Label
VDD2a
H2SW3a
RG23a
VDD3a
H1BEMa
H2SEMa
H2a
Description
Amplifier 2 Supply, Quadrant a
A4
HCCD Output 3 Selector, Quadrant a
Amplifier 2 and 3 Reset, Quadrant a
Amplifier 3 Supply, Quadrant a
A5
A6
A7
EMCCD Barrier Phase 1, Quadrant a
EMCCD Storage Phase 2, Quadrant a
HCCD Phase 2, Quadrant a
A8
A9
A10
A11
A12
A13
A14
A15
A16
H1Sa
HCCD Storage Phase 1, Quadrant a
HCCD Barrier Phase 2, Quadrant a
HCCD Barrier Phase 3, Quadrant a
HCCD Barrier Phase 3, Quadrant b
HCCD Barrier Phase 2, Quadrant b
HCCD Storage Phase 1, Quadrant b
HCCD Phase 2, Quadrant b
H2Ba
H3Ba
H3Bb
H2Bb
H1Sb
H2b
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KAE−01093
Table 3. PIN DESCRIPTION (continued)
Pin No.
A17
A18
A19
A20
A21
A22
B2
Label
H2SEMb
H1BEMb
VDD3b
RG23b
H2SW3b
VDD2b
VOUT1a
H2Xa
Description
EMCCD Storage Multiplier Phase 2, Quadrant b
EMCCD Barrier Phase 1, Quadrant b
Amplifier 3 Supply, Quadrant b
Amplifier 2 and 3 Reset, Quadrant b
HCCD Output 3 Selector, Quadrant b
Amplifier 2 Supply, Quadrant b
Video Output 1, Quadrant a
B3
Floating Gate Exit HCCD Gate, Quadrant a
HCCD Output 2 Selector, Quadrant a
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant a
Video Output 3, Quadrant a
B4
H2SW2a
H2La
B5
B6
VOUT3a
H1SEMa
H2BEMa
H1a
B7
EMCCD Storage Multiplier Phase 1, Quadrant a
EMCCD Barrier Phase 1, Quadrant a
HCCD Phase 1, Quadrant a
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
H2Sa
HCCD Storage Phase 2, Quadrant a
HCCD Storage Phase 3, Quadrant a
HCCD Barrier Phase 1, Quadrant a
HCCD Barrier Phase 1, Quadrant b
HCCD Storage Phase 3, Quadrant b
HCCD Storage Phase 2, Quadrant b
HCCD Phase 1, Quadrant b
H3Sa
H1Ba
H1Bb
H3Sb
H2Sb
H1b
H2BEMb
H1SEMb
VOUT3b
H2Lb
EMCCD Barrier Phase 2, Quadrant b
EMCCD Storage Multiplier Phase 1, Quadrant b
Video Output 3, Quadrant b
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant b
HCCD Output 2 Selector, Quadrant b
Floating Gate Exit HCCD Gate, Quadrant b
Video Output 1, Quadrant b
H2SW2b
H2Xb
VOUT1b
V3B
VCCD Bottom Phase 3
C2
VDD1a
RG1a
Amplifier 1 Supply, Quadrant a
C3
Amplifier 1 Reset, Quadrant a
C4
VOUT2a
VOUT2b
RG1b
Video Output 2, Quadrant a
C21
C22
C23
C24
D1
Video Output 2, Quadrant b
Amplifier 1 Reset, Quadrant b
VDD1b
V3B
Amplifier 1 Supply, Quadrant b
VCCD Bottom Phase 3
V2B
VCCD Bottom Phase 2
D2
OG1a
Output 1 Gate, Quadrant a
D3
VSS1a
Amplifier 1 Return, Quadrant a
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KAE−01093
Table 3. PIN DESCRIPTION (continued)
Pin No.
D22
D23
D24
E1
Label
VSS1b
OG1b
V2B
Description
Amplifier 1 Return, Quadrant b
Output 1 Gate, Quadrant b
VCCD Bottom Phase 2
VCCD Bottom Phase 1
VCCD Bottom Phase 4
ESD Protection Disable
ESD Protection Disable
VCCD Bottom Phase 4
VCCD Bottom Phase 1
Ground
V1B
E2
V4B
E3
ESD
E22
E23
E24
F1
ESD
V4B
V1B
GND
GND
GND
GND
GND
GND
VDD15
SUBREF
THERM2
TEC−
TEC−
TEC−
SUB
F2
Ground
F3
Ground
F22
F23
F24
G1
Ground
Ground
Ground
+15 V Supply
G2
Substrate Voltage Reference
Thermistor Terminal 2
Thermal Electric Cooler Negative Terminal
Thermal Electric Cooler Negative Terminal
Thermal Electric Cooler Negative Terminal
Substrate
G3
G22
G23
G24
H1
H2
SUB
Substrate
H3
THERM1
TEC+
TEC+
TEC+
GND
GND
GND
GND
GND
V1T
Thermistor Terminal 1
Thermal Electric Cooler Positive Terminal
Thermal Electric Cooler Positive Terminal
Thermal Electric Cooler Positive Terminal
Ground
H22
H23
H24
I1
I2
Ground
I22
I23
I24
J1
Ground
Ground
Ground
VCCD Top Phase 1
VCCD Top Phase 4
Device ID
J2
V4T
J3
ID
J22
J23
J24
K1
VDD15
V4T
+15 V Supply
VCCD Top Phase 4
VCCD Top Phase 1
VCCD Top Phase 2
V1T
V2T
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KAE−01093
Table 3. PIN DESCRIPTION (continued)
Pin No.
K2
Label
OG1c
Description
Output 1 Gate, Quadrant c
K3
VSS1c
VSS1d
OG1d
Amplifier 1 Return, Quadrant c
Amplifier 1 Return, Quadrant d
Output 1 Gate, Quadrant d
K22
K23
K24
L1
V2T
VCCD Top Phase 2
V3T
VCCD Top Phase 3
L2
VDD1c
RG1c
Amplifier 1 Supply, Quadrant c
Amplifier 1 Reset, Quadrant c
L3
L4
VOUT2c
VOUT2d
RG1d
Video Output 2, Quadrant c
L21
L22
L23
L24
M2
Video Output 2, Quadrant d
Amplifier 1 Reset, Quadrant d
VDD1d
V3T
Amplifier 1 Supply, Quadrant d
VCCD Top Phase 3
VOUT1c
H2Xc
Video Output 1, Quadrant c
M3
Floating Gate Exit HCCD Gate, Quadrant c
HCCD Output 2 Selector, Quadrant c
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant c
Video Output 3, Quadrant c
M4
H2SW2c
H2Lc
M5
M6
VOUT3c
H1SEMc
H2BEMc
H1c
M7
EMCCD Storage Multiplier Phase 1, Quadrant c
EMCCD Barrier Phase 2, Quadrant c
HCCD Phase 1, Quadrant c
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
N3
H2Sc
HCCD Storage Phase 2, Quadrant c
HCCD Storage Phase 3, Quadrant c
HCCD Barrier Phase 1, Quadrant c
HCCD Barrier Phase 1, Quadrant d
HCCD Storage Phase 3, Quadrant d
HCCD Storage Phase 2, Quadrant d
HCCD Phase 1, Quadrant d
H3Sc
H1Bc
H1Bd
H3Sd
H2Sd
H1d
H2BEMd
H1SEMd
VOUT3d
H2Ld
EMCCD Barrier Phase 2, Quadrant d
EMCCD Storage Multiplier Phase 1, Quadrant d
Video Output 3, Quadrant d
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant d
HCCD Output 2 Selector, Quadrant d
Floating Gate Exit HCCD Gate, Quadrant d
Video Output 1, Quadrant d
H2SW2d
H2Xd
VOUT1d
VDD2c
H2SW3c
RG23c
VDD3c
Amplifier 2 Supply, Quadrant c
HCCD Output 3 Selector, Quadrant c
Amplifier 2 and 3 Reset, Quadrant c
Amplifier 3 Supply, Quadrant c
N4
N5
N6
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KAE−01093
Table 3. PIN DESCRIPTION (continued)
Pin No.
N7
Label
H1BEMc
H2SEMc
H2c
Description
EMCCD Barrier Phase 1, Quadrant c
EMCCD Storage Multiplier Phase 2, Quadrant c
HCCD Phase 2, Quadrant c
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
H1Sc
HCCD Storage Phase 1, Quadrant c
HCCD Barrier Phase 2, Quadrant c
HCCD Barrier Phase 3, Quadrant c
HCCD Barrier Phase 3, Quadrant d
HCCD Barrier Phase 2, Quadrant d
HCCD Storage Phase 1, Quadrant d
HCCD Phase 2, Quadrant d
H2Bc
H3Bc
H3Bd
H2Bd
H1Sd
H2d
H2SEMd
H1BEMd
VDD3d
RG23d
H2SW3d
VDD2d
EMCCD Storage Multiplier Phase 2, Quadrant d
EMCCD Barrier Phase 1, Quadrant d
Amplifier 3 Supply, Quadrant d
Amplifier 2 and 3 Reset, Quadrant d
HCCD Output 3 Selector, Quadrant d
Amplifier 2 Supply, Quadrant d
N22
NOTE: Pin No. I3 is connected to the heat sink.
Imaging Performance
Table 4. TYPICAL OPERATION CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions)
Description
Light Source (Note 1)
Operation
Condition
Continuous Red, Green, Blue, and IR LED Illumination
Nominal Operating Voltages and Timing
0°C
Temperature
1. For monochrome sensor, only green and IR LED illumination is used.
Table 5. PERFORMANCE PARAMETERS
(Performance parameters are evaluated at initial design validation.) (Note 5)
Description
Symbol
Nom
Unit
Maximum Photoresponse Non-linearity
(EMCCD gain = 1) (Note 1)
NL
2
%
Maximum Gain Difference Between Outputs (EMCCD gain = 1) (Note 4)
Maximum Signal Error due to Non-linearity Differences (EMCCD gain = 1) (Note 1)
Photodiode Dark Current (Average)
Vertical CCD Dark Current
DG
10
1
%
DNL
%
I
0.1
8
e/p/s
e/p/s
PD
−
Image Lag
Lag
<1
500
−115
21
e
Anti-blooming Factor
X
AB
Vertical Smear (Blue Light)
Smear
dB
−
Read Noise (VOUT2) (Note 2)
n
e−T
n
e−T
n
e−T
e rms
−
Read Noise (EMCCD Gain = 1, VOUT3) (Note 2)
Read Noise (EMCCD Gain = 20)
11
e rms
−
<1
1.4
e rms
EMCCD Excess Noise Factor (Gain = 20x)
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KAE−01093
Table 5. PERFORMANCE PARAMETERS (continued)
(Performance parameters are evaluated at initial design validation.) (Note 5)
Description
Symbol
Nom
69
Unit
dB
Dynamic Range (Gain = 1) (Notes 2, 3)
DR
−
−
Dynamic Range (60 ke /1 e Noise)
Output Amplifier Bandwidth (Note 6)
Output Amplifier Impedance
95
dB
f_3db
250
140
44
MHz
W
R
OUT
−
Output Amplifier Sensitivity (VOUT3)
Output Amplifier Sensitivity (VOUT2)
Output Amplifier Sensitivity (VOUT1)
DV/DN
DV/DN
mV/e
mV/e
mV/e
−
−
16.5
5.8
DV/DN
(FG)
Quantum Efficiency (Monochrome, Peak)
Green (500 nm)
QE
QE
%
%
W
max
54
16
8
NIR (850 nm)
NIR (920nm)
Quantum Efficiency (Color, Peak)
Red (620 nm)
Green (540 nm)
Blue (470nm)
max
44
48
43
Power (Note 2)
4-output Mode
Gain = 1x
0.9
1.2
Gain = 100x
2-output Mode
Gain = 1x
0.5
0.65
Gain = 100x
1. Value is over the range of 10% to 90% of photodiode saturation.
2. At 40 MHz.
3. Uses 20 LOG (P /n
)
Ne e−T
4. The output-to-output gain differences may be adjusted by independently adjusting the EMCCD amplitude for each output.
5. Nominal performance as measured at 0°C
6. Calculated from f
= 1 / 2p × R
× C
where C
= 5 pF.
LOAD
−3db
OUT
LOAD
Table 6. PERFORMANCE SPECIFICATION
Temperature
Tested at (5C)
Description
Symbol
Min
Nom
−
Max
2.0
Unit
mV pp
% rms
%pp
Dark Field Global Non-uniformity
Bright Field Global Non-uniformity (Note 1)
DSNU
−
−
−
0
0
0
2.0
5.0
5.0
Bright Field Global Peak to Peak
Non-uniformity (Note 1)
PRNU
15.0
Bright Field Center Non-uniformity (Note 1)
Photodiode Charge Capacity (Note 2)
Horizontal CCD Charge Transfer Efficiency
Vertical CCD Charge Transfer Efficiency
Output Amplifier DC Offset (VOUT2, VOUT3)
Output Amplifier DC Offset (VOUT1)
1. Per color.
−
1.0
60
2.0
% rms
0
0
0
0
0
0
−
P
ke
Ne
HCTE
VCTE
0.999995
0.999995
8
0.999999
0.999999
10
−
−
V
ODC
V
ODC
12
2.5
V
V
−0.5
1
2. The operating value of the substrate reference voltage, V , can be read from V
.
AB
SUBREF
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KAE−01093
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome and Color with Microlens and MAR Glass
Figure 6. Monochrome Quantum Efficiency
Figure 7. Color Quantum Efficiency
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KAE−01093
Angled Response
Monochrome and Color with Microlens and MAR Glass
Horizontal − the incident light angle is varied in a plane parallel to the HCCD.
Vertical − the incident light angle is varied in a plane perpendicular to the HCCD.
Figure 8. Angled Response for Monochrome Device
Figure 9. Angled Response for Color Sensor
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KAE−01093
Figure 10. Frame Rates vs. Clock Frequency
DEFECT DEFINITIONS
Table 7. DEFECT DEFINITIONS
Description
Definition
Maximum Number Allowed
Defect ≥ 30 mV deviation from the mean, for all pixels
in the active image area
20
Major Dark Field Defective Bright Pixel
≥ 12%
Major Bright Field Defective Dark Pixel
Minor Dark Field Defective Bright Pixel
Defect ≥ 15 mV deviation from the mean, for all pixels
200
8
in the active image area
Cluster Defect
Column Defect
A group of 2 to 10 contiguous major defective pixels,
with no more than 2 adjacent defects horizontally
A group of more than 10 contiguous major dark defective
pixels along a single column or 10 contiguous bright
defective pixels along a single column
0
1. For the color device, a bright field defective pixel deviates by 12% with respect to pixels of the same color.
2. Column and cluster defects are separated by no less than 2 good pixels in any direction (excluding single pixel defects).
3. Low exposure dark column defects are not counted at temperatures above 0_C.
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KAE−01093
Absolute Maximum Ratings
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the
description. If the level or the condition is exceeded, the
device will be degraded and may be damaged. Operation at
these values will reduce MTTF.
formed is non-hermetic, and may allow moisture ingress
over time, depending on the storage environment. As
a result, care must be taken to avoid cooling the device
below the dew point inside the package cavity, since this
may result in condensation on the sensor. For all
KAE−01093 configurations, no warranty, expressed or
implied, covers condensation.
The KAE−01093 image sensors are provided with
configurations with epoxy sealed cover glass. The seal
Table 8. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
−50
Maximum
+60
Unit
_C
_C
Operating Temperature Range (Note 1)
T
OP
Parameter Specification Temperature
Range (Note 2)
T
PSR
−2
+2
Output Bias Current, Total for Each
Output (Note 3)
I
−
−15
mA
OUT
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Device degradation is not evaluated outside of these temperature ranges.
2. The device will operate effectively within a specified temperature range. The device is tested at nominally 0_C. Performance may not be
guaranteed per the PERFORMANCE SPECIFICATION table for temperatures that are different than those specified within. Noise
performance may degrade beyond the specification at die temperatures higher than specified here. Additionally, charge transfer may
degrade beyond the specification at temperatures lower than specified here.
3. Avoid shorting output pins to ground or any low impedance source during operation. Irreparable damage will occur and is not covered by
warranty. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 9. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description
VDD2(a,b,c,d), VDD3(a,b,c,d)
Minimum
Maximum
Unit
−0.4
17.5
V
VDD1(a,b,c,d), VOUT1(a,b,c,d)
V1B, V1T
−0.4
ESD – 0.4
ESD – 0.4
–0.4
7.0
V
V
V
V
ESD + 22.0
ESD + 14.0
+10
V2B, V2T, V3B, V3T, V4B, V4T
H1(a,b,c,d), H2(a,b,c,d)
H1S(a,b,c,d), H2S(a,b,c,d)
H1B(a,b,c,d), H2B(a,b,c,d)
H1BEM(a,b,c,d), H2BEM(a,b,c,d)
H2SW2(a,b,c,d), H2SW3(a,b,c,d)
H2L(a,b,c,d)
H2X(a,b,c,d)
H3S(a,b,c,d), H3B(a,b,c,d)
RG1(a,b,c,d), RG23(a,b,c,d)
H1SEM(a,b,c,d), H2SEM(a,b,c,d)
−0.4
+20
V
ESD
−9.0
0.0
25
V
V
SUB (Notes 1 and 2)
5.0
1. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
2. The measured value for VSUBREF is a diode drop (0.5 V) higher than the recommended minimum VSUB bias.
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14
KAE−01093
GUIDELINES FOR OPERATION
Power Up and Power Down Sequence
GND at all times. The SUBREF pin will not become valid
until VDD15 has been powered. The SUB pin should be at
least 4 V before powering up VDD2(a,b,c,d) and
VDD3(a,b,c,d).
SUB and ESD power up first, then power up all other
biases in any order. No pin may have a voltage less than ESD
at any time. All HCCD pins must be greater than or equal to
Table 10. DC BIAS OPERATING CONDITIONS
Maximum DC
Description
Pins
Symbol
Min
Nom
Max
Unit
Current
Output Amplifier Return
VSS1(a,b,c,d)
VSS1
(ISS1)
−8.3
−8.0
−7.7
V
4 mA
(Per Output)
Output Amplifier Supply
Output Amplifier Supply
VDD1(a,b,c,d)
VDD2(a,b,c,d)
VDD1
4.5
5.0
6.0
V
V
3 mA + IOUT
(Per Output)
(IDD1)
VDD2
(IDD2)
+14.7
+15.0
+15.3
2 mA + IOUT
(Per Output)
Output Amplifier Supply
Supply Voltage (Note 1)
Ground
VDD3(a,b,c,d)
VDD3
+14.7
+14.7
+15.0
+15.0
+15.3
+15.3
V
V
2 mA + IOUT
(Per Output)
(IDD3)
VDD15
VDD3(a,b,c,d)
VDD15
(IDD15)
9 mA
(Full Sensor)
GND
SUB
GND
0.0
5.0
0.0
0.0
9.0
V
V
Substrate
(Notes 2 and 3)
VSUB
VAB
Up to 1 mA
(Determined by
Photocurrent)
ESD Protection Disable
Output Bias Current
ESD
ESD (IESD)
IOUT
−8.3
−8.0
−7.7
V
2 mA
(Full Sensor)
Per Output
VOUT1(a,b,c,d),
VOUT2(a,b,c,d),
VOUT3(a,b,c,d)
4.5
5.0
7.0
mA
1. VDD15 bias pins must be maintained at 15 V during operation.
2. The value of VAB (nominal VSUB) printed on the label for each sensor corresponds to the voltage output on the VSUBREF pin minus 0.5 V.
VSUBREF is programmed to be one diode drop, 0.5 V, above the nominal VAB voltage at 0°C during production testing (for other
temperatures, there is a temperature dependence of approximately 0.01 V/degree). Therefore the proper VSUB value can be determined
from the sensor itself by measuring VSUBREF when VDD2(a,b,c,d) and VDD3(a,b,c,d) are at their specified voltages and then subtracting
0.5 V. It is noted that VSUBREF is unique to each image sensor and may vary from 5.5 to 9.5 V. In addition, the output impedance of
VSUBREF is approximately 25 kW.
3. Caution: The EMCCD register must NOT be clocked while the electronic shutter pulse is high.
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15
KAE−01093
AC Operating Conditions
Clock Levels
Table 11. CLOCK LEVELS
HCCD and RG
Low Level
Nom
Amplitude
Nom
Min
−0.2
−0.2
−0.2
−0.2
Max
+0.2
+0.2
+0.2
+0.2
Min
3.1
3.1
3.1
3.1
Max
3.6
3.6
3.6
3.6
Function
Pin
H3B(a,b,c,d)
H2B(a,b,c,d)
H1B(a,b,c,d)
H3S(a,b,c,d)
Reversible HCCD Barrier 3
Reversible HCCD Barrier 2
Reversible HCCD Barrier 1
Reversible HCCD Storage 3
0.0
0.0
0.0
0.0
3.3
3.3
3.3
3.3
H2S(a,b,c,d)
H1S(a,b,c,d)
Reversible HCCD Storage 2
Reversible HCCD Storage 1
HCCD Switch 2 and 3
−0.2
−0.2
−0.2
0.0
0.0
0.0
+0.2
+0.2
+0.2
3.1
3.1
3.1
3.3
3.3
3.3
3.6
3.6
3.6
H2SW2(a,b,c,d),
H2SW3(a,b,c,d)
H2L(a,b,c,d)
H2X(a,b,c,d)
HCCD Last Gate
Floating Gate Exit
−0.2
−0.2
−3.0
0.0
0.0
+0.2
+0.2
−2.4
3.1
5.7
3.3
6.0
3.6
6.3
OG1(a,b,c,d)
RG1(a,b,c,d)
RG23(a,b,c,d)
Output Gate 1
−2.7
Cap
Cap
5.7
3.1
3.1
6.0
3.3
3.3
6.3
3.6
3.6
Floating Gate Reset
Floating Diffusion Reset
H1BEM(a,b,c,d)
H2BEM(a,b,c,d)
H1SEM(a,b,c,d)
H2SEM(a,b,c,d)
Multiplier Barrier 1
Multiplier Barrier 2
Multiplier Storage 1
Multiplier Storage 2
−0.2
−0.2
−0.3
−0.3
0.0
0.0
0.0
0.0
+0.2
+0.2
+0.3
+0.3
4.6
4.6
8.0
8.0
5.0
5.0
−
5.4
5.4
18.0
18.0
−
1. HCCD Operating Voltages. There can be no overshoot on any horizontal clock below −0.4 V: the specified absolute minimum. The H1SEM
and H2SEM clock amplitudes need to be software programmable independently for each quadrant to adjust the charge multiplier gain.
2. Reset Clock Operation: The RG1, RG23 signals must be capacitive coupled into the image sensor with a 0.01 mF to 0.1 mF capacitor. The
reset clock overshoot can be no greater than 0.3 V, see Figure 13.
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KAE−01093
Clock Capacitances
Pin
H1SEMa
H2SEMa
H1BEMa
H2BEMa
H1a
H2a
H1Sa
H2Sa
H3Sa
pF
54
54
54
54
42
42
52
52
52
39
39
39
pF
54
54
54
54
42
42
52
52
52
39
39
39
Pin
H1SEMc
H2SEMc
H1BEMc
H2BEMc
H1c
H2c
H1Sc
H2Sc
H3Sc
pF
54
54
54
54
42
42
52
52
52
39
39
39
Pin
H1SEMd
H2SEMd
H1BEMd
H2BEMd
H1d
H2d
H1Sd
H2Sd
H3Sd
pF
54
54
54
54
42
42
52
52
52
39
39
39
Pin
V1B
nF
11
8
9
9
11
8
9
Pin
H1SEMb
H2SEMb
H1BEMb
H2BEMb
H1b
H2b
H1Sb
H2Sb
H3Sb
V2B
V3B
V4B
V1T
V2T
V3T
V4T
9
H1Ba
H2Ba
H3Ba
H1Bc
H2Bc
H3Bc
H1Bd
H2Bd
H3Bd
H1Bb
H2Bb
H3Bb
NOTE: The capacitances of H2X, RG1, RG23, H2SW, H2L, and OG1 are each 20 pF or less.
Figure 11. EMCCD Clock Adjustable Levels
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KAE−01093
For the EMCCD clocks, each quadrant must have
must be software controlled to balance the gain of the four
independently adjustable high levels. All quadrants have
a common low level of GND. The high level adjustments
outputs.
+3.3 V
0 to 75 W
RG1 Clock
Generator
RG1
0.01 to
0.1 μF
+3.3 V
0 to 75 W
RG23 Clock
Generator
RG23
0.01 to
0.1 μF
Figure 12. Reset Clock Drivers
The RG1, RG23 signals must be capacitive coupled into
the image sensor with a 0.01 mF to 0.1 mF capacitor. The
reset clock overshoot can be no greater than 0.3 V, see
Figure 13. The damping resistor values would vary between
0 and 75 W depending on the layout of the circuit board.
3.1 V Minimum
0.3 V Maximum
Figure 13. RG Clock Overshoot
Table 12. VCCD
Pin
Function
Min
−8.0
−0.2
10.5
Nom
−6.5
0.0
Max
−6.0
+0.2
12.0
V1T, V1B, V2T, V2B, V3T, V3B, V4T, V4B
V1T, V1B, V2T, V2B, V3T, V3B, V4T, V4B
V1T, V1B
Vertical CCD Clock, Low Level
Vertical CCD Clock, Mid Level
Vertical CCD Clock, High (3rd) Level
11.0
Table 13. ELECTRONIC SHUTTER PULSE (VES)
High Level
(Pulse)
Minimum
High Level
(Pulse)
Maximum
Low Level
(DC)
Pin
Function
18
SUB
Electronic Shutter
VAB
25
(VSUBREF − 0.5)
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KAE−01093
Device Identification
The device identification pin (DevID) may be used to
determine which ON Semiconductor interline EMCCD
sensor is being used.
Table 14. DEVICE IDENTIFICATION VALUES
Maximum DC
Current
Description
Pin
Symbol
Min
Nom
Max
Unit
Device Identification
(Notes 1, 2 and 3)
ID
DevID
700
920
1100
0.3 mA
W
1. Nominal value subject to verification and/or change during release of preliminary specifications.
2. If the Device Identification is not used, it may be left disconnected.
3. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent
localized heating of the sensor due to current flow through the R_DeviceID resistor.
Recommended Circuit
Figure 14. Device Identification Recommended Circuit
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KAE−01093
THEORY OF OPERATION
Image Acquisition
minimum VES voltage (VES ) of 18 V for a time of at
min
least 2 ms. When the SUB pin is at VES , the photodiode
min
can hold no electrons, and the electrons flow downward into
the substrate. When the SUB pin is returned to its DC level
(VAB), the integration of electrons in the photodiode begins.
The HCCD and EMCCD clocks should be stopped when the
electronic shutter is pulsed, to avoid having the large voltage
pulse on SUB coupling into the video outputs and altering
the EMCCD gain.
It should be noted that there are certain conditions under
which the device will have no anti-blooming protection:
when the V1T and V1B pins are high, very intense
illumination generating electrons in the photodiode will
flood directly into the VCCD.
The VCCD is shielded from light by metal to prevent
detection of more photons. For very bright spots of light,
some photons may leak through or around the metal light
shield and result in electrons being transferred into the
VCCD. This is called image smear.
Image Readout
At the start of image readout, the voltage on the V1T and
V1B pins is pulsed from 0 V up to the high level for at least
10 ms and back to 0 V, which transfers the electrons from the
photodiodes into the VCCD. If the VCCD is not empty, then
the electrons will be added to what is already in the VCCD.
The VCCD is read out one row at a time. During a VCCD
row transfer, the HCCD clocks are stopped. All gates of type
H1 stop at the high level and all gates of type H2 stop at the
low level. After a VCCD row transfer, charge packets of
electrons are advanced one pixel at a time towards the output
amplifiers by each complimentary clock cycle of the H1,
H2, and H3 gates.
Figure 15. An Illustration of Two Columns and
Three Rows of Pixels
This image sensor is capable of detecting up to 60,000
electrons with a small signal noise floor of less than
1 electron all within one image. Each 9.0 mm square pixel,
as shown in Figure 15 above, consists of a light sensitive
photodiode and a portion of the vertical CCD (VCCD). Not
shown is a microlens positioned above each photodiode to
focus light away from the VCCD and into the photodiode.
Each photon incident upon a pixel will generate an electron
in the photodiode with a probability equal to the quantum
efficiency.
To prevent overfilling the charge multiplier,
a non-destructive floating gate output amplifier (VOUT1) is
provided on each quadrant of the image sensor as shown in
Figure 16 below.
The photodiode may be cleared of electrons (electronic
shutter) by pulsing the SUB pin of the image sensor up to the
To VOUT2
VOUT1
FG
4 Clock Cycle
1 Clock Cycle
1 Clock
Cycle
28 Clock Cycles
Empty Pixels
12 Clock Cycles
12 Clock Cycles
From the Dark
VCCD Columns
From the Photo−active
SW
Empty Pixels
VCCD Columns
Charge Transfer
1208 Clock Cycles
To the Charge
Multiplier and
VOUT3
Figure 16. The Charge Transfer Path of One Quadrant
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KAE−01093
Setting the Charge Threshold
After one row has been transferred from the VCCD into
the HCCD, the HCCD clock cycles should begin. After 12
HCCD clock cycles the first dark VCCD column pixel will
arrive at (VOUT1). After another 12 (24 total) HCCD clock
cycles the first photo-active pixel charge packet will arrive
(see Figure 16).
Before reaching the output amplifiers, each pixel charge
packet passes through VOUT1. The floating gate output
amplifier is able to sense how much charge is present in
a pixel charge packet without altering the number of
electrons in that charge packet. An output load sink must be
applied to each VOUT1 pin to activate each floating gate
output amplifier. The voltage at the output of the floating
gate output amplifier is measured using the traditional
correlated double sampling technique and digitized to allow
for analysis by the camera.
The floating gate output amplifier functions as a charge
threshold detector. For each pixel, the camera evaluates the
number of electrons contained in the pixel, compares the
measured number of electrons to the camera’s Charge
Threshold (see Setting the Charge Threshold) and routes the
pixel charge packet to either the normal floating diffusion
output amplifier (VOUT2) or to the EMCCD output
amplifier (VOUT3) by controlling the timing of the H2SW2
and H2SW3 signals.
The pixel packet routing action takes place 28 HCCD
clock cycles after the pixel charge packet passes through the
floating gate amplifier (VOUT1). The 28 HCCD clock cycle
delay is to allow for pipeline delays of the A/D converter
inside the Analog Front End (AFE). The camera’s timing
generator must dynamically alter the timing of the H2SW2
and H2SW3 signals on a pixel by pixel basis based on the
results of the pixel packet measurement performed on the
VOUT1 signal (see Figure 17 FPGA Pipeline).
The charge multiplier has a maximum charge handling
capacity (above 20x gain) of 30,000 electrons. Therefore,
the average signal level should be 20,000 electrons or less to
accommodate a normal distribution of signal levels (see
Figure 18). At the maximum gain of 130x no more than
150 electrons should be allowed into the EMCCD.
The criteria that determines which output the pixel charge
packet will be routed to is the Charge Threshold. For most
applications, it is recommended that the Charge Threshold
be set to 150 electrons. Pixels with charge packets measured
to be greater than 150 electrons should be routed to the
normal floating diffusion output amplifier VOUT2. Pixels
with charge packets measured to be less than 150 electrons
should be routed to the EMCCD and VOUT3.
Considerations when setting the camera’s Charge
Threshold:
1. EMCCD large signal performance. Sending signals
larger than 150 electrons into the EMCCD will
produce images with lower signal to noise ratio than
if they were read out of the normal floating diffusion
output amplifier.
2. EMCCD capacity. The EMCCD charge multiplier
has a maximum charge handling capacity of
30,000 electrons. Overfilling the charge multiplier
beyond 30,000 electrons will shorten its useful
operating lifetime and risks inducing a latchup
condition within the imager. To recover from an
EMCCD latchup condition the HSEM clock
voltages have to be lowered to +8.0 volts and
clocked with this lower voltage for a time period that
will allow the EMCCD to be emptied of charge.
The non-destructive floating gate output amplifier is
able to sense how much charge is present in a charge
packet without altering the number of electrons in
that charge packet. This type of amplifier has a low
To route a charge packet to the EMCCD charge multiplier
(VOUT3) H2SW2 is held at GND and H2SW3 is clocked
with the same timing as H2 for that one clock cycle.
To route a charge packet to the normal output (VOUT2)
H2SW3 is held at GND and H2SW2 is clocked with the
same timing as H2 for that one clock cycle.
For optimum performance, alignment of the critical
timing signals is very important (see CCD clock signal
optimization).
charge-to-voltage
conversion
gain
(about
−
5.8 mV/e ) and high noise (about 65 electrons), but
it is being used only as a threshold detector, and not
an imaging detector. Even with 65 electrons of noise,
it is adequate to determine whether a charge packet
is greater than or less than the recommended
threshold of 150 electrons.
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KAE−01093
Figure 17. KAE−01093 FPGA Pipeline
Figure 18. EMCCD Charge Multiplier (VOUT3) Histogram at the Maximum Gain of 130x and Charge Threshold
Set to 150 Electrons
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KAE−01093
FG
H2
H1
H2X
OG1
H2L
H1S
H2S
H3S
Figure 19. The Structure of the HCCD and Floating Gate Amplifier. The Direction of Charge is from Right to Left
Figure 20. The Timing of the Clock Inputs Associated with the Floating Gate Amplifier, VOUT1
CCD Clock Signal Optimization
The RG1 input signal is pulsed during the rising edge of
the H2L signal to reset the floating gate to a known starting
voltage. The OG1 signal is clocked opposite of the H2X and
H2L signals. The OG1 clocking counteracts any capacitive
coupling effects that clocking the H2X and H2L signals
would otherwise have on the floating gate. For maximum
charge handling capability, the rising edge of the H2X signal
should lead the rising edge of the H2L signal and the falling
edge of the OG1 signal.
Aligning the rising edge of H2X with the rising edge of
H2L limits the maximum signal level to less than 60 ke .
−
The falling edges of the H2X and H2L signals should be
coincident with the rising edge of the OG1 signal.
The RG1, RG2, H2X, H2L, and OG1 signals are all
continuously running clocks. These signals should not be
stopped during a VCCD line transfer.
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KAE−01093
EMCCD OPERATION
NOTE: Charge flows from right to left.
Figure 21. The Charge Multiplication Process
The charge multiplication process, shown in Figure 21
above, begins at time step A, when an electron is held under
the H1SEM gate. The H2BEM and H1BEM gates block the
electron from transferring to the next phase until the H2SEM
has reached its maximum voltage. When the H2BEM is
clocked from 0 to +5 V, the channel potential under H2BEM
increases until the electron can transfer from H1SEM to
H2SEM. When the H2SEM gate is above 10 V, the electric
field between the H2BEM and H2SEM gates gives the
electron enough energy to free a second electron which is
collected under H2SEM. Then the voltages on H2BEM and
H2SEM are both returned to 0 V at the same time that
H1SEM is ramped up to its maximum voltage. Now the
process can repeat again with charge transferring into the
H1SEM gate.
The alignment of clock edges is shown in Figure 22. The
rising edge of the H1BEM and H2BEM gates must be
delayed until the H1SEM or H2SEM gates have reached
their maximum voltage. The falling edge of H1BEM and
H2BEM must reach 0 V before the H1SEM or H2SEM reach
0 V. There are a total of 1,800 charge multiplying transfers
through the EMCCD on each quadrant.
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KAE−01093
Figure 22. The Timing Diagram for Charge Multiplication
The amount of gain through the EMCCD will depend on
temperature and H1SEM and H2SEM voltage as shown in
Figure23. Gain also depends on substrate voltage, as
shown in Figure 24, and on the input signal, as shown in
Figure 25.
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 23. The Variation of Gain vs. EMCCD High Voltage and Temperature
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KAE−01093
NOTE: EMCCD gain is not constant with substrate voltage.
Figure 24. The Requirement EMCCD Voltage for Gain of 20x vs. Substrate Voltage
NOTE: The EMCCD voltage was set to provide 20x gain with an input of 150 electrons.
Figure 25. EMCCD Gain vs. Input Signal
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KAE−01093
If more than one output is used, then the EMCCD high
unpredictably from one image sensor to the next, as in
Figure 26. Because of this, the gain vs. voltage relationship
must be calibrated for each image sensor, although within
each quadrant, the H1SEM and H2SEM high level voltage
should be equal.
level voltage must be independently adjusted for each
quadrant. This is because each quadrant will require a
slightly different voltage to obtain the same gain. In
addition, the voltage required for a given gain differs
Figure 26. An Example Showing How Two Image Sensors Can have Different Gain vs. Voltage Curves
The effective output noise of the image sensor is defined
as the noise of the output signal divided by the gain. This is
measured with zero input signal to the EMCCD. Figure 27
shows the EMCCD by itself has a very low noise that goes
as the noise at gain = 1 divided by the gain. The EMCCD has
very little clock-induced charge and does not require
elaborate sinusoidal waveform clock drivers. Simple square
wave clock drivers with a resistor between the driver and
sensor for a small RC time constant are all that is needed. The
minimum possible noise is limited by a combination of
vertical CCD spurious charge, EMCCD spurious charge,
and output amplifier glow.
NOTE: The data represented by this chart includes noise from dark current and spurious charge generation.
Figure 27. EMCCD Output Noise vs. EMCCD Gain in Quad Output Mode from −405C to +405C
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KAE−01093
Operating Temperature
Because of these pixel array noise sources, it is
recommended that the maximum gain used be 130x, which
typically gives a noise floor between 0.3e and 0.6e at 0°C.
Using higher gains will provide limited benefit and will
degrade the signal to noise ratio due to the EMCCD excess
noise factor. Furthermore, the image sensor noise is not
limited by dark current noise sources when the temperature
is below −20°C. Therefore, cooling below −20°C will not
provide a significant improvement to the noise floor, with
the negative consequence that lower temperatures increase
the probability of poor charge transfer.
The reasons for lowering the operating temperature are to
reduce dark current noise and to reduce image defects. The
average dark signal from the VCCD and photodiodes must
−
be less than 1 e in order to have a total system noise less than
−
1 e when using the EMCCD. The recommended operating
temperature is 0°C. This represents the best compromise of
low noise performance vs. complexity of cooling the image
sensor. Operation below −20°C is not recommended, and
temperatures below −20°C may result in poor charge
transfer in the HCCD. Operation above +20°C may result in
excessive dark current noise.
CAUTION: The EMCCD should not be operated near
saturation for an extended period, as this may
result in gain aging and permanently reduce
the gain. It should be noted that device
degradation associated with gain aging is not
covered under the device warranty.
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KAE−01093
TIMING DIAGRAMS
Pixel Timing
NOTE: The minimum time for one pixel is 25 ns.
Figure 28. Pixel Timing Pattern P1
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KAE−01093
2x Horizontal Charge Binning
Figure 29. 2x Horizontal Charge Binning Timing Pattern
Black, Clamp, VOUT1, VOUT2, and VOUT3
Alignment at Line Start
The black level clamping operation of the analog front end
(AFE) should take place within the first 28 clock cycles of
every row. This applies to all modes of operation.
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KAE−01093
VCCD Timing
Vertical Transfer Times and Pulse Widths
Table 15. TIMING DEFINITIONS
Symbol
Definition
VCCD Transfer Time A
Min
0.3
2.0
280
5.0
Nom
0.4
Max
2.0
Unit
ms
T
V
Electronic Shutter Pulse
4.0
10.0
320
10.0
T
SUB
ms
T
3D
Photodiode Transfer Delay Time
Photodiode to VCCD Transfer Time
300
8.0
ms
T
3
ms
Figure 30. Timing Pattern F1. VCCD Frame Timing to Transfer Charge from Photodiodes to the VCCD
Figure 31. Line Timing L2. VCCD Line Timing to Transfer One Line of Charge from the VCCD to the HCCD
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KAE−01093
Electronic Shutter
VES
VAB
VSUB
3.3 V
0 V
HCCD
VCCD
0 V
−8 V
TV
TV
TSUB
First VCCD
Clock Edge
Last HCCD
Clock Edge
Figure 32. Electronic Shutter Timing Pattern S1
CAUTION: Caution: The EMCCD register must not be clocked
while the electronic shutter pulse is high.
HCCD and EMCCD Clocks for Electronic Shutter
The HCCD and EMCCD clocks must be static during the
frame, line, and electronic shutter timing sequences.
Table 16. HCCD AND EMCCD CLOCKS FOR ELECTRONICS SHUTTER
Clocks
State
High
Low
H1S, H2S, H1, H1SEM, H1BEM
H3S, H2, H2SEM, H2BEM
Table 17. FRAME RATES
Dual (Top/Bottom)
Quad
Unit
52
fps
91
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32
KAE−01093
Image Exposure and Readout
Table 18. IMAGE READOUT TIMING
The flowchart for image exposure and readout is shown in
the figure below. The electronic shutter timing may be
omitted to obtain an exposure time equal to the image read
out time. NEXP is the number of lines exposure time and NV
is the number of VCCD clock cycles (row transfers).
Mode
Dual
NH
NV
532
1208
1208
Quad
1064
Figure 33. The Image Readout Timing Flow Chart
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33
KAE−01093
Long Integrations and Readout
For extended integrations the output amplifiers need to be
powered down. When powered up, the output amplifiers
emit near infrared light that is sensed by the photodiodes. It
will begin to be visible in images of 30 second integrations
or longer.
Figure 34. Timing Flow Chart for Long Integration Time
To power down the output amplifiers set VDD1 and VSS1
to 0 V, and VDD2(a,b,c,d) and VDD3(a,b,c,d) to +5 V.
VDD2 or VDD3 must not be set to 0 V during the integration
of an image. During the time the VDD2 and VDD3 supplies
are reduced to +5 V the VDD15 pin is to be kept at +15 V.
The substrate voltage reference output SUBV will be valid
as long as VDD15 is powered. The HCCD and EMCCD may
be continue to clock during integration. If they are stopped
during integration then the EMCCD should be re-started at
+7 V amplitude to flush out any undesired signal before
increasing the voltage to charge multiplying levels.
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34
KAE−01093
THERMOELECTRIC COOLER
EMCCD register of each or the four outputs was 20 mV, the
EMCCD gain was 20x, and the horizontal clock rate was
40 MHz. The recommended maximum input current (Imax)
is 2.0 A, requiring an input voltage (Vmax) of 11.1 V, but the
optimum current and voltage needed for a given temperature
gradient may be lower.
Representative performance plots for the TEC are shown
in the following graphs.
Performance Plots of PGA Integrated TEC
For the performance plots below, the TEC was operated
at maximum pulse width (DC mode) to maintain the cold
DT and Voltage vs. Current
70
60
50
40
30
20
10
0
12.0
10.0
8.0
6.0
4.0
2.0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Operating Current [A]
Figure 35. PGA with Integrated TEC, Temperature Gradient and Required Voltage vs. Applied Current
Performance Plot of Thermistor in PGA
with Integrated TEC
The thermoelectric cooler (TEC) has an on-board
thermistor with 3% tolerance, and 10 kW (Ro) at 25_C
(298_K, To). Its performance follows the equation shown
below, where T = temperature in _K, over the range of 233
to 398_K, R = thermistor resistance in ohms. A plot of
T
resistance vs. temperature is shown in Equation 1.
1
(eq. 1)
T + NJ(
Nj
ǒ
)
Ǔ3
)
(
)
(
7.96E * 4 ) 2.67E * 4 @ ln(RT) ) 1.21E * 7 @ ln(RT)
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35
KAE−01093
360
340
320
300
280
260
240
220
200
1 000
10 000
100 000
1 000 000
Resistance [W]
Figure 36. Thermistor Resistance vs. Temperature
60.0
50.0
40.0
30.0
20.0
y = −16.816x + 55.473
10.0
0.0
0.00
0.50
1.00
1.50
2.00
2.50
Cooling System Thermal Resistance [K/W]
(Cooling Source at 275C)
Figure 37. Maximum DT vs. Cooling System Thermal Resistance
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36
KAE−01093
STORAGE AND HANDLING DETAILS
For information on Storage, ESD prevention, cover glass
care and cleanliness, please download the Image Sensor
Handling and Best Practices Application Note
(AN52561/D) from www.onsemi.com. Please note that
CCD products are not shipped or stored in Moisture Barrier
Bags (MBB) and Moisture Sensitivity Level (MSL) ratings
are not specified.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
www.onsemi.com
37
KAE−01093
PACKAGE DIMENSIONS
CPGA148, 33x30
CASE 107FK
ISSUE O
XXXXX
NNNN
N
M
L
K
J
I
H
G
F
E
D
C
B
A
24 23 22 21 2019 18 17 1615 14 13121110
9 8 7 6 5 4 3 2 1
XXXX = Specific Device Code
NNNN= Serial Number
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38
KAE−01093
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