FXMAR2104UMX [ONSEMI]
双电源、4位电源转换器/隔离器,用于漏极开路和推挽式应用;![FXMAR2104UMX](http://pdffile.icpdf.com/pdf2/p00369/img/icpdf/FXMAR2104UMX_2253642_icpdf.jpg)
型号: | FXMAR2104UMX |
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描述: | 双电源、4位电源转换器/隔离器,用于漏极开路和推挽式应用 PC 接口集成电路 转换器 |
文件: | 总17页 (文件大小:1568K) |
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July 2012
FXMAR2104
Dual-Supply, 4-Bit Voltage Translator / Isolator for
Open-Drain and Push-Pull Applications
Features
Description
The FXMAR2104 is
a
4-bit high-performance,
.
Bi-Directional Interface between Any Two Levels:
1.65V to 5.5V
configurable dual-voltage supply, open-drain translator
for bi-directional voltage translation over a wide range of
input and output voltages levels. The FXMAR2104 also
works in a push-pull environment.
.
.
.
Direction Control Not Needed
Internal 10KΩ Pull-Up Resistors
Intended for use as a voltage translator in applications
using the I2C-Bus® interface, the input and output
voltage levels are compatible with I2C device
specification voltage levels. Eight internal 10KΩ pull-up
resistors are integrated.
System GPIO Resources Not Required when OE
Tied to VCCA
I2C-Bus® Isolation
.
.
A/B Port VOL = 175mV (Typical), VIL = 150mV,
I
OL = 6mA
The device is designed so that the A port tracks the
VCCA level and the B port tracks the VCCB level. This
allows for bi-directional A/B port voltage translation
between any two levels from 1.65V to 5.5V. VCCA can
equal VCCB from 1.65V to 5.5V.
.
.
.
Open-Drain Inputs / Outputs
Works in a Push-Pull Environment
Accommodates Standard-Mode and Fast-Mode
I2C-Bus Devices
Supports I2C Clock Stretching & Multi-Master
Non-preferential power-up means VCC can be powered-
up first. Internal power-down control circuits place the
device in 3-state if either VCC is removed.
.
.
.
Fully Configurable: Inputs and Outputs Track VCC
The two ports of the device have automatic direction-
sense capability. Either port may sense an input signal
and transfer it as an output signal to the other port.
Non-Preferential Power-Up; Either VCC May Be
Powered-Up First
.
.
.
Outputs Switch to 3-State if Either VCC is at GND
Tolerant Output Enable: 5V
Packaged in 12-Lead Ultrathin MLP
(1.8mm x 1.8mm)
.
ESD Protection Exceeds:
- 5kV HBM (per JESD22-A114)
- 2kV CDM (per JESD22-C101)
Ordering Information
Operating
Temperature Range
Top
Mark
Packing
Part Number
Package
Method
5000 Units on
12-Lead, Ultrathin MLP, 1.8mm x 1.8mm
Tape and Reel
FXMAR2104UMX
-40 to +85°C
BY
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
Block Diagram
OE
VCCB
Dynamic
Driver(with
Time Out)
10K
Internal Direction
Generator &
Control
VbiasB
Vbias
A
B
A
VCCA
10K
Internal Direction
Generator &
Control
Dynamic Driver
(with Time Out)
Figure 1. Block Diagram, 1 of 4 Channels
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
2
Pin Configuration
Figure 2. UMLP (Top-Through View)
Pin Definitions
Pin #
Name
Description
1
VCCB
VCCA
B-Side Power Supply
A-Side Power Supply
2
3, 4, 5, 6
A0, A1, A2, A3
GND
A-Side Inputs or 3-State Outputs
Ground
7
8
OE
Output Enable Input
9, 10, 11, 12
B3, B2, B1, B0
B-Side Inputs or 3-State Outputs
Truth Table
Control
Outputs
OE
LOW Logic Level
HIGH Logic Level
3-State
Normal Operation
Note:
1. If the OE pin is driven LOW, the FXMAR2104 is disabled and the A0, A1, A2, A3, B0, B1, B2 and B3 pins (including
dynamic drivers) are forced into 3-state. Also, if the OE pin is driven LOW, all eight 10KΩ internal pull-up
resistors are decoupled from their respective VCCs.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
Max.
7.0
Unit
VCCA, VCCB Supply Voltage
A Port
7.0
V
VIN
DC Input Voltage
Output Voltage(2)
B Port
7.0
Control Input (OE)
An Outputs 3-State
Bn Outputs 3-State
An Outputs Active
Bn Outputs Active
At VIN < 0V
7.0
7.0
7.0
VO
V
VCCA + 0.5V
VCCB + 0.5V
-50
IIK
DC Input Diode Current
DC Output Diode Current
mA
mA
At VO < 0V
-50
IOK
At VO > VCC
+50
IOH / IOL
ICC
DC Output Source/Sink Current
-50
-65
+50
mA
mA
mW
°C
DC VCC or Ground Current per Supply Pin
±100
0.129
+150
PD
Power Dissipation
At 400KHz
TSTG
Storage Temperature Range
Human Body Model, B-Port
8
(vs. GND & vs. VCCB
)
Electrostatic Discharge
Capability
ESD
Human Body Model, All Pins,
JESD22-A114
kV
5
2
Charged Device Mode, JESD22-C101
Note:
2. IO absolute maximum rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
1.65
0
Max.
5.50
5.5
Units
VCCA, VCCB Power Supply Operating
V
A Port
VIN
Input Voltage
B Port
0
5.5
V
Control Input (OE)
0
VCCA
Thermal Resistance
301.5
+85
C°/W
°C
ΘJA
TA
Free Air Operating Temperature
-40
Note:
3. All unused I/O pins should be disconnected.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
4
Functional Description
Power-Up/Power-Down Sequencing
FXM translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0V, outputs are in a
high-impedance state. The control input (OE) is
designed to track the VCCA supply. A pull-down resistor
tying OE to GND should be used to ensure that bus
contention, excessive currents, or oscillations do not
occur during power-up/power-down. The size of the pull-
down resistor is based upon the current-sinking
capability of the device driving the OE pin.
The recommended power-up sequence is:
1. Apply power to the first VCC
2. Apply power to the second VCC
.
.
3. Drive the OE input HIGH to enable the device.
The recommended power-down sequence is:
1. Drive OE input LOW to disable the device.
2. Remove power from either VCC
.
3. Remove power from other VCC
.
Note:
4. Alternatively, the OE pin can be hardwired to VCCA
to save GPIO pins. If OE is hardwired to VCCA
either VCC can be powered up or down first.
,
Application Circuit
Figure 3. Application Circuit
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
5
Application Information
The FXMAR2104 has four bi-directional, open-drain
I/Os and includes a total of eight internal 10K pull-up
resistors (RPUs) on each port of all four data I/O pins. If
a pair of data I/O pins (An/Bn) is not used, these pins
should be left unconnected, eliminating unwanted
current flow through the internal RPUs. External RPUs
can be added to the I/Os to reduce the total RPU value,
depending on the total bus capacitance. The user is free
to lower the total pull-up resistor value to meet the
maximum I2C edge rate per the I2C specification
(UM10204 rev. 03, June 19, 2007). For example,
according to the I2C specification, the maximum edge
rate (30% - 70%) during Fast Mode (400kbit/s) is 300ns.
If the bus capacitance is approaching the maximum
400pF, a lower total RPU value helps keep the rise time
below 300ns (Fast Mode). Likewise, the I2C
specification also specifies a minimum SCL high time of
600ns during Fast Mode (400KHz). Lowering the total
RPU also helps increase the SCL high time. If the bus
C = the bus capacitance. If the FXMAR2104 is attached
to the master [on the A port] and there is a slave on the
B port, the Npassgates act as a low resistive short
between the ports until either of the port’s VCC/2
thresholds are reached. After the RC time constant has
reached the VCC/2 threshold of either port, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the LOW-to-HIGH (LH)
direction, accelerating the rising edge. The resulting rise
time resembles the scope shot in Figure 4. Effectively,
two distinct slew rates appear in rise time. The first slew
rate (slower) is the RC time constant of the bus. The
second slew rate (much faster) is the dynamic driver
accelerating the edge.
If both the A and B ports of the translator are HIGH, a
high-impedance path exists between the A and B ports
because both the Npassgates are turned off. If a master
or slave device decides to pull SCL or SDA LOW, that
device’s driver pulls down (Isink) SCL or SDA until the
edge reaches the A or B port VCC/2 threshold. When
either the A or B port threshold is reached, the port’s
edge detector triggers both dynamic drivers to drive
their respective ports in the HIGH-to-LOW (HL)
direction, accelerating the falling edge.
capacitance
approaches
400pF,
consider
the
FXMA2102, which does not contain internal RPUs.
Then the user can calculate the ideal external RPU
value. Section 7.1 of the I2C specification provides an
excellent guideline for pull-up resistor sizing.
Theory of Operation
The FXMAR2104 is designed for high-performance level
shifting and buffer / repeating in an I2C application.
Figure 1 shows that each bi-directional channel contains
two series-Npassgates and two dynamic drivers. This
hybrid architecture is highly beneficial in an I2C
application where auto-direction is a necessity.
For example, during the following three I2C protocol
events:
.
.
Clock Stretching
Slave’s ACK Bit (9th bit = 0) following a Master’s
Write Bit (8th bit = 0)
.
Clock Synchronization and Multi Master
Arbitration
the bus direction needs to change from master-to-slave
to slave to master without the occurrence of an edge. If
there is an I2C translator between the master and slave
in these examples, the I2C translator must change
direction when both A and B ports are LOW. The
Npassgates can accomplish this task very efficiently
because, when both A and B ports are LOW, the
Npassgates act as a low resistive short between the two
(A and B) ports.
Figure 4. Waveform C: 600pF, Total RPU: 2.2KΩ
Due to I2C’s open-drain topology, I2C masters and
slaves are not push-pull drivers. Logic LOWs are “pulled
down” (Isink), while logic HIGHs are “let go” (3-state). For
example, when the master lets go of SCL (SCL always
comes from the master), the rise time of SCL is largely
determined by the RC time constant, where R = RPU and
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
6
the master greater than 495mV. To complicate matters,
the I2C specification states that 6mA of IOL is
recommended for bus capacitances approaching
400pF. More IOL increases the voltage drop across the
I2C translator. The I2C application benefits when I2C
VOL vs. IOL
The I2C specification mandates a maximum VIL (IOL of
3mA) of VCC • 0.3 and a maximum VOL of 0.4V. If there
is a master on the A port of an I2C translator with a VCC
of 1.65V and a slave on the I2C translator B port with a
VCC of 3.3V, the maximum VIL of the master is (1.65V x
0.3) 495mV. The slave could legally transmit a valid
logic LOW of 0.4V to the master.
translators exhibit low VOL performance. Figure
5
depicts typical FXMAR2104 VOL performance vs. a
competitor, given a 0.4V VIL.
If the I2C translator’s channel resistance is too high, the
voltage drop across the translator could present a VIL to
Figure 5. VOL vs. IOL
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
7
master. However, if the OE pin is pulled LOW
(disabled), both ports (A and B) are 3-stated. This
results in the FXMAR2104 isolating slave #2 from the
master and slave #1, allowing full communication
between the master and slave #1.
I2C Bus Isolation
The FXMAR2104 supports I2C-Bus® isolation for the
following conditions:
. Bus isolation if bus clear
Either VCC to GND
. Bus isolation if either VCC goes to ground
Bus Clear
If slave #2 is a camera that is suddenly removed from
the I2C bus, resulting in VCCB transitioning from a valid
Because the I2C specification defines the minimum SCL
frequency of DC, the SCL signal can be held LOW
forever; however, this condition shuts down the I2C bus.
The I2C specification refers to this condition as Bus
Clear. In Figure 6, if slave #2 holds down SCL forever,
the master and slave #1 are not able to communicate
because the FXMAR2104 passes the SCL stuck-LOW
condition from slave #2 to slave #1 as well as the
VCC (1.65V
–
5.5V) to 0V; the FXMAR2104
automatically forces all I/Os on both its A and B ports
into 3-state. Once VCCB has reached 0V, full I2C
communication between the master and slave #1
remains undisturbed.
Figure 6. Bus Isolation
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
8
DC Electrical Characteristics
TA = –40°C to +85°C.
Symbol
Parameter
Condition
Data Inputs An
VCCA (V) VCCB (V)
Min.
Typ.
Max.
Unit
1.65-5.50 1.65-5.50 VCCA – 0.4
1.65-5.50 1.65-5.50 0.7 x VCCA
High Level Input
Voltage A
VIHA
V
Control Input OE
High Level Input
Voltage B
VIHB
VILA
VILB
Data Inputs Bn
Data Inputs An
Control Input OE
1.65-5.50 1.65-5.50 VCCB – 0.4
1.65-5.50 1.65-5.50
V
V
V
0.4
Low Level Input
Voltage A
0.3 x
VCCA
1.65-5.50 1.65-5.50
Low Level Input
Voltage B
Data Inputs Bn
1.65-5.50 1.65-5.50
1.65-5.50 1.65-5.50
1.65-5.50 1.65-5.50
0.4
VIL = 0.15V
Low Level
Output Voltage
VOL
0.4
V
IOL = 6mA
Input Leakage
Current
Control Input OE,
IL
±1
±2
±2
µA
VIN = VCCA or GND
V
IN or VO = 0V
An
0
5.50
0
to 5.5V
Power-Off
Leakage Current
IOFF
µA
µA
VIN or VO = 0V
to 5.5V
Bn
5.50
VO = 0V to
5.5V,
OE = VIL
An,
Bn
5.50
5.50
5.50
0
±2
±2
VO = 0V to
5.5V,
OE = Don’t
Care
3-State Output
Leakage(6)
An
Bn
IOZ
VO = 0V to
5.5V,
OE = Don’t
Care
0
5.50
±2
Quiescent
Supply
V
IN = VCCI or
ICCA B
/
1.65-5.50 1.65-5.50
1.65-5.50 1.65-5.50
5
5
µA
µA
µA
Floating, IO = 0
Current(7,8)
Quiescent
VIN = VCCI or GND,
ICCZ
Supply Current(7) IO = 0, OE = VIL
VIN = 5.5V or GND,
0
1.65-5.50
-2
2
Quiescent
ICCA
IO = 0, OE = Don’t
Care, Bn to An
Supply Current(6)
1.65-5.50
0
0
VIN = 5.5V or GND, IO 1.65-5.50
-2
2
Quiescent
ICCB
= 0, OE = Don’t
Care, An to Bn
µA
Supply Current(6)
0
1.65-5.50
Resistor Pull-up
Value
RPU
VCCA & VCCB Sides
1.65-5.50 1.65-5.50
10
KΩ
Notes:
5. This table contains the output voltage for static conditions. Dynamic drive specifications are given in the Dynamic
Output Electrical Characteristics.
6. “Don’t Care” indicates any valid logic level.
7. VCCI is the VCC associated with the input side.
8. Reflects current per supply, VCCA or VCCB
.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
9
Dynamic Output Electrical Characteristics
Output Rise / Fall Time
Output load: CL = 50pF, RPU = NC, push-pull driver, and TA = -40°C to +85°C.
(10)
VCCO
1.65 to
1.95V
Symbol
Parameter
4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V
Unit
Typical
trise
tfall
Output Rise Time; A Port, B Port(11)
Output Fall Time; A Port, B Port(12)
3
4
8
5
6
7
4
ns
ns
11
Notes:
9. Output rise and fall times guaranteed by design simulation and characterization; not production tested.
10. CCO is the VCC associated with the output side.
V
11. See Figure 11.
12. See Figure 12.
)
Maximum Data Rate(13
Output load: CL = 50pF, RPU = NC, push-pull driver, and TA = -40°C to +85°C.
VCCB
VCCA
Direction
4.5 to 5.5V
3.0 to 3.6V
2.3 to 2.7V
1.65 to 1.95V Unit
Minimum
A to B
B to A
A to B
B to A
A to B
B to A
A to B
B to A
26
26
26
26
26
26
26
26
20
20
20
20
20
20
20
20
16
16
16
16
16
16
16
16
9
4.5V to 5.5V
3.0V to 3.6V
2.3V to 2.7V
MHz
9
9
MHz
9
9
MHz
9
9
1.65V to 1.95V
MHz
9
Note:
13. F-toggle guaranteed by design simulation; not production tested.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXMAR2104 • Rev. 1.0.1
10
AC Characteristics(17)
Output Load: CL = 50pF, RPU = NC, push-pull driver, and TA = -40°C to +85°C.
VCCB
3.0 to 3.6V 2.3 to 2.7V 1.65 to 1.95V Unit
Typ. Max. Typ. Max. Typ. Max. Typ. Max.
Symbol
Parameter
4.5 to 5.5V
VCCA = 4.5 to 5.5V
A to B
tPLH
1
1
3
3
1
2
3
4
1
3
3
5
1
4
3
7
ns
ns
ns
B to A
A to B
tPHL
2
4
3
5
4
6
6
7
B to A
2
4
2
5
2
6
5
7
OE to A
tPZL
4
5
6
10
7
5
9
7
15
15
105
16
1.0
OE to B
3
5
4
5
8
10
65
9
OE to A
tPLZ
65
5
100
9
65
6
105
10
1.0
65
7
105
12
1.0
ns
ns
OE to B
tskew
A Port, B Port(14)
0.5
1.5
0.5
0.5
0.5
VCCA = 3.0 to 3.6V
A to B
tPLH
2.0
1.5
2.0
2.0
4.0
4.0
100
5
5.0
3.0
4.0
4.0
8.0
8.0
115
10
1.5
1.5
2.0
2.0
5.0
6.0
100
4
3.0
4.0
4.0
4.0
9.0
9.0
115
8
1.5
2.0
2.0
2.0
6.0
8.0
100
5
3.0
6.0
1.5
3.0
6.0
3.0
7.0
10.0
100
9
3.0
9.0
ns
ns
ns
B to A
A to B
tPHL
5.0
7.0
B to A
5.0
5.0
OE to A
tPZL
11.0
11.0
115
10
15.0
14.0
115
15
OE to B
OE to A
tPLZ
ns
ns
OE to B
tskew
A Port, B Port(14)
0.5
1.5
0.5
1.0
0.5
1.0
0.5
1.0
VCCA = 2.3 to 2.7V
A to B
tPLH
2.5
1.5
2
5.0
3.0
5
2.5
2.0
2
5.0
4.0
5
2.0
3.0
2
4.0
6.0
5
1.0
5.0
5
3.0
10.0
6
ns
ns
ns
B to A
A to B
tPHL
B to A
2
5
2
5
2
5
3
6
OE to A
tPZL
5.0
4.0
100
65
0.5
10.0
8.0
115
110
1.5
5.0
4.5
100
65
0.5
10.0
9.0
115
110
1.0
6.0
5.0
100
65
0.5
12.0
10.0
115
115
1.0
90.0
9.0
100
12
18.0
18.0
115
25
OE to B
OE to A
tPLZ
ns
ns
OE to B
tskew
A Port, B Port(14)
0.5
1.0
VCCA = 1.65 to 1.95V
A to B
tPLH
4.0
1.0
5
7.0
2.0
8
4.0
1.0
3
7.0
2.0
7
5.0
1.5
3
8.0
3.0
7
5.0
5.0
8
10.0
10.0
9
ns
ns
ns
B to A
A to B
tPHL
B to A
4
8
3
7
3
7
3
7
OE to A
tPZL
11
6
15
14
115
115
1.5
11
6
14
14
115
115
1.0
14
6
28
14
115
115
1.0
14
9
23
OE to B
19
OE to A
tPLZ
75
75
0.5
75
75
0.5
75
75
0.5
75
75
0.5
115
115
1.0
ns
ns
OE to B
tskew
A Port, B Port(14)
Note:
14. Skew is the variation of propagation delay between output signals and applies only to output signals on the same
port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 14). Skew is
guaranteed, but not tested.
15. AC Characteristic is guaranteed by Design and Characterization
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
11
Capacitance
TA = +25°C.
Symbol
Parameter
Condition
Typical Unit
CIN
Input Capacitance Control Pin (OE) VCCA = VCCB = GND
Input/Output Capacitance, An, Bn VCCA = VCCB = 5.0V, OE = GND
2.2
pF
pF
CI/O
13.0
Figure 7. AC Test Circuit
Table 1. Propagation Delay Table(16)
Test
tPLH, tPHL
Input Signal
Output Enable Control
VCCA
Data Pulses
tPZL (OE to An, Bn)
tPLZ (OE to An, Bn)
Note:
0V
0V
LOW to HIGH Switch
HIGH to LOW Switch
16. For tPZL and tPLZ testing, an external 2.2KΩ pull-up resistor to VCCO is required to force the I/O pins HIGH while
OE is LOW. When OE is low, the internal 10KΩ RPUs are decoupled from their respective VCC’s.
Table 2. AC Load Table
VCCO
CL
RL
NC
NC
NC
NC
1.8 ± 0.15V
2.5 ± 0.2V
3.3 ± 0.3V
5.0 ± 0.5V
50pF
50pF
50pF
50pF
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
12
Timing Diagrams
V
CCI
DATA
IN
V
CCA
V
mi
OUTPUT
CONTROL
V
mi
GND
GND
t
t
t
pxx
pxx
PZL
DATA
OUT
V
CCO
V
DATA
OUT
Y
V
V
OL
mo
Figure 8. Waveform for Inverting and Non-Inverting
Functions(17)
Figure 9. 3-STATE Output Low Enable Time(17)
V
CCA
Symbol
Vmi
VCC
OUTPUT
V
mi
CONTROL
GND
VCCI / 2
t
PLZ
Vmo
VCCO / 2
0.5 x VCCO
0.1 x VCCO
DATA
OUT
V
VX
x
V
OL
VY
Figure 10.
3-STATE Output High Enable Time(17)
Figure 11. Active Output Rise Time
Figure 12. Active Output Fall Time
V
CCO
DATA
OUTPUT
V
V
mo
mo
GND
t
period
t
t
skew
skew
V
CCI
DATA
IN
V
/ 2
V
/ 2
CCI
CCI
V
CCO
GND
DATA
OUTPUT
V
V
mo
mo
F-toggle rate, f = 1 / t
period
GND
t
= (t
– t
)
(t
– t
)
skew
pHLmax pHLmin or pLHmax pLHmin
Figure 13. F-Toggle Rate
Figure 14. Output Skew Time
Notes:
17. Input tR = tF = 2.0ns, 10% to 90% at VIN = 1.65V to 1.95V;
Input tR = tF = 2.0ns, 10% to 90% at VIN = 2.3 to 2.7V;
Input tR = tF = 2.5ns, 10% to 90%, at VIN = 3.0V to 3.6V only;
Input tR = tF = 2.5ns, 10% to 90%, at VIN = 4.5V to 5.5 only.
18. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2).
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXMAR2104 • Rev. 1.0.1
13
Physical Dimensions
(11X)
0.563
2.10
1.80
A
B
0.10
C
0.588
0.40
2X
1
1.80
0.10
2.10
PIN#1 IDENT
C
(12X)
0.20
TOP VIEW
2X
RECOMMENDED
LAND PATTERN
0.55 MAX.
0.152
0.10
0.08
C
C
0.45
0.35
0.10
0.05
0.00
SEATING
PLANE
C
0.10
0.10
SIDE VIEW
DETAIL A
SCALE : 2X
0.35
(11X)
NOTES:
0.45
3
6
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
0.40
B. DIMENSIONS ARE IN MILLIMETERS.
DETAIL A
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
1
PIN#1 IDENT
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
12
9
0.25
0.15
(12X)
BOTTOM VIEW
0.10
C A B
E. DRAWING FILENAME: MKT-UMLP12Arev4.
0.05
C
PACKAGE
EDGE
LEAD
LEAD
OPTION 2
SCALE : 2X
OPTION 1
SCALE : 2X
Figure 15. 12-Lead Ultrathin MLP, 1.8mm x 1.8mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
14
© 2011 Fairchild Semiconductor Corporation
FXMAR2104 • Rev. 1.0.1
www.fairchildsemi.com
15
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