FXL2SD106BQX [ONSEMI]
低电压双电源 6 位电压转换器，带自动方向感应;
| 型号： | FXL2SD106BQX |
| 厂家： | 
ONSEMI |
| 描述： | 低电压双电源 6 位电压转换器，带自动方向感应 转换器 |
| 文件： | 总13页 (文件大小：419K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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June 2011
FXL2SD106
Low-Voltage Dual-Supply 6-Bit Voltage
Translator with Auto-Direction Sensing
Features
General Description
– Bi-Directional Interface between Two Levels: 1.1V
and 3.6V
The FXL2SD106 is a configurable dual-voltage-supply
translator designed for both uni-directional and bi-
directional voltage translation between two logic levels.
The device allows translation between voltages as high
as 3.6V to as low as 1.1V. The A port tracks the VCCA
level and the B port tracks the VCCB level. This allows for
bi-directional voltage translation over a variety of voltage
levels: 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
– Fully Configurable: Inputs and Outputs Track VCC
Level
– Non-Preferential Power-up; Either VCC May Be
Powered-up First
– Outputs Remain in 3-State until Active VCC Level is
Reached
The device remains in 3-state until both VCC reach active
levels, allowing either VCC to be powered-up first. Inter-
nal power-down control circuits place the device in 3-
state if either VCC is removed.
– Outputs Switch to 3-State if Either VCC is at GND
– Power-Off Protection
– Bus hold on Data Inputs Eliminates Need for Pull-
up Resistors (Do NOT Use Resistors on the A or B
Ports)
The OE input, when low, disables both A and B ports by
placing them in a 3-state condition. The FXL2SD106 is
– OE and CLK IN are Referenced to VCCA Voltage
– Packaged in 16-Terminal DQFN (2.5mm x 3.5mm)
– Direction Control Not Needed
designed so that OE and CLK IN are supplied by VCCA
.
The device senses an input signal on A or B port auto-
matically. The input signal is transferred to the other port.
– 80 Mbps Throughput Translating between 1.8V
and 2.5V
The FXL2SD106 is not designed for SD card applica-
tions. The internal bus hold circuitry conflicts with pull-up
resistors. SD cards have internal pull-up resistors on the
CD/DAT3 pins.
– ESD Protection Exceeds:
– 12kV HBM (B port I/O to GND)
(per JESD22-A114 & Mil Std 883e 3015.7)
– 8kV HBM (A port I/O to GND)
(per JESD22-A114 & Mil Std 883e 3015.7)
– 1kV CDM (per ESD STM 5.3)
Ordering Information
Order Number
Package Number
Package Description
16-Terminal Depopulated Quad Very-Thin Flat Pack,
No Leads (DQFN), JEDEC MO-241, 2.5mm x 3.5mm
FXL2SD106BQX
MLP16E
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
Connection Diagram
Functional Diagram
VCCA
VCCB
VCCB
VCCA
1
OE
16
2
3
4
5
6
7
15
14
13
12
11
10
CLK IN
A0
CLK OUT
A0 – A4
B0 – B4
B0
B1
B2
B3
B4
CLK OUT
CLK IN
A1
A2
Function Table
Control
OE
A3
Outputs
A4
LOw Logic Level
HIGH Logic Level
3-State
Normal Operation
8
9
OE
GND
Power-Up/Power-Down Sequencing
FXL translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0 volts, outputs are in
a high-impedance state. The control input (OE) is
designed to track the VCCA supply. A pull-down resistor
tying OE to GND should be used to ensure that bus con-
tention, excessive currents, or oscillations do not occur
during power-up / power-down. The size of the pull-down
resistor is based upon the current-sinking capability of
the device driving the OE pin.
Pin Description
Number Name
Description
1
2
VCCA
A-Side Power Supply
CLK IN A-Side Input
3–7
8
A0–A4 A-Side Inputs or 3-State Outputs
OE
Output Enable Input
Ground
The recommended power-up sequence is the following:
9
GND
1. Apply power to the first VCC
.
10–14
15
B4–B0 B-Side Inputs or 3-State Outputs
CLK OUT 3-State Output
2. Apply power to the second VCC
.
16
VCCB
B-Side Power Supply
3. Drive the OE input high to enable the device.
The recommended power-down sequence is the
following:
1. Drive OE input low to disable the device.
2. Remove power from either VCC
3. Remove power from other VCC
.
.
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCCA, VCCB
VI
Parameter
Rating
–0.5V to +4.6V
Supply Voltage
DC Input Voltage
I/O Port A
–0.5V to +4.6V
–0.5V to +4.6V
–0.5V to +4.6V
I/O Port B
OE, CLK IN
VO
Output Voltage(1)
Outputs 3-STATE
Outputs Active (An)
–0.5V to +4.6V
–0.5V to VCCA + 0.5V
–0.5V to VCCB + 0.5V
Outputs Active (Bn, CLK OUT)
IIK
DC Input Diode Current at VI 0V
–50mA
IOK
DC Output Diode Current at
VO 0V
–50mA
+50mA
VO VCC
IOH /IOL
ICC
DC Output Source/Sink Current
DC VCC or Ground Current per Supply Pin
Storage Temperature Range
–50mA / +50mA
±100mA
TSTG
–65°C to +150°C
Note:
1. IO Absolute Maximum Rating must be observed.
(2)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
1.1V to 3.6V
VCCA or VCCB
Power Supply Operating
Input Voltage
Port A
0.0V to 3.6V
0.0V to 3.6V
0.0V to VCCA
Port B
OE, CLK IN
Dynamic Output Current in IOH/IOL with VCC at
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
1.4V to 1.65V
1.1V to 1.4V
±18.0mA
±11.8mA
±7.4mA
±5.0mA
±2.6mA
Static Output Current IOH/IOL with VCC at 1.1V to 3.6V
Free Air Operating Temperature
±20.0µA
–40°C to +85°C
10ns/V
TA
t
/
V
Maximum Input Edge Rate VCCA/B 1.1V to 3.6V
Note:
2. All unused inputs and I/O pins must be held at VCCI or GND.
© 2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXL2SD106 • Rev. 1.8.1
3
DC Electrical Characteristics (TA = –40°C to +85°C)
Symbol
Parameter
VCCA (V)
1.4–3.6
1.1–1.4
1.1–3.6
1.1–3.6
1.4–3.6
1.1 –1.4
1.1–3.6
1.1–3.6
1.65–3.6
1.1–1.4
1.1–3.6
1.1–3.6
1.65–3.6
1.1–1.4
1.1–3.6
1.1–3.6
3.6
VCCB (V)
1.1–3.6
1.1–3.6
1.4–3.6
1.1–1.4
1.1–3.6
1.1–3.6
1.4–3.6
1.1–1.4
1.1–3.6
1.1–3.6
1.65–3.6
1.1–1.4
1.1–3.6
1.1–3.6
1.65–3.6
1.1–1.4
3.6
Conditions
Min.
Typ.
Max.
Units
VIH
High Level
Input Voltage
Data inputs An, CLK IN,
OE
0.6 x VCCA
0.9 x VCCA
0.6 x VCCB
0.9 x VCCB
V
Data inputs Bn
VIL
Low Level
Input Voltage
Data inputs An, CLK IN,
OE
0.35 x VCCA
0.1 x VCCA
0.35 x VCCB
0.1 x VCCB
V
V
Data inputs Bn
(3)
VOH
High Level
Output Voltage
Data outputs An,
IHOLD = –20µA
0.75 x VCCA
0.75 x VCCB
0.8
0.8
0.3
0.3
Data outputs Bn,
HOLD = –20µA
I
(3)
VOL
Low Level
Output Voltage
Data outputs An,
HOLD = 20µA
0.2 x VCCA
0.2 x VCCB
V
I
Data outputs Bn,
HOLD = 20µA
I
(4)
II(ODH)
Bushold Input
Overdrive High
Current
Data inputs An, Bn
450
300
200
120
80
µA
2.7
2.7
1.95
1.95
1.6
1.6
1.4
1.4
(5)
II(ODL)
Bushold Input
Overdrive Low
Current
3.6
3.6
Data inputs An, Bn
-450
-300
-200
-120
-80
µA
2.7
2.7
1.95
1.95
1.6
1.6
1.4
1.4
II
Input Leakage
Current
1.1–3.6
3.6
OE, CLK IN, VI = VCCA or
GND
±1.0
µA
µA
IOFF
Power Off
Leakage
Current
0
3.6
0
An, VO = 0V to 3.6V
Bn, CLK OUT,
±2.0
±2.0
3.6
VO = 0V to 3.6V
(6)
IOZ
3-State Output
Leakage
3.6
3.6
3.6
0
An, Bn, CLK OUT, VO = 0V
or 3.6V, OE = VIL
±2.0
±2.0
±2.0
5.0
µA
An, VO = 0V or 3.6V,
OE = Don’t Care
0
3.6
Bn, CLK OUT, VO = 0V or
3.6V, OE = Don’t Care
(7)(8)
ICCA/B
Quiescent
Supply
1.1–3.6
VI = VCCI or GND, IO = 0
µA
1.1–3.6
Current
(7)
ICCZ
Quiescent
Supply Current
1.1–3.6
VI = VCCI or GND, IO = 0,
OE = VIL
5.0
µA
µA
1.1–3.6
(7)
ICCA
Quiescent
Supply Current
0
1.1–3.6
0
VI = VCCB or GND; IO = 0
VI = VCCA or GND; IO = 0
-2.0
2.0
1.1–3.6
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
4
DC Electrical Characteristics (TA = –40°C to +85°C) (Continued)
Symbol
Parameter
VCCA (V)
1.1–3.6
0
VCCB (V)
0
Conditions
Min.
Typ.
Max.
-2.0
2.0
Units
(7)
ICCB
Quiescent
Supply Current
VI = VCCB or GND; IO = 0
VI = VCCA or GND; IO = 0
µA
1.1–3.6
Notes:
3. This is the output voltage for static conditions. Dynamic drive specifications are given in “Dynamic Output Electrical
Characteristics.”
4. An external driver must source at least the specified current to switch LOW-to-HIGH.
5. An external driver must source at least the specified current to switch HIGH-to-LOW.
6. “Don’t Care” indicates any valid logic level.
7. VCCI is the VCC associated with the input side.
8. Reflects current per supply, VCCA or VCCB
.
(9)
Dynamic Output Electrical Characteristics
A Port (A )
n
Output Load: CL = 15pF, RL 1M
TA = -40°C to +85°C, VCCA =
3.0V to 3.6V 2.3V to 2.7V 1.65V to 1.95V 1.4V to 1.6V 1.1V to 1.3V
Symbol
Parameter
Typ. Max. Typ. Max.
Typ.
Max.
Typ. Max.
Typ.
Units
(10)
Output Rise
Time A Port
trise
3.0
3.5
4.0
5.0
7.5
ns
(11)
Output Fall Time
A Port
tfall
3.0
3.5
4.0
5.0
7.5
-2.6
+2.6
ns
(10)
Dynamic Output
Current High
IOHD
-18.0
-11.8
-7.4
-5.0
mA
mA
(11)
Dynamic Output
Current Low
IOLD
+18.0
+11.8
+7.4
+5.0
B Port (B , CLK OUT)
n
Output Load: CL = 15pF, RL 1M
TA = -40°C to +85°C, VCCB =
3.0V to 3.6V 2.3V to 2.7V 1.65V to 1.95V 1.4V to 1.6V 1.1V to 1.3V
Symbol
Parameter
Typ. Max. Typ. Max.
Typ.
Max.
Typ. Max.
Typ.
Units
(10)
Output Rise
Time B Port
trise
3.0
3.5
4.0
5.0
7.5
ns
(11)
Output Fall Time
B Port
tfall
3.0
3.5
4.0
5.0
7.5
-2.6
+2.6
ns
(10)
Dynamic Output
Current High
IOHD
-18.0
-11.8
-7.4
-5.0
mA
mA
(11)
Dynamic Output
Current Low
IOLD
+18.0
+11.8
+7.4
+5.0
Notes:
9. Dynamic Output Characteristics are guaranteed, but not tested.
10. See Figure 5.
11. See Figure 6.
© 2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXL2SD106 • Rev. 1.8.1
5
AC Characteristics
V
= 3.0V to 3.6V
CCA
TA = -40°C to +85°C, VCCB
=
3.0V–3.6V
2.3V–2.7V
1.65V–1.95V
1.4V–1.6V
1.1V–1.3V
Typ.
22.0
Symbol
Parameter
A to B
Min. Max. Min. Max. Min.
Max. Min. Max.
Units
ns
t
, t
0.2
0.2
3.5
3.5
3.0
1.7
0.5
0.3
0.2
3.9
3.8
3.5
1.7
0.5
0.5
0.3
5.4
5.0
4.5
1.7
0.5
0.6
0.5
6.8
6.0
6.0
1.7
1.0
PLH PHL
B to A
15.0
ns
t
, t
CLK IN to CLK OUT
OE to A, OE to B
A Port, B Port
15.0
ns
PLH PHL
t
, t
1.7
µs
PZL PZH
(12)
t
1.0
ns
skew
V
= 2.3V to 2.7V
CCA
TA = -40°C to +85°C, VCCB
=
3.0V–3.6V
2.3V–2.7V
1.65V–1.95V
1.4V–1.6V
1.1V–1.3V
Typ.
22.0
Symbol
Parameter
A to B
Min. Max. Min. Max. Min.
Max. Min. Max.
Units
ns
t
, t
0.2
0.3
3.8
3.9
3.5
1.7
0.5
0.4
0.4
4.2
4.2
4.0
1.7
0.5
0.5
0.5
5.6
5.5
4.5
1.7
0.5
0.8
0.5
6.9
6.5
6.5
1.7
1.0
PLH PHL
B to A
15.0
ns
t
, t
CLK IN to CLK OUT
OE to A, OE to B
A Port, B Port
15.0
ns
PLH PHL
t
, t
1.7
µs
PZL PZH
(12)
t
1.0
ns
skew
V
= 1.65V to 1.95V
CCA
TA = -40°C to +85°C, VCCB
=
3.0V–3.6V
2.3V–2.7V
1.65V–1.95V
1.4V–1.6V
1.1V–1.3V
Typ.
22.0
Symbol
Parameter
A to B
Min. Max. Min. Max. Min.
Max. Min. Max.
Units
ns
t
, t
0.3
0.5
5.0
5.4
4.5
1.7
0.5
0.5
0.5
5.5
5.6
4.5
1.7
0.5
0.8
0.8
6.7
6.7
6.3
1.7
0.5
0.9
1.0
7.5
7.0
6.7
1.7
1.0
PLH PHL
B to A
15.0
ns
t
, t
CLK IN to CLK OUT
OE to A, OE to B
A Port, B Port
15.0
ns
PLH PHL
t
, t
1.7
µs
PZL PZH
(12)
t
1.0
ns
skew
V
= 1.4V to 1.6V
CCA
TA = -40°C to +85°C, VCCB
=
3.0V–3.6V
2.3V–2.7V
1.65V–1.95V
1.4V–1.6V
1.1V–1.3V
Typ.
22.0
Symbol
Parameter
A to B
Min. Max. Min. Max. Min.
Max. Min. Max.
Units
ns
t
, t
0.5
0.6
6.0
6.8
6.0
1.7
1.0
0.5
0.8
6.5
6.9
6.5
1.7
1.0
1.0
0.9
7.0
7.5
6.7
1.7
1.0
1.0
1.0
8.5
8.5
8.5
1.7
1.0
PLH PHL
B to A
15.0
ns
t
, t
CLK IN to CLK OUT
OE to A, OE to B
A Port, B Port
15.0
ns
PLH PHL
t
, t
1.7
µs
PZL PZH
(12)
t
1.0
ns
skew
Note:
12. Skew is the variation of propagation delay between output signals and applies only to output signals on the same
port (An or Bn) and switching with the same polarity (Low-to-High or High-to-Low). See Figure 8.
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
6
(13)(14)
Maximum Data Rate
T = -40°C to +85°C, V
=
CCB
A
3.0V to 3.6V 2.3V to 2.7V 1.65V to 1.95V 1.4V to 1.6V 1.1V to 1.3V
V
Min.
100
100
80
Min.
100
100
80
Min.
80
Min.
60
Typ.
20
Units
Mbps
Mbps
Mbps
Mbps
CCA
VCCA = 3.0V to 3.6V
VCCA = 2.3V to 2.7V
VCCA =1.65V to 1.95V
VCCA = 1.4V to 1.6V
80
60
20
60
40
20
60
60
40
40
20
Typ.
20
Typ.
20
Typ.
20
Typ.
20
Typ.
20
VCCA = 1.1V to 1.3V
Mbps
Note:
13. Maximum data rate is guaranteed but not tested.
14. Maximum data rate is specified in megabits per second. See Figure 7. It is equivalent to two times the F-toggle
frequency, specified in megahertz. For example, 100 Mbps is equivalent to 50 MHz.
Capacitance
T = +25°C
A
Symbol
Parameter
Conditions
Typical
Units
pF
C
4
5
Input Capacitance, OE, CLK IN
VccA = VccB = GND
IN
C
pF
Input/Output
Capacitance
An
VccA = VccB = 3.3V,
OE = VccA
I/O
6
Bn, CLK OUT
C
25
pF
Power Dissipation Capacitance
VccA = VccB = 3.3V,
PD
Vi = 0V or Vcc, f = 10MHz
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
7
V
CC
TEST
SIGNAL
DUT
C1
R1
Output Enable
Control
Test
tPLH, tPHL
tPZL
Input Signal
Data Pulses
0V
VCCA
Low to High Switch
Low to High Switch
tPZH
VCCI
Figure 1. AC Test Circuit
AC Load Table
V
Cl
Rl
CCO
1.2V ± 0.1V
1.5V ± 0.1V
1.8V ± 0.15V
2.5V ± 0.2V
3.3 ± 0.3V
15pF
15pF
15pF
15pF
15pF
1M
1M
1M
1M
1M
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
8
V
CCI
DATA
IN
V
mi
V
V
CCA
OUTPUT
CONTROL
GND
V
mi
t
t
GND
pxx
pxx
t
PZL
V
CCO
DATA
OUT
mo
DATA
OUT
V
Y
V
OL
Input tR = tF = 2.0ns, 10% to 90%
Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Input tR = tF = 2.0ns, 10% to 90%
Figure 2. Waveform for Inverting and
Non-inverting Functions
Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Figure 3. 3-STATE Output Low Enable Time for Low
Voltage Logic
Symbol
Vmi(15)
Vmo
Vcc
V
CCA
OUTPUT
V
VCCI / 2
mi
CONTROL
GND
VCCO / 2
0.9 x VCCO
0.1 x VCCO
t
PZH
V
OH
VX
DATA
OUT
V
x
VY
Note:
15. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2).
Input tR = tF = 2.0ns, 10% to 90%
Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Figure 4. 3-STATE Output High Enable Time for
Low Voltage Logic
V
OH
t
fall
t
rise
V
OH
80% x V
CCO
80% x V
CCO
VOUT
VOUT
20% x V
CCO
20% x V
CCO
V
OL
V
OL
Time
= (C
Time
ΔV
Δt
(20% – 80%) x V
ΔV
Δt
(80% – 20%) x V
CCO
OUT
CCO
OUT
I
≈ (C
C
) x
= (C
C
) x
I
≈ (C
C
) x
C
) x
OHD
L + I/O
L + I/O
OLD
L + I/O
L + I/O
t
t
FALL
RISE
Figure 5. Active Output Rise Time and Dynamic
Output Current High
Figure 6. Active Output Fall Time and Dynamic
Output Current Low
V
CCO
DATA
OUTPUT
V
mo
V
mo
t
W
GND
t
t
skew
skew
V
CCI
DATA
IN
V
/2
V
/2
CCI
CCI
V
CCO
GND
DATA
OUTPUT
V
mo
V
mo
Max. data rate, f = 1/t
W
GND
Figure 7. Maximum Data Rate
t
= (t
– t
)
(t
– t
)
pLHmin
skew
pHLmax
pHLmin or pLHmax
Figure 8. Output Skew Time
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
9
Physical Dimensions
Figure 9. 16-Terminal Depopulated Quad, Very-Thin Flat Pack, No Leads (DQFN),
JEDEC MO-241 2.5mm x 3.5mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
For current tape and reel specifications, visit Fairchild Semiconductor’s packaging area:
http://www.fairchildsemi.com/ms/MS/MS-522.pdf
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
10
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
www.fairchildsemi.com
11
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