FUSB15201VMNWTWG_技术文档

DATA SHEET

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Dual Port USB Type-C & PD

Controller

24

1

QFNW24 4x4, 0.5P

CASE 484AU

FUSB15201

The FUSB15201 is a highly integrated dual port USB Type−C and

Power Delivery Controller optimized for automotive and industrial

power sourcing applications. The FUSB15201 enables a complete

solution for USB power sources through optimized hardware

peripherals and complete open−source embedded firmware all in a

compact solution. Maximizing total system power budgets is enabled

through both hardware and firmware of the FUSB15201.

onsemi offers a complete open−source embedded firmware solution

that draws inputs from various hardware peripherals and system level

USB−PD identifiers to provide the most optimal power sharing across

ports while staying within the total power budget.

System designers can easily tailor this algorithm to meet the specific

needs of their end application through an easy to use API for the

embedded firmware. The FUSB15201 also provides a completely

USB PD3.1 compliant solution with interoperability with leading

mobile and computing devices in the market.

MARKING DIAGRAM

FUSB

FUSB15

201DV

ALYWG

G

15201V

ALYWG

G

FUSB15201V = Specific Device Code

A

L

Y

W

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

†

Device

Package Shipping

Key Features

FUSB15201VMNWTWG QFNW24 4,000 / Tape

& Reel

• Small Footprint Dual−port USB PD Controller Supporting

the most Popular Peripherals

♦ USB PD 3.1 & USB Type−C 2.1

♦ I C Master/Slave

FUSB15201DVMNWTWG QFNW24 4,000 / Tape

& Reel

2

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

♦ Dual USB BC1.2 Provider Emulation

• Fully Programmable and Upgradable Open−source Firmware

providing API for Customer Specific Device Policy Manager

Development

• High Voltage Protection on CC and D+/− Pins

• Supports Firmware Upgrades via USB−C

• 10−bit ADC for Accurate Monitoring of VBUS, External

Temperature and Voltages

• External Temperature Monitoring via NTC Resistors

• 24−Pin QFNW Package (4 mm x 4 mm, 0.5 mm Pitch)

• Grade 2 AEC−Q100 Qualified

• These are Pb−free Devices

Typical Applications

• Automotive

• Power Outlets

• Wall Chargers

1

Publication Order Number:

August, 2022 − Rev. 4

FUSB15201/D

FUSB15201

Features

• Arm Cortex−M0+: A 32−bit core with flexible clocking

up to 24 MHz

• Memories: A total of 132 kB of flash is available to store

program code. 6 kB of SRAM program memory.

• USB Type−C and PD: Integrated USB PD PHY and

Type−C termination/comparators supporting latest

USB−IF specification.

• Integrated VCONN Switch: Provides the full 1.5 W

power to interrogate cable eMarkers and power active

cables.

• GPIOs: Fully programmable I/Os with internal

terminations. Configurable as input or output (CMOS or

open−drain).

• Programmable

VBUS

discharge:

Internal

programmable resistors capable of discharging up to

100 mF

• Multiple Timers: Four independent 32−bit timers are

available: 2 General Purpose, 1 Watchdog, and 1

Wake−up / General Purpose

• External NTC: Integrated current sources are used in

conjunction with the ADC to monitor a variety of NTC

resistors.

• Low Power Operation Modes: Programmable sleep

modes allowing device to minimize power usage as

needed. Automatic USB−C detection and wake−up

functionality from sleep modes.

• BC1.2 Support: Fully programmable USB BC1.2

interface is capable of presenting as CDP, DCP or SDP.

• High Voltage Protection: Robust USB−C connector

interface with 28 V DC tolerant VBUS and CC. 20 V DC

D+/−for FUSB15201 and 28 V DC D+/−for FUSB15201D

• ADC: Multi−channel 10−bit ADC for accurate

monitoring of VBUS, external temperature and voltages.

• Automotive Ready: Grade

2 temperature range

performance and AECQ−100 Qualified. QFN package

2

• I C: Serial communication port capable of acting as a

with 0.5 mm pitch and wettable flank.

host or device allowing control of external system

peripherals by FUSB15201.

FUSB15201 INTERNAL BLOCK DIAGRAM

FUSB15201 − Dual Port PD Controller

ARM Cortex M0+

Interrupts

2x Timers, WDT, WUT

Flash

(132KB)

RAM

(6KB)

Serial Wire Debug

AHB

Peripheral Bus

Type−C Port A

GPIOs

I²C

USB PD PHY

VCONN FET w/ OCP

BC1.2 Emulation

Type−C Port B

Power Management

Internal Regulators

Reset

USB PD PHY

VCONN FET w/ OCP

BC1.2 Emulation

2x NTC Resistor Monitoring

Figure 1. FUSB15201 Block Diagram

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2

FUSB15201

18

17

16

15

14

13

1

2

3

4

5

6

VBUS_B

VBUS_A

HVCC2_A

VDD

HVCC2_B

VDD

GND

HVCC1_B

HVDP_B

HVDM_B

HVCC1_A

HVDP_A

HVDM_A

Figure 2. Pin Diagram

Table 1. FUNCTION DESCRIPTION

Pin #

1

Name

VBUS_A

Port

Description

Analog

Power

Analog

PA1

Port A VBUS. Monitoring Discharge (28 V)

Port A High Voltage Configuration Channel 2 (28 V)

Power Supply

2

HVCC2_A

VDD

3

4

HVCC1_A

HVDP_A

Port A High Voltage Configuration Channel 1 (28 V)

Port A High Voltage USB 2.0 D+ (FUSB15201: 20 V; FUSB15201D: 28 V)

Port A High Voltage USB 2.0 D− (FUSB15201: 20 V; FUSB15201D: 28 V)

General Purpose I/O/ Serial Wire Debug Port Clock

General Purpose I/O/ Serial Wire Debug Port Data

General Purpose I/O

5

6

HVDM_A

GPIO1/SWCK

GPIO2/SWD

GPIO3

7

8

PA2

9

PA3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DAP

GND

Ground

Power

Input

Ground

VDDIO

I/O Power Supply

RESET_N

HVDM_B

HVDP_B

Reset

Analog

Power

Analog

PA4

Port B High Voltage USB 2.0 D− (FUSB15201: 20 V; FUSB15201D: 28 V)

Port B Hight Voltage USB 2.0 D+ (FUSB15201: 20 V; FUSB15201D: 28 V)

Port B High Voltage Configuration Channel 1 (28 V)

Power Supply

HVCC1_B

VDD

HVCC2_B

VBUS_B

Port B High Voltage Configuration Channel 2 (28 V)

Port B VBUS. Monitoring Discharge (28 V)

Port B External NTC sense Pin / General Purpose I/O

NTC_B/GPIO4

I2C_INT1/GPIO5

I2C_SDA1/GPIO6

I2C_SCL1/GPIO7

CAP

2

PA5

I C Port Interrupt / General Purpose I/O

2

PA6

I C Port Data / General Purpose I/O

2

PA7

I C Port Clock / General Purpose I/O

Analog

PA8

1.5V capacitor

NTC_A/GPIO8

GND

Port A External NTC sense Pin / General Purpose I/O

Ground

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3

FUSB15201

APPLICATIONS DIAGRAM

The figure below shows a typical dual port automotive

External NTC resistors monitor temperature at each port and

is used for over−temperature protection or to dynamically

change power capabilities.

source application. The FUSB15201 communicates to the

2

DC−DC controllers via integrated I C host peripheral.

CSN1_A

CSP2_A CSN2_A

CSP1_A

NVMFS5A140PLZ

VSW1_A

VSW2_A

HSG2_A

NVTFS4C10N

HSG1_A

NVTFS4C10N

SZ1SMB40

CAT3G

SZMM3Z1

8VT1G

2 x

NSVR0240V2

LSG 1_A

LSG 2_A

VCC_A

NVTFS4C10N

EN

BST1

BST2

HSG1

V1

HSG1_A

LSG 1 LSG 1_A

VCCD

VDRV

VCC

HSG2

LSG 2

HSG2_A

LSG 2_A

VCC_A

NCV81599

PGND1

PGND2

CSP1

CSN1

CSP2

CSN2

FB

CS1

CS2

COMP

VSW1

VSW2

VBUS_A

VSW1

VSW2

PDRV

CSP1_A

CSN1_A

CSP2_A

CSN2_A

SZESD

INT

SDA

SCL

INT

7241

SDA

SCL

CLIND

ADDR

AGND GND

VINT

CC2_A

DM_ A

VINT

DP_ A

CC1_A

Optional.

Use LDO in low I_Qapplications,

or use VCC_A or VCC_B from

NCV81599 instead of LDO.

4 x

SZESD

VI NT

7272

FUSB15201

NCV8730B

VINT

LDO

INT

SDA

NTC

SCL

CSP2_B CSN2_B

CSP1_B

CSN1_B

GPIO1

GPIO2

VSW1

VSW2

HSG2_B

NVTFS4C10N

HSG1_B

NVTFS4C10N

2 x

LSG 2_B

LSG 1_B

NSVR0240V2

NVTFS4C10N

VCC_B

NVTFS4C10N

CC2_B

DM_

DP_

B

EN

BST1

BST2

HSG1

V1

HSG1_B

CC1_B

LSG 1 LSG 1_B

VCCD

VDRV

VCC

HSG2

LSG 2

HSG2_B

LSG 2_B

VCC_B

4 x

SZESD

NCV81599

PGND1

PGND2

CSP1

CSN1

CSP2

CSN2

FB

VSW1_B

VSW2_B

VSW1

VSW2

7272

CSP1_B

CSN1_B

CSP2_B

CSN2_B

PDRV

INT

SDA

SCL

SDA

SCL

CLIND

ADDR

VBUS_B

CS1

CS2

COMP

AGND GND

SZESD

7241

Figure 3. Automotive Application Schematic

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4

FUSB15201

ELECTRICAL SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1, 2, 3)

Symbol

Parameter

Minimum

−0.3

−0.5

−0.3

−0.5

−40

Maximum

28

Unit

V

VBUS

VBUS Pin Voltage

V

HVCC1, HVCC2 Connector Pins

HVDP, HVDM Connector Pins (FUSB15201)

HVDP, HVDM Connector Pins (FUSB15201D)

I/O Voltage

28

V

CONNECTOR

V

USB

20

V

28

V

VIO

VDD

6.0

V

Supply Voltage

6.0

V

VDDIO

VCAP

VDDIO Supply

6.0

V

CAP Pin

2.0

V

T

J

Junction Temperature

150

260

°C

kV

V

T

STG

Storage Temperature

−40

TL

Lead Temperature (Soldering, 10 Seconds)

Human Body Model, ANSI/ESDA/JEDEC JS*001*2012 (Note 3)

Charged Device Model, JESD22*C101 (Note 3)

ESD

2

HBM

CDM

ESD

750

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. All voltage values, except differential voltages, are given with respect to the GND Pin.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

3. Meets JEDEC standards JS−001−2012 and JESD 22−C101.

Table 3. RECOMMENDED ESD DEVICES

Function

Manufacturer

onsemi

Part Number

Type−C Connector Pins ESD

TBD

Table 4. THERMAL RATINGS (Note 4)

Symbol

Parameter

Junction−to−Ambient Thermal Resistance

Min

Typ

Max

Unit

q

57

°C/W

JA

4. T = 25°C unless otherwise specified with JEDEC 2S2P board with no thermal vias.

A

Table 5. OPERATING RATINGS

Symbol

Parameter

Min

3.0

3.1

1.7

0

Typ

Max

5.5

Unit

V

DD

Supply Voltage Range

Voltage

3.3

V

BUS

V

22.05

5.5

V

BUS

V

DDIO

I/O Supply Voltage

V

Communication Channel Pins

HVDM, HVDP Pins

5.5

V

HVCCx

HVUSB

V

0

3.6

V

2

V

IO

GPIO, I C, RESET

0

5.5

V

T

A

Operating Ambient Temperature

−40

+105

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

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5

FUSB15201

Table 6. ELECTRICAL CHARACTERISTICS

Minimum and maximum values are at V = 2.8 V to 5.5 V, T = −40°C to +105°C unless otherwise noted.

DD

A

Typical values are at T = 25°C, V = 3.3 V

A

DD

TYPE−C AND PD SECTION

USB PD PHY

TRANSMITTER

Symbol

Parameter

Conditions

Min

Typ

Max

3.7

Units

μs

UI

Unit Interval

3.03

3.33

pBitRate

Maximum difference between

the bit−rate during the payload

and last 32 bits of preamble

0.25

%

tEndDriveBMC

tHoldLowBMC

Time to cease driving the line after

the end of the last bit of the Frame

23

μs

Time to cease driving the line

after the final high−to−low transition

1

tInterFrameGap Any PD transmission cannot

be sent out before a dead time

25

of at least tInterFrameGap

from receiving or sending a packet

tFall

tRise

Fall Time

Rise Time

300

−1

ns

μs

tStartDrive

Time before the start of the first bit

of the preamble when the

1

transmitter shall start driving the line

vSwing

zDriver

BMC voltage swing

1.05

33

1.125

1.2

75

V

TX output impedance at 750 kHz

with an external 220 pF

or equivalent load

Ω

RECEIVER

cReceiver

Receiver capacitance when driver

isn’t turned on

Vrms=0.371; Vdc=0.5 V;

Freq.=1 MHz

75

pF

tRxFilter

Rx bandwidth limiting filter

100

12

ns

μs

tTransitionWindow Time window for detecting non−idle

20

vFRSwapCableTx The Fast Role Swap Request has

to be below this voltage threshold

to be detected.

490

520

550

mV

zBmcRx

Receiver Input Impedance

(cannot be tested but can be

simulated and guaranteed by design)

1

MΩ

TYPE−C FRONT END

R

VBUS Leakage Impedance to

ground when VBUS is not sourced

72.4

kΩ

VBUS−LEAK

I

SRC 80 μA CC current (Default)

SRC 180 μA CC current (1.5 A)

SRC 330 μA CC current (3 A)

Device pull−down resistance

Powered Cable Termination

64

80

96

194

356

5.6

μA

kΩ

Ω

80_CCX

I

166

304

4.6

180

330

5.1

180_CCX

330_CCX

I

R

DEVICE

R

800

126

1200

A

zOPEN

CC resistance for disabled state,

when Vdd is valid

kΩ

R

Rdson for VDD to CC1

or VDD to CC2

I

= 0 to 600 mA,

0.85

1.8

Ω

SW_CCx

SW_CCX

VCONN_OCP > 80 mA

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6

FUSB15201

Table 6. ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at V = 2.8 V to 5.5 V, T = −40°C to +105°C unless otherwise noted.

DD

A

Typical values are at T = 25°C, V = 3.3 V

A

DD

Symbol

TYPE−C FRONT END

Parameter

Conditions

Min

Typ

Max

Units

R

Low OCP setting Rdson

I

= 0 to 80 mA,

2.7

5

Ω

SW_CCx_LOW_O

CP

SW_CCx

for VDD to CC1 or VDD to CC2

VCONN_OCP v 80 mA

VCONN_OCP = 800 mA

I

Over Current Protection (OCP)

limit at which VCONN switch

shuts off over the entire VCONN

voltage range

600

5.6

800

1000

mA

SW_CCx

V

CC1/2 Over−Voltage Protection

6.0

V

CCx_OVP

vRdSRCUSB

vRdSRC1.5

vRdSRC3.0

vRaSRCUSB

vRaSRC1.5

vRaSRC3.0

vRdSNKUSB

vRdSNK1.5

vRdSNK3.0

vRaSNK

Source attach threshold for CC Pin

at default current

1.5

1.6

1.65

2.75

0.25

0.45

0.85

0.7

V

Source attach threshold for CC Pin

at 1.5 A current

Source attach threshold for CC Pin

at 3 A current

2.45

0.15

0.35

0.75

0.61

1.16

2.04

0.15

0.6

2.6

Source Ra threshold for CC Pin

at default current

0.2

Source Ra threshold for CC Pin

at 1.5 A current

0.4

Source Ra threshold for CC Pin

at 3 A current

0.8

Attach threshold for CC Pin SNK

(default current)

0.66

1.23

2.11

0.2

Attach threshold for CC Pin SNK

(1.5 A current)

1.31

2.18

0.25

0.8

Attach threshold for CC Pin SNK

(3 A current)

Attach threshold for CC Pin SRC

or SNK

VSafe0V

Safe Operating Voltage at 0 V

VBUS DISCHARGE

R

Pull−down Resistance applied to

VBUS when selected

VBUS = 0.8 V to 21.5 V

315

420

450

600

585

780

W

VBUS DISCH 0

VBUS DISCH 1

VBUS DISCH 2

VBUS DISCH 3

VBUS DISCH 4

VBUS DISCH 5

R

525

750

975

700

1000

2000

6.00

1300

2600

7.80

1400

4.20

kW

μA

CURRENT CONSUMPTION

I

Current consumption

when in deep sleep

VDD = VDDIO = 3.0 to

5.5 V VBUS = 0 V;

75

SLEEP−UNATTACH

ED

Not Type−C attached,

DRP Toggling; LSOSC

enabled; BC1.2 disabled

I

Sleep Current

VDD = VDDIO = 3.0 to

5.5 V VBUS = 0 V;

700

μA

SLEEP

2

No I C traffic, LSOSC

running; PD Peripheral

and ADC enabled. No

PD traffic.

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7

FUSB15201

Table 6. ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at V = 2.8 V to 5.5 V, T = −40°C to +105°C unless otherwise noted.

DD

A

Typical values are at T = 25°C, V = 3.3 V

A

DD

Symbol

CURRENT CONSUMPTION

Port with PD traffic

Parameter

Conditions

Min

Typ

Max

Units

I

Active and communicat-

ing via USB PD trans-

mitting and receiving

packets on both ports

4.0

mA

PD−ACTIVE

PMU

V

POR Trip point

VDD Rising

1.0

3.0

2.4

V

VDD POR

V

Minimum VDD level

for enabling device

VDD_GOOD

V

VDDIO Detection Threshold used

in asserting PMU_STS when

VDDIO is above it.

VDDIO Rising

VDD Falling

1.0

3.0

V

VDDIO_GOOD

V

VDD Brown Out Threshold

2.6

VDD BRWN

CLOCKS

F

Low Speed Clock for Idle,

114

120

24

126

kHz

LS_CLK

Type−C Attach

F

Internal clock for Active Core

and full function

22.8

25.2

MHz

HS_CLK

INTERNAL TEMPERATURE PROTECTION

T

Temperature for internal

temperature protection

VDD= 3.0 V to 5.5 V

145

10

°C

SHUT

T

Temp hysteresis for internal

temperature protection

HYS

EXTERNAL TEMPERATURE MEASUREMENT

I

Current Source on NTCA

Current Source on NTCB

55

60

65

μA

NTCA

NTCB

BC1.2 DETECTION

R

DCP Emulation Resistance

VD+/D− = 0 V, 1.0 V, ION

= 2 mA

80

180

Ω

DCP

R

DP/DM pull down resistance

DCD Source Current

VD+/− = 0 V − 3.6 V

VDD = 3.0 V to 5.5 V

5mA pulled out of DP

5mA pulled out of DM

V(sw) = 0 V to 3.6 V

16

7

19.5

10

23

13

kΩ

μA

V

Dx_DWN

I

DP_SRC

I

Sink Current to Dx

25

75

175

2.85

36

Dx_SNK

V

DIV

Divider Mode Output Voltage

Divider Mode resistance on DP

Divider Mode resistance on DM

2.65

24

2.75

30

R

DIVP

DIVM

kΩ

R

24

30

36

R

Resistor weak pull−down

on D+ and D−

300

700

1100

DAT_LKG

V

Source Voltage

VDD = 3.0 V to 5.5 V

0.5

4.4

288

0.9

0.6

4.55

320

1.0

0.7

4.7

352

1.1

V

Dx_SRC

V

D+/D− Over−Voltage Protection

Pull−Up Moisture Detection Resistor

Dx OVP

PU MOS

SRC MOS

R

kΩ

V

Voltage Source for Moisture Detec-

tion

SERIAL WIRE DEBUG INTERFACE

F

Serial Wire Debug

Input Clock Frequency

Core frequency = 24 MHz

10

MHz

SWDCLK

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8

FUSB15201

Table 6. ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at V = 2.8 V to 5.5 V, T = −40°C to +105°C unless otherwise noted.

DD

A

Typical values are at T = 25°C, V = 3.3 V

A

DD

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SERIAL WIRE DEBUG INTERFACE

T

Serial Wire Debug

Data Setup timing

0.25*(1/SWCLK)

ns

SWDI_SET

T

Serial Wire Debug Data Hold Timing

0.25*(1/SWCLK)

0.7 x VDDIO

ns

V

SWDI_HOLD

V

Serial Wire Debug

Input voltage threshold

VDDIO = 1.7 V to 5.5 V

IH−SWD

V

0.3 x VDDIO

+10

IL−SWD

V

Serial Wire Debug

Input Voltage Hysteresis

300

mV

HYS−SWD

I

Serial Wire Debug Input Leakage

VDDIO = 1.7 V to 5.5 V,

Input Voltage 0 V to 5.5 V

−10

μA

LKG−SWD

V

Serial Wire Debug

VDDIO = 1.7 V to 5.5 V,

Iout = −2 mA

VDDIO−0.5 V

V

OH−SWD

Output Voltage High

V

Serial Wire Debug

Output Voltage Low

VDDIO = 1.7 V to 5.5 V,

Iout = +4 mA

0.4 V

OL−SWD

RESET

RESET_N_VIL1

Low level input voltage

VDD = 2.8 V to 5.5 V

0.3 x VDD

V

RESET_N_VIH1 High Level Input Voltage

0.7 x VDD

−120

RESET_N_RPU

Internal Pull−Up Resistor to VDD

100

kW

μA

RESET_N_ILKG Input Leakage

GPIO

VI

High Level Input Voltage

Low level input voltage

Output High Voltage

VDDIO = 1.7 V to 5.5 V

0.7 x VDDIO

VDDIO−0.5

V

H−GPIO

IL−GPIO

V

0.3 x VDDIO

0.4

V

VDDIO = 1.7 V to 5.5 V,

Iout = −2 mA

OH−GPIO

V

Output Low Voltage

VDDIO = 1.7 V to 5.5 V,

Iout = +4 mA

V

OL−GPIO

V

Output High Voltage

for PA4 and PA8

VDD = 2.8 V to 5.5 V,

VDD – 0.5

V

OH−NTC

Iout = −2 mA

V

Output Low Voltage

for PA4 and PA8

VDD = 2.8 V to 5.5 V,

Iout = +4 mA

0.4

OL−NTC

V

Input Hysteresis

VDDIO = 1.7 V to 5.5 V,

3.6 V Typ

300

mV

mA

HYS−GPIO

I

Input Leakage

VDDIO = 1.7 V to 5.5 V,

Input Voltage 0 V to 5.5 V

−5

5

IN−GPIO

I

Off Input Leakage

VDDIO = 0 V,

VDD = 0 V to 5.5 V

Input Voltage 0 V to 5.5 V

OFF−GPIO

R

Pull−Down resistance

Pull−up resistance

Pin Capacitance

PORT_PDx = 1

PORT_PUx = 1

100

5

kW

pF

PD−GPIO

PU−GPIO

C

GPIO

2

I C I/O

I

VDD current when SDA or SCL

is HIGH

VDD = 2.8 V to 5.5,

VIN = 1.8 V

−10

1.2

10

μA

V

CCTI2C

I

Input Current of SDA and SCL Pins

VDD = 2.8 V to 5.5,

VI = 0 to 5.5 V

I2C

V

High−Level Input Voltage

VDD = 2.8 V to 5.5 V

IH−I2C

www.onsemi.com

9

FUSB15201

Table 6. ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at V = 2.8 V to 5.5 V, T = −40°C to +105°C unless otherwise noted.

DD

A

Typical values are at T = 25°C, V = 3.3 V

A

DD

Symbol

Parameter

Conditions

Min

Typ

Max

Units

2

I C I/O

V

Low−Level Input Voltage

VDD = 2.8 V to 5.5 V

0.4

0.3

V

IL−I2C

V

Low−Level Output Voltage at 3mA

Sink Current (Open−Drain)

0

OL1−I2C

OL2−I2C

HYS−I2C

V

Low−Level Output Voltage at 2mA

Sink Current (Open−Drain)

VDD = 2.8 V to 5.5 V

0.3

V

Hysteresis of Schmitt Trigger Inputs VDD = 2.8 V to 5.5 V

0.1

20

0.2

V

I

Low−Level Output Current

(Open−Drain)

VDD = 2.8 V to 5.5 V,

V_OL = 0.4 V

(Note 5)

mA

OLSDA

V

INT_N Output Low Voltage

VDD = 2.8 V to 5.5 V,

I_OL = 4 mA

0.4

50

V

OL_INT

C

Capacitance for Each I/O Pin

VDD = 2.8 V to 5.5 V

5

pF

ns

I−I2C

t

SP

Pulse Width of Spikes that Must Be

Suppressed by the Input Filter

0

V

High−Level Input Voltage

Low−Level Input Voltage

VDD = 2.8 V to 5.5 V

1.2

V

IH_INT

V

0.4

IL_INT

FLASH

NEND

Sector Endurance

Data Retention

20,000

Erase/

write

cycles

T

DR

T = 25°C

T = 105°C

T = 125°C

100

20

years

10

5. (20 mA guaranteed over −40°C to 85°C)

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10

FUSB15201

Arm Cortex−M0+ Processor

source interrupts for peripheral devices. A powerful nested,

pre−emptive and priority based interrupt handling system

assures timely and flexible response to external events.

Low power features on FUSB15201 include the WIC,

adjustable clock rates, and different software controlled

power modes to maximize opportunities to save power in

the final application.

The FUSB15201 integrates an Arm Cortex−M0+

processor with Nested Vector Interrupt Controller (NVIC),

Wake−up Interrupt Controller (WIC), and Debug Access

Port (DAP). The processor uses the Thumb instruction set

and is optimized for high performance with reduced code

size and low power operation. The Arm Cortex−M0+

efficiently handles multiple parallel peripherals and has

integrated sleep modes. Test and debug capability is

enhanced with the Arm Serial Wire Debug Port.

Power Management Unit

The Power Management Unit (PMU) provides

appropriate power to all the blocks in the FUSB15201.

The FUSB15201 power management unit prevents

system brown−outs in case VDD voltage dips below

the specified minimum voltage required for reliable

operation. Firmware monitors the power supply and safely

shuts down the system as needed.

The Arm implementation in the FUSB15201 includes

a 132 kB Flash RAM and 6 kB of SRAM.

The MCU, Memory and DAP are interconnected using

the AMBA (Advanced Microcontroller Bus Architecture)

AHB−Lite interface and peripherals are connected to

the AHB via APB interface (Advanced Peripheral Bus).

In addition to the base Arm Cortex−M0+ processor

interrupts, the FUSB15201 implements multiple external

(2.8V−5.5V)

(1.7V−5.5V)

VDD

VDDIO

VDDIO Detect

VDDIO_GOOD

1.5V

Regulator

(VCORE)

VDD/

CAP

BRWN

V1P5

VDD_GOOD

Detect

VDD POR

LDO POR

V1P5_POR

POR

UVLO

Figure 4. FUSB15201 PMU

Reset Sources

The FUSB15201 has various sources of reset including:

• Watchdog Timer Reset – The watchdog timer reset

is caused by the watchdog timeout and is used to prevent

errant software from locking up the device. The watchdog

reset resets the entire chip including core, debug port,

peripherals, and watchdog. The watchdog timer

is disabled upon power up and must be enabled

by software. The watchdog is not paused when the

debugger halts the processor.

• External Pin Reset – The external reset is under user

control with the external RESET_N Pin. External pin

reset resets the entire chip including core, debug port,

peripherals, wakeup timer, and watchdog.

• Internal Power−On Reset (VDD_POR)

– The

VDD_POR reset asserts when the regulated supply is

below threshold levels for proper operation. The

VDD_POR resets the entire chip including core, debug

port, peripherals, wakeup timer, and watchdog.

• Software Issued Reset – The software reset can be called

by writing to a given register in the Cortex address space.

It is typically called on exit from a processor exception.

Software reset resets the entire chip including core,

peripherals, wakeup timer, and watchdog.

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11

FUSB15201

Power and Sleep Behavior

Serial Wire Debug Interface (SWD)

The FUSB15201 has been optimized to conserve power

by utilizing peripheral interrupts and hardware autonomy.

The device can be configured via firmware to enter low

power states, disable unneeded peripherals and scale clock

frequencies based on different application needs.

The Type−C block is designed to function at the lowest

power states and will automatically wake when a Type−C

attach is detected. This minimizes total power consumption

when no device is attached.

The Arm M0+ implementation includes a Debug Access

Port (DAP). The debug mode implementation includes

4 hardware breakpoints and 2 hardware watch points.

The Debug Access Port interface implementation is

the Arm Serial Wire Debug Port (SW−DAP) connected

to Pins SWCLK and SWDIO. The Serial Wire Debug Port

Interface uses a single bi−directional data connection. Each

operation consists of three phases: Packet request,

Acknowledge response, and Data transfer phase. Use any

Serial Wire Debug (SWD) compliant hardware debugger

interface to interact with the internals of the FUSB15201.

Clock Sources

FUSB15201’s implements a dual oscillator architecture

to minimize power consumption.

• A 24 MHz internal RC oscillator to enable full

functionality.

• A 120 kHz internal RC oscillator that can be used for very

low power sleep modes.

TIMERS

32−bit General Purpose Timers (TIM0/1)

There are two 32−bit down−counters that generate

interrupts and status when the counter reaches 0. The timing

resolution depends on the programmable clock source and

pre−scale ratios.

32−bit Wake−up Timer (WUT)

The main purpose of the wakeup timer is to facilitate

scheduled exit from low power modes. It can also be used

for general purpose event timing.

32−bit Watchdog Timer (WDT)

The watchdog timer applies a reset to the system in the

event of a software failure, providing a way to recover

from software crashes. The watchdog timer is disabled

by default and must be enabled through software.

The watchdog is protected with a lock mechanism

to prevent rogue software from disabling the watchdog

functionality. A special value has to be written to the lock

register to access watchdog control. The watchdog timer is

clocked from the same oscillator as the core, which can be

LS_CLK or HS_CLK.

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12

FUSB15201

USB Type−C & PD Peripheral Overview

The USB Type−C and PD peripheral is a fully compliant

USB Type−C and PD solution.

This peripheral consists of an analog front end and a

digital state machine. Firmware implements the higher level

protocol and policy layers whereas the analog and digital

components can perform lower level PD protocol and PHY

layer functions.

The Type−C block includes all terminations and

comparators required for Source/Sink/DRP operation: plug

orientation detection, power capability advertisement

and power role detection. If no VDD is applied, the CC Pins

are high impedance.

VCONN Switch

VDD

Type−C Terminations

CC1

CC2

vdd

CC State Machine &

Comparators

LV REG

USB PD PHY

Timers

ADC

BMC

Rcvr

ARM

M0+

BMC

DRIVER

CRC32Tx

BMC

4B5B

SRAM

6KB

Encode

Type−C

USB PD

CDR

BMC

4B5B

Decode

Flash

132KB

CRC32Rx

Figure 5. USB Type−C and PD

VCONN Switch

VBUS Discharge

Some applications require that a VCONN voltage be

sourced in order to provide additional capabilities, such as

greater than 3 A VBUS sourcing or support for full−featured

Type−C cables.

The FUSB15201 can provide 1.5 W or more depending on

VDD level.

The FUSB15201 is able to discharge VBUS via selectable

pull−down resistors.

Typical source applications will rely on the DC−DC

converter to transition between VBUS voltages.

If the application requires the FUSB15201 to discharge

VBUS, the firmware may select the proper resistance

of the discharge. Selection of discharge resistance needs to

take into account any capacitive load on VBUS as not to

violate VsrcSlewNeg in the USB PD spec (30 mV/ms).

Source applications, where the FUSB15201 internal

discharge is utilized, will have to isolate any large bulk

capacitances in order to prevent extreme internal

temperature rises. Typical isolated source capacitances

are around 4.7 mF.

USB PD PHY State Machine Logic

The FUSB15201 PD module includes the following

digital functions to enable USB PD messaging:

• Serialization and de−serialization

• Clock and data recovery (CDR)

• 4B5B coding

• BMC coding

The FUSB15201 is capable of discharging up to 100 mF

from VBUS in the entire operating range.

• Packet CRC generation and checking

• Coding and detection of Power Delivery K−Codes

• Automatic GoodCRC packet response

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13

FUSB15201

Connector Moisture Detection

INTERNAL PROTECTION

If moisture or pollutants are present in the connector

and the device provides VBUS, there could be a resistive

short between VBUS and other connector Pins.

The FUSB15201 provides a method to detect if there is

moisture or other pollutants in the connector.

The FUSB15201 integrates multiple system level

protections to enable robust designs.

VCONN Over−Current Protection

Each port’s VCONN Switch provides over−current

detection and protection for the switch that is enabled based

on the Type−C orientation and can be software configured

based on application needs. The level of OCP can be

controlled via a register setting.

Moisture detection can be turned on or off as not

to conflict with cable attach detection.

VSRC_MOS

In case of an over−current event the switch will be opened.

RPU_MOS

CC, DP, DM Over−Voltage Protection

Over−voltage protection on connector Pins protects

the internal circuitry damage from high voltages.

Interrupts can be used to inform the software that an OVP

event has occurred and take appropriate actions.

To ADC

HVDP

OVP

Figure 6. Moisture Detection

Internal Over Temperature Protection

Internal over temperature protection is always on. Two

potential sources of elevated internal temperature are:

• High Current through VCONN Switch

• High current through VBUS discharge

Port Control and GPIOs

The FUSB15201 includes a number of Pins that can be

configured to be used as standard GPIO or for use with

2

a dedicated peripheral such as I C. A subset of these Pins

In either case, if the over temperature is triggered

(T > Tshut), both ports’ VCONN switches and VBUS

discharge circuitry will be disabled.

can also be connected as an input to the ADC. Internal

pull−up/down resistors are programmable. Pull−up resistors

are always connected to VDDIO.

VDDIO

RPU

PORT_PUx

Analog

Peripheral

GPIO

MUX

PAx

PORT_PDx

PORT_CFGx

RPD

GND

Figure 7. Typical Port Configuration

www.onsemi.com

14

FUSB15201

External Temperature Measurements

When the PORT is configured as GPIOs it will have

the following capabilities:

• Bi−directional capability

• Push pull or open drain configuration

• Individually configurable interrupt lines

• Rising or Falling edge interrupt

• High or Low level interrupt

There are two Pins that can be configured to monitor

external NTC resistors that can be located near where high

temperature devices are located. A parallel resistor is

recommended for measurement linearity.

These NTC measurements are useful for reporting Source

temperatures to a Sink device via FUSB15201 provided PD

Status messages. Other uses include protection due

to excessive thermals and dynamic power capabilities

reduction.

Firmware implementation of the external temperature

measurements make NTC selection flexible.

The pull−up current sources INTCA and INTCB provide

a bias to the external NTC resistor networks. If desired, this

current source may be turned−off.

The port mapping and power domain is shown in the table

below:

Table 7. PIN − PORT CONFIGURATION

AND POWER DOMAIN

Power

Domain

VDDIO

VDD

Pin #

Name

GPIO1

SWCK

GPIO2

SWD

Port

7

PA1

INTCA

8

PA2

ADC_CH3

NTC_A/GPIO8

MUX

GPIO

R_PAR

9

GPIO3

GPIO4

NTC_B

I2C_INT

GPIO5

I2C_SDA

GPIO6

I2C_SCL

GPIO7

GPIO8

NTC_A

PA2

PA4

R_NTC

19

PORT_CONFIG

VDD

INTCB

20

21

22

24

PA5

PA6

PA7

PA8

VDD

ADC_CH7

VDDIO

VDD

NTC_B/GPIO4

MUX

GPIO

R_PAR

R_NTC

VDDIO

VDD

PORT_CONFIG

VDDIO

VDD

Figure 8. External NTC Diagram

www.onsemi.com

15

FUSB15201

BC1.2 Support

I²C

The FUSB15201 is capable of emulating and detecting

BC1.2 and Divider Mode.

The following modes are supported:

The FUSB15201’s serial interface is compatible with

2

Standard, Fast, and Fast Mode Plus I C bus specifications.

2

The I C peripheral can be configured for either host or

device modes.

• SDP

• CDP

• DCP

Bus Timing

As shown in figure below, for data bits, SDA must be

stable while SCL is HIGH. SDA may only transition when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

• 2.4 A Divider Mode (Provider only)

The analog circuitry is firmware configurable for the

function required by the application and follows the final

BC1.2 specification.

V

IL =

0.3 V

DD

V

IH =

0.7 V

DD

Figure 9. I²C Bus Timing Definition

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH.

During a read from the FUSB15201, the host issues

a Repeated Start after sending a data command and before

resending the device address. The Repeated Start is a 1−to−0

transition on SDA while SCL is HIGH.

A transaction ends with a STOP condition, which is

defined as SDA transitioning from 0 to 1 with SCL HIGH.

1

2

Bus timing referenced from I C−bus specification Rev. 6 – 4 April 2014

www.onsemi.com

16

FUSB15201

ADC

voltages, two NTC temperature channels, two D+/D− BC1.2

The FUSB15201 allows for up to 12 signals to be

measured and converted using the internal 10−bit ADC.

For most applications, this will consist of two VBUS

and, optionally, two CC1/2 ports. The table below shows

the typical FUSB15201 configuration along with the

expected settings for the ADC module.

Table 8. ADC CONFIGURATION

ADC Channel

Pin Measurement

Resolution

10 mV

20 mV

40 mV

4 mV

Range

Full Scale Voltage

1.024 V

2.048 V

4.096 V

1.28 V

0

VBUS_A

0 V to 10.23 V

0 V to 20.46 V

0 V to 40.92 V

0 V to 4.096 V

0°C to 160°C

0 V to 4.096 V

0 V to 10.23 V

0 V to 20.46 V

0 V to 40.92 V

0 V to 4.096 V

0°C to 160°C

0 V to 4.096 V

1

2

3

4

5

6

DP_A

DM_A

4 mV

NTC1 Temperature

HVCC1_A

HVCC2_A

VBUS_B

1°C

4 mV

4.096 V

1.024 V

2.048 V

4.096 V

1.28 V

4 mV

10 mV

20 mV

40 mV

4 mV

7

8

DP_B

DM_B

4 mV

9

NTC2 Temperature

HVCC1_B

1°C

10

11

4 mV

4.096 V

HVCC2_B

4 mV

Development Tools

FUSB15201 is supported by a full suite of comprehensive

Specifications References

• Universal Serial Bus Power Delivery specification

revision 3.1 Version 1.3, dated January 2022

• Universal Serial Bus Type C Cable and Connection

Specification release 2.1, dated May 2021

tools including:

• An easy−to−use development board

• Software Development Kit (SDK) including:

USB PD protocol stacks, shared capacity algorithms,

sample code, libraries, and documentation

• USB Battery Charging Specification, revision 1.2,

dated December 7, 2010

2

• I C−bus specification Rev. 6 – 4 April 2014

Arm, Cortex, and the Arm logo are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.

onsemi is licensed by the Philips Corporation to carry the I2C bus protocol.

www.onsemi.com

17

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

QFNW24 4x4, 0.5P

CASE 484AU

ISSUE O

DATE 07 AUG 2020

GENERIC

MARKING DIAGRAM*

XXXX = Specific Device Code

= Assembly Location

WL = Wafer Lot

= Year

WW = Work Week

*This information is generic. Please refer to

A

XXXXXX

AWLYWW

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Y

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON24253H

QFNW24 4x4, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

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under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

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


型号：	FUSB15201VMNWTWG
厂家：	ONSEMI
描述：	Integrated Dual Port USB Type-C & PD Source Controller 光电二极管
文件：	总19页 (文件大小：591K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FUSB15201VMNWTWG [ONSEMI]

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